JP3098720B2 - Synchronization circuit for mobile station - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a PHS (Personal
The present invention relates to a mobile communication system such as a handy phone system, and particularly to a synchronization pull-in circuit used in the mobile station.

[0002]

2. Description of the Related Art A mobile communication system generally includes a fixedly disposed base station and a mobile or portable mobile station, and wireless communication is performed between the base station and the mobile station. Is done. Since there is a physical restriction on radio wave propagation in a range where a mobile station can receive a signal wirelessly transmitted from a base station, usually, a large number of base stations are dispersedly arranged in an area to be a service area, and these base stations are distributed. The method of covering this area by the whole station is used. In particular, PHS
Provides a substantial service area mainly in urban areas by distributing a large number of relatively low power base stations and densely distributing them.

Since the mobile station can be moved or carried as described above, the position of the base station as viewed from the mobile station, and the state of receiving signals from the base station, change sequentially as the mobile station moves. To go. Therefore, the mobile station is generally configured to constantly or at a predetermined frequency monitor the surrounding radio wave propagation state and select a base station that can expect the best signal reception state. For example, as the mobile station moves from the coverage area of a certain base station to the coverage area of another base station, it is common to switch the wireless communication partner from the certain base station to the other base station (so-called handover). ). Like PHS,
In a system in which wireless communication between a base station (CS) and a mobile station (PS) is executed in a time-division manner, a time slot related to a certain CS (each time-division signal transmission period is referred to) in handover. The operation state of the PS is switched from a state synchronized with a time slot related to another CS to a state synchronized with a time slot related to another CS. In addition to the resynchronization at the time of such handover,
PS is CS including so-called switching back and self-service mode
Since a process for ensuring synchronization with a signal from a PC is frequently executed, how to perform synchronization pull-in quickly and accurately is an important issue in the PHS. It should be noted that a similar problem can generally occur in mobile radio systems that generally require synchronization.

FIG. 4 shows an outline of a synchronization pull-in circuit conventionally used in the PS of the PHS. In PHS,
A signal transmitted between the PS and the CS via the air is scrambled by a pseudo-noise code for the purpose of improving confidentiality of communication contents and the like, and a π / 4DQPSK (Differe
ntial Quadrature Phase Shift Keying) modulated. The receiver 10 receives a radio signal from the CS and performs frequency conversion, amplification, and the like. π / 4DQPSK modem 12
Converts the signal supplied from the receiver 10 into π / 4DQPSK.
After demodulation, the descrambler 14 descrambles the π / 4DQPSK demodulated signal. The data reproduced as a result of the descrambling is supplied to a circuit (not shown) on the one hand for provision to a carrier or the like, and is supplied to the CRC decoder 16 on the other hand. The CRC decoder 16 receives, from the data received from the CS via the receiver 10, the π / 4 DQPSK modem 12 and the descrambler 14, the I
TU-T 16-bit CRC (Cyclic Redundancy Check)
) Decode the code. The CRC decoded by the CRC decoder 16 is subjected to a match determination (not shown) or the like, thereby detecting data errors or the like. The descrambler 14 and the CRC decoder 16 among the above members are
It is a part of a circuit that performs processing such as demodulation and decoding of a signal received from CS via a wireless channel and further converted to baseband. This circuit is called a channel codec 18 together with functions such as coding and modulation (not shown).

In synchronizing the PS with the signal from the CS, a signal transmitted from the CS via a control radio channel (control channel) is used. In that case, first,
The CPU 20 in FIG. 4 operates the receiver 10 and the π / 4DQPSK modem 12 (start of “detection operation” in FIG. 5),
Data is sequentially fetched from the descrambler 14 via the buffer 22. The CPU 20 selects one that satisfies a predetermined connection condition from among the CSs that the receiver 10 can receive a signal (for example, selects a CS for which a data error has not been detected by a circuit (not shown)) and sends the CS to that CS. Is started (the start of the "pull-in operation" in FIG. 5). The slot timing generator 24 detects the arrival of a slot using the output of the CRC decoder 16. Each time the slot timing is detected by the slot timing generator 24 after the start of the pull-in operation, the CPU 20 sends the same CS-ID as the base station identification code (CS-ID) unique to the selected CS via the buffer 22. Check if it is included in the data.
At that point, the CPU 20 sets the receiver 10 and the π / 4DQPSK to end the retraction operation.
A command is given to the modem 12 to interrupt its continuous operation ("slot synchronization stop" in FIG. 5). Thereafter, before the "slot synchronization stop", the slot timing generator 2
The synchronous operation using a timing loop from the slot timing generator 24 to the receiver 10 and the π / 4DQPSK modem 12 is performed so that the receiver 10 and the π / 4DQPSK modem 12 operate at predetermined intervals from the arrival of the slot detected by the receiver 4. Be executed.

[0006] The PHS includes a public system in which a CS provided at a station or the like and an unspecified number of PSs communicate with each other, and a specific CS provided at a factory or the like and a predetermined PS.
There is a self-employed system that communicates with. The above CS-
As shown in FIG. 6, the configuration of the ID differs depending on whether it is for public use or for private use. Further, the PS-ID, that is, the identification code for specifying the PS called by the CS is transmitted together with the CS-ID.

One of the problems with the conventional circuit is that the CPU 20
Therefore, it takes a certain amount of time until the pull-in operation is stopped after the slot timing generator 24 detects the arrival of the slot related to the CS to be synchronized. On the other hand, in the synchronization operation, a reception operation and the like are executed at predetermined intervals, starting from the arrival of the slot detected by the slot timing generator 24 last before “slot synchronization stop”. Therefore, as shown in FIG. 7, after the arrival of the slot related to the CS to be synchronized is detected by the slot timing generator 24, the arrival of the slot related to another CS does not occur until the pull-in operation is stopped. When detected by the slot timing generator 24,
It erroneously synchronizes with the other CS. In this case, a signal from the CS generally tends to cause a data error, and after all, the procedure of FIG. 5 must be executed again. This hinders handover and other high-speed operations.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for handover in a public system by enabling a stop of a synchronization pull-in operation and a transition to a synchronous reception operation immediately after detecting the arrival of a signal from a base station. , Switching back, receiving a call in the private system, and the like can be performed more quickly than before.

[0009] To achieve this object, the present invention
Is identified as the synchronization pull-in circuit for mobile station mounted on the mobile station.
A sign comparator and a slot timing generator are provided.
The self-running operation of the reset timing generator allows
Prevents synchronization destination errors due to processing delays in PU etc.
In. That is, the present invention provides (1) a predetermined slot-to-slot
Times related to other base stations periodically with a tarball
Generally, each base station creates a lot asynchronously and
Move the base station identification code unique to that base station from that base station
Of the time slots used to transmit to the station
A mobile station responds to a time slot related to a base station.
Installed in the mobile station to synchronize the
In the mobile station synchronization pull-in circuit,
Data received during the period when the
Shift in synchronization with the clock recovered from the data
Shift register to hold while synchronization
Registers for holding base station identification codes related to lots,
The contents of these registers and shift registers
Detects that both match by comparing
Code comparator having a group of comparators, and (3) an identifier code
When a match is detected by the signal comparator
The reception demodulation operation is performed between the above-mentioned continuous execution and
Slot to shift to synchronous operation with interval as cycle
And a timing generator. More preferred
(4) The identification code comparator includes a register and a serial
Out of the corresponding bit strings in the bit register
Identify bits to be excluded from target and match decision basis
A mask register for storing information;
In the group of units, the bits specified by the mask register
Such a comparator is a register and a corresponding register on the shift register.
The two must always match, regardless of the content of the
And outputs the signal indicating (6)
Are some bits of the register and shift register
Bit comparison of the contents of
The slot timing is detected
In response to this, perform the transition to the synchronous operation.
And

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. Note that the same reference numerals as those in the prior art shown in FIGS. 4 to 7 are used to omit redundant description, but this means that members having exactly the same functions as those in the prior art must be used. Not something.

FIG. 1 shows a configuration of a PS pull-in circuit according to an embodiment of the present invention. In the circuit of this figure, an identification code comparator 26 is shown in place of the buffer 22 and the CPU 20, and the identification code comparator 26 is used together with the CRC decoder 16 and the slot timing generator 24.
Are used as the slot synchronization circuit 28. As shown in FIG. 2, the identification code comparator 26 has registers 26a and 26b, shift registers 26c and 26d, mask registers 26e and 26f, a comparator 26g, and an OR gate 26h.

The registers 26a and 26b are respectively
The CS-ID of the CS to be synchronized and the PS-ID to be transmitted from the CS are set in the register. The shift registers 26c and 26d are registers in which data to be sequentially received is set. The reproduced clock in the figure is a clock reproduced from the received data by a circuit (not shown), and provides the timing for storing the received data from the descrambler 14 in the shift registers 26c and 26d and bit-shifting the same. Comparator 2
6g is provided corresponding to each bit of CS-ID and PS-ID (accordingly, a total of 70 in the configuration of FIG. 6).
When each bit data on the shift registers 26c and 26d matches the corresponding bit data on the registers 26a and 26b, a "0" value is output. That is, C from the CS to be synchronized on the shift registers 26c and 26d
When the S-ID and the PS-ID exist, a “0” value is output. Note that the comparator 26g has, for example, the configuration shown on the lower side of FIG. The setting of the CS-ID and PS-ID on the registers 26a and 26b may be performed by means such as transfer from the shift registers 26c and 26d according to the determination of the synchronization destination CS (desired wave) by a CPU or the like (not shown). .

The OR gate 26h calculates the logical sum of the outputs of all the comparators 26g and supplies the result to the slot timing generator 24 as a coincidence signal. That is, all comparators 26
Since the output of the OR gate 26h becomes the “0” value only when the “0” value output is obtained from g, the OR gate 26h
Is "0", the shift register 26
All bit data on c and 26d match the corresponding bit data on registers 26a and 26b, respectively.
In other words, it can be considered that the CS-ID and the PS-ID from the CS to be synchronized have been captured, so that the synchronous reception operation at a predetermined interval by the slot timing generator 24 can be started. Also, the mask registers 26e and 26f are provided with an optional comparator 26g if necessary.
Is a register for forcibly setting the output of the comparator 26 to the value "0". When the output of the comparator 26g relating to a certain bit is to be set to "0", "0" is set in the mask register 26e or 26f for that bit. deep. Thereby, the output condition of the coincidence signal can be eased.

In this embodiment, first, when a synchronization destination CS is determined by a CPU (not shown) as in the prior art, the registers 26a and 26b, which are features of this embodiment,
The S-ID and PS-ID are set, the detection operation A in FIG. 3 ends, and the pull-in operation C starts. After this time point B, at the time point D when a match signal is obtained from the identification code comparator 26 having the above-described configuration, the slot timing generator 24
Stops the continuous reception / demodulation operation by the receiver 10 and the π / 4 DQPSK demodulator 12, and thereafter, the slot timing generator 24 generates an inter-slot interval (625 μs in PHS) by counting the reproduction clock,
The receiver 10 and the π / 4D are set so that the synchronous reception operation E is performed.
Trigger the QPSK demodulator 12 (self-running operation of the slot timing generator 24). Therefore, unlike the prior art, no problematic processing delay occurs, and the pull-in operation C continues until a coincidence signal of “0” value is obtained.
It is possible to quickly shift to the synchronous receiving operation without erroneous synchronization. Further, since the output of the identification code comparator 26 is synchronized with the bit, the above-described trigger operation causes the π / 4DQ
The PSK demodulator 12 can hold the bit phase. As a result, bit errors after shifting to the synchronous reception operation are less likely to occur.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an identification code comparator according to the embodiment.

FIG. 3 is a time chart showing a synchronization pull-in procedure in this embodiment.

FIG. 4 is a block diagram illustrating a configuration of a circuit according to the related art.

FIG. 5 is a time chart showing a synchronization pull-in procedure according to the related art.

FIG. 6 is a diagram showing a configuration of a CS-ID and a PS-ID in a PHS.

FIG. 7 is a time chart showing a problem of the related art.

[Explanation of symbols]

24 slot timing generator, 26 identification code comparator, 26a, 26b register, 26c, 26d shift register, 26e, 26f mask register, 28 slot synchronization circuit.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masaru Mitobe 5-1-1 Shimorenjaku, Mitaka-shi, Tokyo Japan Radio Co., Ltd. (72) Yuko Kashino 5-1-1 Shimorenjaku, Mitaka-shi, Tokyo Sun (56) References JP-A-6-120922 (JP, A) JP-A-6-104893 (JP, A) JP-A-6-13968 (JP, A) JP-A-4-373330 ( JP, A) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H04B ^7/ 24-7/26 H04Q ⁷ /04-7/38

Claims (2)

(57) [Claims] The present invention relates to a method for controlling a slot at a predetermined interval between slots.
Periodically and for time slots related to other base stations
In general, each base station creates the data asynchronously, and
To transmit the base station identification code from the base station to the mobile station
One of the used time slots
Reception demodulation operation in mobile station for such time slot
Synchronization for mobile stations installed in mobile stations.
In the embedded circuit, the reception is performed during the period in which the reception demodulation operation is continuously performed.
Data synchronized with the clock recovered from the data.
Shift register to hold while shifting, synchronization destination
Register holding a base station identification code related to the time slot of
And the contents of these registers and shift registers
Are compared by bit comparison with each other.
An identification code comparator having a comparator group for detecting that a match has been detected by the identification code comparator.
Thus, the reception demodulation operation is performed from the continuous execution to the slot execution.
Shift to synchronous operation with interval between packets
A synchronization pull-in circuit for a mobile station , comprising: a slot timing generator . 2. A synchronization pull-in circuit for a mobile station according to claim 1.
In the above, the identification code comparator includes a register and a shift register.
The bit comparison target and the match
Stores information specifying bits that should be removed from the fixed basis
Having a mask register, of the comparator group specified by the mask register
Comparators related to bits are on registers and shift registers
Regardless of the contents of the corresponding bits of
Is output, indicating that the identification code comparator has a register and a shift register.
The bit contents of some of the bits in the
By detecting that both match partially,
The slot timing generator responds accordingly to the synchronization
Mobile station synchronization characterized by performing a transition to operation
Retraction circuit.