JP3095638B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a magnetic disk drive and the like.
And a data processing device having the disk storage device .

[0002]

2. Description of the Related Art As a method of accessing a disk storage device such as a magnetic disk device at a high speed, there is a so-called elevator seeking method. This means that one file is not stored in a continuous sector, and data dispersed in a plurality of areas of the disk is moved to the sector closest to the current head position or the head in one direction to move the data to the current position. This is a method of changing the order of access so that data can be accessed by moving in the sector closest to the head position or in the direction of the head position.

[0003] According to this method, it is possible to avoid re-seeking for each file, to avoid seeking a distributed file by accessing each block, or to make a file exist in a continuous block even if it is a different file. In this case, the speed can be increased because continuous access can be performed by one seek (see Japanese Patent Application Laid-Open No. 2-7273).

That is, as shown in FIG. 11, when a read request is issued to a magnetic disk device in which files are stored in the order of files C, A, and B, access is normally performed while seeking in this order. Here, since file A is distributed to A1 and A2, a total of 4
The seek of times enters. However, by performing the above-described elevator seeking, access is performed in the order of A1, B, A2, and C. Since B and A2 are continuous, only three seeks are required, and the seek distance is short. Fast access. In another method of elevator seek, since access from A2 to C is faster than continuous access than from seek, A1, B, A2, Z, X,
Two seeks are sufficient for access in C order.

[0005]

By the way, as described above,
According to the conventional elevator seeking, only sequential addresses can be generated. Therefore, first, a continuous area on the memory is secured, and data read by the elevator seeking is sequentially stored in the memory.

However, since data stored in the memory is not always stored in one file, it is necessary to perform a rearrangement process by the CPU.

That is, as shown in FIG. 12, for example, the files B and A2 can be accessed continuously, and therefore are stored in the continuous space of the memory as they are. Therefore, in order to make A1 and A2 continuous in the memory, it is necessary to perform rearrangement by the CPU.

Further, according to the conventional method, if there is unnecessary data in the middle of elevator seeking, seek is performed, or as shown in FIG. 13, unnecessary data is directly read and stored in a memory. The access is slowed down or an extra memory area is required. In general, a continuous area is not always empty in the memory, so it is necessary to secure a continuous area by moving data or performing garbage collection.

Accordingly, the present invention is capable of continuously storing data in a predetermined order on a memory even if the disk storage device is accessed sequentially without randomly accessing the disk storage device. It is an object of the present invention to provide a data processing device capable of reducing the processing of the above.

[0010]

A data processing apparatus according to the present invention.
Is used to translate memory logical addresses to physical addresses.
Specify the mapping data address used for
Specify an access-prohibited address among the
CPU to be specified, and the above-mentioned map specified by the CPU.
Ping data address mapping table
Provided memory and disk storage device for storing data
And the disk storage device is a continuous one-way head
Data in sector units read by the
D that outputs the logical address of the memory
MA transfer means and logic output from the DMA transfer means
Logical address read from the mapping table.
Convert to physical address based on ping data address
And outputs the converted physical address.
Mapping data stored in the mapping table
Access prohibition specified by the CPU among the dresses
Output access prohibition signal when address matches
Address translation means, and the output from the address translation means.
From the DMA transfer means based on the physical address
Write the transmitted data on the memory and
When an access prohibition signal is output from the address conversion means
The data transferred from the DMA transfer means.
Writing control means for prohibiting writing to the memory.
It is prepared for.

[0011]

[0012]

[0013]

According to such a configuration, the disk storage device
Read by continuous head movement in one direction
The data for each sector is output from the address conversion means.
Stored in memory based on physical address. Accordingly
Data of one file on the disk storage device
No random access, even if they are not connected
Access to memory sequentially
Can be stored. In addition, from disk storage
Unnecessary data is included in the read sector unit data.
Access from the address translation means
Write the unnecessary data to the memory by the inhibit signal
To reduce the load of memory access.
Wear.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. 4, de of the present invention
FIG. 2 is a block diagram illustrating an example of a data processing device . The data processing device in the present embodiment includes a data transfer device 1,
It includes a CPU 2, a memory 3, and a magnetic disk device 4.
You. The data transfer device 1 includes a SCSI controller 14 ,
The DMA controller 12 includes an address converter 11 and a controller 13. The magnetic disk device 4 is connected to the SCSI controller 14 via a cable.

On the other hand, the control unit 13
Connected to U2. The memory 5 is connected to the bus 5 together with the CPU 2. Data transfer control device 1
Operate under the control of the CPU 2 and
Is transferred to the memory 3 or the memory 3
The data transfer control is performed by, for example, storing the data stored in the magnetic disk device 4.

The CPU 2 sets parameters necessary for disk access to the data transfer control device 1 via the bus 5. This parameter is sent to the SCSI controller 14, the DMA controller 12,
It is set in the address conversion unit 11 and the control unit 13.

The SCSI controller 14 controls a device conforming to the SCSI interface specification, and is connected to the magnetic disk device 4 via a SCSI cable. When reading data from the magnetic disk device 4, the SCSI
In accordance with an instruction from the controller 14, the head of the magnetic disk device 4 is moved to a logical address of a sector to be read, and data of a desired number of sectors is transferred from the logical address. When data is transferred from the magnetic disk device 4 to the SCSI controller 14, the SCSI controller 14 outputs a DMA request signal (hereinafter, a DREQ signal) to the DMA controller 12. Upon receiving the DREQ signal, the DMA controller 12 returns a DMA acknowledge signal (hereinafter, a DACK signal) to the SCSI controller 14 and stores the data in an internal register.

The DMA controller 12 is a device for directly transferring data between the I / O device and the memory without interposing a CPU, and transfers the received data to the memory 3. At this time, the DMA controller 12 acts as an address generation unit, generates an address according to the parameters set by the CPU 2, and outputs the generated address together with the data.

In this embodiment, the data output from the DMA controller 12 is sent to the control unit 13 and the address is sent to the address conversion unit 11 to send the data to the DMA controller 1.
After converting the logical address generated in step 2 into a physical address, the logical address is stored in the physical address of the memory 3 on the bus 5 via the control unit 13.

By repeating this process, data in the magnetic disk device 4 is read out and stored in the memory 3. When writing data to the magnetic disk device 4, the DMA controller 12 generates a logical address,
After being converted into a physical address by the address conversion unit 11, the control unit 13 issues a data read request to the memory 3 for the physical address.

When the memory 3 reads the data corresponding to the physical address, the data is transferred to the control unit 13 via the bus 5.
To finish the reading. This data is
It is sent to the MA controller 12 and latched. At this time, if the DREQ signal is output to the SCSI controller 14, the latched data is output to the SCSI controller 14 together with the DACK signal, and the SCSI controller 14 latches the data in the internal register, and the data to the magnetic disk device 4 is transferred. You.

Here, from the SCSI controller 14,
When the output of the DREQ signal is received, the data is transferred to the SCSI controller 14, and after the completion, the logical address is output again and a request for reading data from the memory 3 is issued.

Next, the configuration of the address conversion unit 11 of the device according to the present embodiment will be described. FIG. 5 is a block diagram illustrating a configuration of the address conversion unit 11. Address translation unit 1
1 is a physical address conversion unit 103 for converting a logical address to a physical address, a logical address register 100 for temporarily storing a logical address, and a logical address register 10
The comparator 101 compares the address stored at 0 with the logical address from the DMA controller 12, and the mapping data address for calculating an address on the memory 3 that stores a parameter called mapping data for converting the logical address into a physical address. Calculation unit 102 and mapping data address calculation unit 10 based on the result of comparator 101
A selector 106 for selecting an address from the address 2 and a physical address output from the physical address conversion unit 103;
An access prohibition address register 104 set by the CPU 2, a comparator 105 for comparing the access prohibition address set in the access prohibition address register 104 with a physical address, and an access prohibition permission for enabling the result of the comparator 105 And 107.

Here, the mapping data address calculation unit 102 for calculating the mapping data address is shown in FIG.
As shown in the figure, a base address register 11 for storing a base address of the memory 3 storing the mapping data.
1 and an adder 112.

Referring to the example shown in FIG. 9, when mapping data is stored from the address F00000000h on the memory 3, the CPU 3 stores the F in the base address register 111 via the control unit 13 via the control unit 13.
00000000h is written. The logical address from the DMA controller 12 is 00000000h at first, and the mapping data address as a result of the addition by the adder 112 is F00000000h, which is the base address. In this embodiment, the mapping unit is 4 KB.
Therefore, in the 32-bit address in byte units, the upper 20 bits are valid and the lower 12 bits are ignored.

Therefore, the logical address 000000
From 0h to 000000FFFh, the result of the adder 112 is F00000000h. Next, if the logical address is 00
When 001000h is reached, F00000000h and 000
000000004h and F0000004h.
This is because the mapping data to be stored is 32-bit data, and the address is added in units of 4h.

Thus, the logical address 000000
0h-000000FFFh is F00000000h, logical address 00001000h-00001FFFh
Is F0000004h, logical address 0000200
0h to 00002FFFFh are F0000008h, logical addresses 003000h to 00003FFFFh
Becomes F000000Ch.

Next, the physical address translator 103
As shown in (1), it comprises a mapping data register 113 and an address replacement unit 114, and converts a logical address into a physical address.

That is, the mapping address calculation unit 10
After the data stored in the mapping data address calculated in step 2 is read from the memory 3, the data is stored in the mapping data register. In FIG. 9, F000000
The address 0h contains 10000000h, which is stored in the mapping data register 113. Since the mapping is performed in units of 4 KB as described above, the upper 20 bits are replaced with the upper 20 bits of the logical address. That is, the logical address 00000000h ~
00000FFFh is 10000000h to 10000
FFFh.

In the case of the logical address 00001 *** h, the data at the address F0000004h 100100000
h is set in the mapping data register 113 and the replacement unit 114 sets the logical addresses 00001000h to 00
001FFFh is 10010000h to 10010FF
Fh.

Similarly, the logical address 0000200
0h-00002FFFFh is 1005000h-10
005FFFh, logical address 003000h-0
0003FFFFh is 10001000h ~ 10001F
The address is converted to FFh.

Next, the operation of the apparatus according to this embodiment will be described. FIG. 10 is a flowchart illustrating an outline of the operation of the data transfer control device according to the present embodiment.

In this embodiment, when there is a memory access request from the DMA controller 12, it is determined whether or not to perform the mapping process (S1). If not, the memory 3 is accessed as it is (S8). Then, an access end notice is issued to S12 (S9).

When performing the mapping process, first, it is checked whether mapping data is set (S
2) If not set, after calculating the mapping data address (S3), read the mapping data from the memory 3 (S4), map the logical address to the logical address register and map the mapping data read from the memory 3 It is set in a data register (S5), and a physical address is calculated (S6).

Next, it is checked whether or not the physical address matches the access prohibited address (S7). If not, the memory 3 is accessed with the calculated physical address (S8). Then, an end notification is issued to the DMA controller 12 without accessing the memory 3 (S9).

Hereinafter, the operation of the data transfer control device will be described in detail focusing on the operation of the address conversion unit 11. Here, a case where data from the magnetic disk device 4 is transferred to the memory 3 will be described.

FIG. 8 shows data of a physical address on the magnetic disk device 4. Now, assume that one sector is 4 KB, and data of four sectors at physical addresses (N) to (N + 3) are read out to the memory 3. The CPU 2 writes the mapping table on the memory 3 as data, as shown in FIG. That is, 4 bits from the base address F00000000h to F000000Fh of the mapping data
Write the word data.

This is because the data of the sector (N) is stored in the memory 3
The data of the sector (N + 1) is changed from 1000000h to 4 KB from 1000000h to 4 KB.
+2) data from 1005000 h to 4 KB, and sector (N + 3) data from 10001000 h to 4 KB.
Means to transfer.

Next, the CPU 2 causes the data transfer control device 1 to perform this transfer, and sets parameters in the data transfer control device 1. First, the logical addresses 00000000h to 000003 are provided to the DMA controller 12.
It is set to generate a byte address up to FFFh. This can be easily configured with a counter, an adder, and the like.

Subsequently, in the address conversion unit 11,
Base address F0000 storing mapping data
000h is set in the base address register 111. Further, in the present embodiment, since the data of the sector (N + 1) on the magnetic disk device 4 is not required,
The upper 20 bits 10010h of the mapping data indicating the above physical address are set in the access prohibition address register 104.

In order to perform data transfer by mapping, the mapping is enabled in the control unit 13 and the DM
The logical address register 100 is initialized to set the mapping data by comparison with the logical address from the A controller 12, and indicates that the mapping data has not been set in the mapping data register 113 at the start of the transfer.

The setting of the parameters from the CPU 2 is performed via the bus 5 and the control unit 13. next,
The CPU 2 instructs the SCSI controller 14 to send a SCSI command to the magnetic disk device 4 to read four sectors from the sector (N) of the magnetic disk device 4.

The reading is started as described above. When the first byte data of the sector (N) is transferred from the magnetic disk device 4 to the SCSI controller 14, it is stored in a FIFO register in the SCSI controller. S
As a result, the CSI controller 14 outputs a DREQ signal to the DMA controller 12.

The DMA controller 12 that has received the DREQ signal sends a DAC signal to the SCSI controller 14.
A read request signal is output simultaneously with the K signal, and 1-byte data is stored in a register in the DMA controller 12.

Next, the DMA controller 12 generates an address, outputs data from the latched register together with the address of 00000000h, and outputs the logical address 0.
A write request to 00000h is issued to the control unit 13. In response, first, the address conversion unit 11
The comparator 101 compares the logical address from the controller 12 with the address of the logical address register 100.

This is the first data. Since the logical address register 100 is initialized and no logical address is stored, the result of the comparator 101 does not match, and the mapping data access signal is controlled. Output to the unit 13.

In the mapping data address calculation unit 102, F0 set in the base address register 111
The logical address is added to 000000h by the adder 112, and the mapping data address 21 is changed to F00000000.
h is input to the selector 106.

Since the mapping data is accessed before the access by the physical address, the selector 106 outputs the mapping data address and passes it to the control unit 13 as the address 17.

The control unit 13 receives the read request from the DAM controller 12, but reads the mapping data first because the mapping data access signal 15 is input by the processing of the address conversion unit 11.

That is, the mapping data address F00000000h from the address conversion unit 11 is output to the bus 5 and a read request is issued to the memory 3. From memory 3, F
The data 10000000h of 00000000h is output, once received by the control unit 13, and the memory access ends. The upper 20 bits of this data are stored in the mapping data register of the physical address converter 103. At the same time as this processing is completed, the DMA controller 1
The logical address 00000000h from 2 is latched in the logical address register 100.

0000 is set in the logical address register 100
000h is stored, the result of the comparator 101 matches, and the selector 106
The physical address output from the control unit 03 is selected and sent to the control unit 13.

On the other hand, in the physical address conversion unit 103, the mapping data of the mapping data register 113 and the upper 20 bits of the logical address are replaced by the replacement unit 114, and the physical address 10000000h is replaced with the physical address 2
Output as 0.

In the comparator 105, the physical address 2
0 is compared with the value set in the access prohibition address register. The upper 20 bits of the physical address 20 are 10 bits.
Since it is not 010h, the access prohibition signal is disabled. Thereby, the control unit 13 accesses the memory 3 via the bus 5 so as to write 1-byte data to the physical address 10000000h, and stores the 1 byte of the sector (N) of the magnetic disk device 4 in the address of 10000000h of the memory 3. The eyes are written and the process ends. At this time, the control unit 13 and the DMA controller 12
Sent to

Next, the data after the second byte is the SCS
Since the data register of the I controller is a FIFO register, access to the memory 3 is asynchronously taken into the FIFO register in the SCSI controller until this register becomes full. If there is data to be transferred to the FIFO register, the data is written to the memory 3 as described above. However, the data after the second byte of the sector (N) has already been
00000000h in 1 logical address register 100
Is stored, the result of the comparator 101 becomes a match, the mapping data is not accessed, and only the writing to the memory 3 is performed.

The physical address 20 is 10000001h, 10000 as a result of the physical address conversion unit 103.
002h,... Next, a case in which data of sector (N + 1) has been obtained will be described.

The first byte data of the sector (N + 1) is transferred to the DMA by the DREQ signal of the SCSI controller 14.
When received by the controller 12, the logical address becomes 00
001000h is output, and a write request is issued to the control unit 13. However, in the address conversion unit 11, since 00000000h is stored in the logical address register 100 by comparison of the logical addresses of the comparator 101, they do not match, and a mapping data access signal is output.

In the mapping data address calculation unit 102, a part of the logical address is added to the base address register 111 in the same manner as described above, and the mapping data address 2
F000004h, which is 1, is generated. Selector 10
6 selects the mapping data address 21 and issues a read request from the control unit 13 to the memory 3, and as a result, the mapping data register 113
h is set.

As a result, the physical address conversion unit 103 generates the physical address 20 and sets 10010000h
Is output. At this time, the comparator 105 sets the 10010
Compare with h. As a result, since they match, an access prohibition signal is output. The control unit 13 receives the access prohibition signal and has received a write request from the DMA controller 12 to the memory 3, but does not access the memory 3 and notifies the DMA controller 12 of the end.

Thus, the data of the sector (N + 1) of the magnetic disk device 4 is read from the magnetic disk device 4 but is not written to the memory 3. Next, a case where data of sector (N + 2) has been described will be described.

When the DMA controller receives data in response to the DREQ signal of the SCSI controller 14, the logical address 00002000h is output and a write request is issued to the control unit 13.

However, in the address conversion unit 11, since the logical address of the comparator 101 compares 00001000h in the logical address register 100, they do not match, and the mapping data access signal 15 is output. The mapping data address calculation unit 102 adds a part of the logical address to the base address register 111 in the same manner as described above, and generates F0000008h, which is the mapping data address 21.

The selector 106 selects the mapping data address 21, and the control unit 13 sends the selected data to the memory 3.
A read request is issued, and as a result, 10005h is set in the mapping data register. At the same time, the logical address register 100 stores the logical address 0000.
2000h is latched.

As a result, the physical address conversion section 103 generates the physical address 20 and 1005000h
Is output. At this time, the comparator 105 sets 10010h in the access prohibition address register 104.
Compare with. As a result, the access prohibition signal is not output because they do not match.

Accordingly, the selector 106 outputs the physical address 1005000h, and outputs the sector (N +
The data of the first byte in 2) is 1000500 in the memory 3.
0h is written. Thereafter, 4 KB data including the first byte is written to the address of 10005 *** h.

Next, a case where data of sector (N + 3) is obtained will be described. D of SCSI controller 14
When the DMA controller receives the data by the REQ signal, the logical address of 003000h is output, and a write request is issued to the control unit 13.

[0066] However, in the address conversion unit 11, by comparing the logical address of the comparator 101, the logical address register 100 for 00002000h is stored, it becomes mismatched, mapping data access signal is output.

In the mapping data address calculation unit 102, a part of the logical address is added to the base address register 111 in the same manner as described above, and the mapping data address 2
F000000Ch which is 1 is generated. Selector 10
6 selects the mapping data address 21 and issues a read request from the control unit 13 to the memory 3, and as a result, 10001h is set in the mapping data register.

At the same time, the logical address register 100
, The logical address 003000h is latched. Thus, the physical address conversion unit 103 generates the physical address 20 and outputs 10001000h. At this time, the comparator 105 performs comparison with 10010h set in the access prohibition address register 104. As a result, the access prohibition signal is not output because they do not match.

Therefore, the selector 106 outputs the physical address 10001000h and outputs the sector (N +
The data of the first byte in 3) is 1000100 in the memory 3.
0h is written. Thereafter, 4 KB data including the first byte is written to the address 10001 *** h.

When the above transfer is completed, the DREQ signal is no longer output from the SCSI controller 14, and the data transfer control device 1 notifies the CPU 2 of the completion by an interrupt signal or the like. Thus, a series of data transfer processing ends.

Therefore, according to this embodiment, even if the data to be accessed is not continuous on the magnetic disk device,
Instead of randomly accessing the magnetic disk device, the magnetic disk device can be accessed sequentially and stored continuously in the memory, and the loss time due to random access can be reduced. In addition, if there is unnecessary data at the time of sequential access, access to the disk device is continued without accessing the memory, so that it is not necessary to secure a continuous free space in the memory. In the above embodiment, the data transfer control device 1 detects unnecessary data and does not transfer the data to the memory as an example. Can be configured.

In this case, the CPU specifies one address as a garbage area on the memory, and creates mapping data so that all unnecessary data is transferred to this garbage area.

Therefore, unnecessary data is overwritten one after another in the garbage area, and the data is stored in the effective area of the memory in a predetermined order in the same manner as in the above embodiment. In this case, the CPU specifies one address as a garbage area on the memory, and creates mapping data so that all unnecessary data is transferred to this garbage area.

Therefore, the unnecessary data is overwritten in the garbage area, and the data is stored in the effective area of the memory in a predetermined order as in the above embodiment. In this case, the data transfer control device 1 does not need the access prohibition address register 104, the comparator 105, the access prohibition permission means 107, etc. for generating the access prohibition signal, and the configuration of the device becomes simple.

In the above embodiment, a magnetic disk device has been described as an example of a disk device. However, the disk device may be another disk device such as an optical disk device or a magneto-optical disk device.

Therefore, it is possible to reduce the loss time due to random access of the disk storage device. Unnecessary data in the continuous data is transferred to a specific address on the memory 3 and overwritten one after another.

Therefore, necessary data is stored in an appropriate address of the memory 3 in an appropriate order without adding a particular structure, and unnecessary data is stored at a specific address different from the data. .

Further, the data in sector units read by the continuous one-way movement of the head from the disk storage device 4 is transferred to the address conversion means 11 of the data transfer control device 1.
Then, the logical address is converted into the physical address for each sector so as to be arranged in an arbitrary order on the memory. For this reason, continuous data read out from the disk storage device 4 and not necessarily arranged in order is stored in an appropriate address of the memory 3 in an arranged order.

Accordingly, it is possible to reduce a loss time due to random access of the disk storage device 4. In addition, the prohibiting means 105 prohibits the transfer of unnecessary data among the data to be sequentially output. In this case, the access to the disk device is continued without accessing the memory 3. Access load can be reduced.

[0080]

As described above, according to the present invention,
Since means for converting a logical address into a predetermined physical address in sector units is provided, even if one file is not continuous on the disk device, random access is not performed, and sequential access is performed on the memory without performing random access. Can be stored continuously. Therefore, the loss time due to random access can be reduced.
In addition, even if there is unnecessary data at the time of sequential access, access to the disk device is continued without seeking and no access to the memory is performed, so that the load on the memory can be reduced, thereby improving the system performance. It can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram for explaining the operation principle of one embodiment of the present invention.

FIG. 2 is a diagram illustrating the principle of a second embodiment of the present invention.

FIG. 3 is a diagram illustrating the principle of a third embodiment of the present invention.

FIG. 4 is a block diagram showing the principle configuration of a data transfer control device according to the present invention.

FIG. 5 is a block diagram showing an example of a configuration of an address conversion unit of the data transfer control device shown in FIG.

FIG. 6 is a block diagram showing a configuration of a mapping address calculation unit of the data transfer control device shown in FIG. 4;

FIG. 7 is a block diagram showing a configuration of a physical address conversion unit of the data transfer control device shown in FIG.

FIG. 8 is a diagram showing an example of a data storage state of the magnetic disk device.

FIG. 9 is a view for explaining a state of a data transfer control device when data on a magnetic disk device is transferred to a memory;

FIG. 10 is a flowchart showing the operation of the data transfer control device shown in FIG. 4;

FIG. 11 is a diagram showing a conventional elevator seek method.

FIG. 12 is a view showing a state in which data is transferred to a memory by the method shown in FIG. 11;

FIG. 13 is a diagram showing a state in which data is transferred to a memory by another elevator seek method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Data transfer control device, 2 ... CPU, 3 ... Memory, 4
... Magnetic disk device, 5 ... Bus, 11 ... Address conversion unit, 12 ... Address generation unit (DMA controller), 1
3 ... control unit, 14 ... SCSI controller.

Claims (1)

(57) [Claims] 1. A method for translating a logical address into a physical address.
Of the mapping data address used for
Access prohibited addresses among ping data addresses
A CPU for specifying said mapping data address specified by the CPU
With mapping table to hold addresses
And a disk storage device for storing data, and the disk storage device moves the head continuously in one direction.
DMA transfer of data in sector units read by
At the same time, the DMA conversion for outputting the logical address of the memory
Transmission means and the logical address output from the DMA transfer means.
Mapping data read from the mapping table
When converted to a physical address based on the
The translated physical address is
Of the mapping data addresses stored in the
Matches an address for which access prohibition is specified by the CPU
Address conversion means that outputs an access prohibition signal when
Based on the physical address output from the address conversion means.
The data transferred from the DMA transfer means
Write on the memory, and from the above address conversion means
When the access prohibition signal is output, the above DMA transfer
Write the data transferred from the means to the memory
Writing control means for prohibiting writing .
Data processing device.