JP3095348B2 - Discrete cosine transform and inverse discrete cosine transform device in data compression / decompression device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs high-speed discrete cosine transform and inverse discrete cosine transform in a data compression / decompression device.
It relates USo location, in particular, to an improved technique using a two-dimensional rotation operation.

[0002]

2. Description of the Related Art In recent years, computers such as WS and PC, and semiconductor devices such as VLSI have been increased in speed and cost, and J.
With the standardization of digital image compression / expansion processing such as PEG, H261, and MPEG, digital compression / expansion processing of image data has become familiar. as a result,
The demand for digital image compression / expansion processing has increased, and image compression / expansion processing technology that achieves a higher compression ratio and higher quality has been required.

[0003] Recently standardized JPEG, H261, M
In image compression / expansion processing such as PEG, Discrete Cosine Transform
m, hereinafter also referred to as “DCT”. ), The resulting DCT coefficients are linearly quantized, and image compression is performed by further performing variable-length coding, and the image is further decompressed by performing the reverse process. .

[0004] Here, DCT is one of orthogonal transforms.
The output DCT coefficient corresponds to a spatial frequency component included in the original image data. Equation 7 is a transform equation representing a one-dimensional N-order DCT, that is, a DCT for N pieces of input data f [x] (0 ≦ x ≦ N−1).

[0005]

(Equation 7) Here, K is a constant, and C [u] (0 ≦ u ≦ N−1) satisfies Expression 8.

[0006]

(Equation 8) In image processing in which compression and decompression are performed by such a DCT coding method, speeding up of DCT and inverse DCT is one of the very important points in realizing a high compression rate and high quality of an image. Various studies have been made on the speeding up of the DCT operation, but one of the factors hindering the speeding up is as follows.
One is that there are many multiplications (for example, W. Che
n et al., '' A FastComputational Algorithm for the Discr
ete Cosine Transform, '' IEEE Trans.Commun., COM-2
5, pp. 1004-1009, 1977.).

However, it has been shown that all or many of the multiplications required in the DCT operation can be expressed using a two-dimensional rotation operation as shown in Equation 1 (for example, A Ligtenberg et al.,
'' A single chip solution for an 8 by 8 twodimensi
onal DCT, '' IEEE Intl.Symp.on Circuits and Syste
ms, ISCAS-87, pp. 1128-1131, 1987., C. Loeffler et al.,
'' Algorithm-architecture mapping for custom DSP ch
ips, '' IEEE Intl.Symp.on Circuits and Systems, I
SCAS-88, pp.1953-1956, 1988.).

Specifically, for example, in equation 7, K = √
If N = 8, a calculation flow graph shown in FIG. 6A can be obtained (for example, KR Rao et al.,
"Image coding technology-DCT and its international standard-", Ohmsha, pages 403-426). From this figure, one dimension 8
It can be seen that many of the multiplications required in the next DCT have been replaced by two-dimensional rotation operations on three different angles (-π / 16, -2π / 16, -5π / 16). FIG. 6B is a table for explaining the meaning of the symbols used in FIG. 6A.

From the above, it can be seen that the DCT operation can be performed at a high speed by increasing the speed of the two-dimensional rotation operation represented by Expression 1. Therefore, techniques for speeding up the two-dimensional rotation operation have been conventionally proposed. The two typical techniques are as follows. (1) The first conventional method is a method of performing a two-dimensional rotation operation of Expression 9 obtained by transforming the two-dimensional rotation operation of Expression 1 instead of performing the two-dimensional rotation operation of Expression 1.

[0010]

(Equation 9) This means that, in the two-dimensional rotation operation shown in Equation 1, four multiplications are required for one two-dimensional rotation operation, but according to the two-dimensional rotation operation shown in Equation 9, three multiplications are performed. It is focused on that it suffices. In fact, it has been reported that this technique can be realized by 11 multiplications, whereas the conventional scheme requires 16 multiplications to realize one-dimensional DCT (Loeffler et al., '' Practical fast
1-D DCT algorithms with 11multiplications, '' IEEE
Intl. Conf. On Acoust., Speech, and Signal Proces
s., ICASSP-89, pp.988-991, 1989.).

According to this method, for example, JPEG, H2
61, 8 required for image compression / decompression such as MPEG
Conventional 25-dimensional DCT of 2D 8th order of × 8 pixel data
The required multiplication of six times is reduced to 176 times. (2) The second conventional method uses CORDIC (COordinate R).
This method uses an algorithm called “otation digital computer” (for example, JE Volder, '' TheCORDIC
trigonometric computing technique, '' IRETrans.El
ectron.Comput., EC-8, pp.330-334, 1959., JS Wa
lther, '' A unifiedalgorithm for elementary functio
n, '' AFIPS Conf., 38, pp.379-385, 1971.).

In this method, equations ( 10), ( 11) and ( 12)
Are repeatedly executed while δ [i] is determined so that z [i] shown in Expression 12 converges to 0.

[0013]

(Equation 10)

[0014]

[Equation 11]

[0015]

(Equation 12) Here, i is an integer, δ [i] = ± 1, x [0], y [0] and z [0] satisfy Expression 13, and θ [i] satisfy Expression 14.

[0016]

(Equation 13)

[0017]

[Equation 14] Then, (x [n], obtained by Expression 10 and Expression 11,
y [n]) multiplied by the correction value C [n] shown in Equation 15 is
It converges on the theoretical value (x ', y') to be obtained.

[0018]

(Equation 15) That is, Equation 16 holds for a large n.

[0019]

(Equation 16) This technique breaks down any angle (θ) to be rotated into a sum or difference of predetermined discrete angles associated with powers of two (eg, θ = θ1−θ2 + θ3,. The dimensional rotation operation is replaced with the repetition of a simple binary operation (digit shift and addition / subtraction).

FIG. 7 is a block diagram showing a configuration in a case where the two-dimensional rotation operation by the CORDIC technique is realized by hardware. This conventional device is roughly divided into a discrete angle rotation calculation unit 710 and a control unit 720, and operates in synchronization with a clock (not shown). That is, the selectors 711 and 712 output the input data x [0] and y [0] in the first clock, and adder / subtractor 71 from the next clock.
7 and 718 to the next registers 713 and 712
Send to

Two sets of data sent directly from the registers 713 and 714 and via the shifters 715 and 716 are calculated by adders / subtracters 717 and 718, respectively. The adder / subtractor 717 corresponds to the operation of Expression 10, and the adder / subtractor 718
Corresponds to the operation of Expression 11. The control unit 720 includes an LUT
(Lookup table) 721, a Z calculation unit 722, and a determination unit 723, and the LUT 721 is a ROM that stores many angles θ [i] that satisfy Expression 14 in advance.
The calculation unit is an arithmetic unit that calculates z [i] in Expression 12, and the determination unit 723 is a comparator that determines whether δ [i] in Expression 12 should be 1 or −1.

The arithmetic function (addition or subtraction) of the adders / subtracters 717 and 718 is dynamically determined for each clock according to an instruction from the control unit. Thus, for each clock, Equation 10, so that the operation of Equation 11 and Equation 12 is executed once. It has been clarified in the CORDIC method that appropriate arithmetic accuracy is ensured by making the number of repetitions of the arithmetic equal to the word length of the input data (for example, GL Haviland et al., “A CORDICArithme
tic Processor Chip, '' IEEE Trans. Comput., C-29, p
p.68-78, 1980.). For example, when performing a 2-dimensional rotation operation on the input data with the operation word length of 16 bits, Equation 10, Equation 11 and Equation 12 may be repeated each 16 times.

Table 1 below shows that the 16-bit fixed-point input data (x, y) = (50, 50) is
A calculation process when a two-dimensional rotation calculation is performed with θ = −π / 16 using the technique will be described.

[0024]

[Table 1] Note that the numerical values shown in Table 1 represent 16-bit data as fixed-point data in which the position of the decimal point is the eighth bit from the lower order. As can be seen from this table, the constant (x [16], y [16]) shown at the bottom is a constant C [16] (= 0.6
072529 ...) (58.787303, 39.286418) is well in agreement with the theoretical value to be obtained (58.793780, 39.284748).

[0025]

However, DCT using the two-dimensional rotation operation and the inverse D
Although the CT has reduced the number of calculations by a certain amount, it has a problem that it cannot be said to be a sufficiently high-speed technique for compressing and expanding real-time large-volume image data in real time. Further, when these operations are realized by hardware, there is a problem that a circuit becomes large-scale.

That is, in the first conventional method, the four multiplications required in the two-dimensional rotation operation are merely reduced to three multiplications, and a complicated operation called multiplication is still required. Therefore, the time saved by this method is not enough. On the other hand, in the second conventional method,
Shifts and additions / subtractions must be performed a number of times equal to the word length of the input data to ensure the operation accuracy. If the word length of the data to be handled is long, a very large number of shifts / additions / subtractions are required. Therefore, the time required for one two-dimensional rotation calculation becomes long.

As shown in FIG. 7, when the second conventional method is implemented by hardware, a look-up table, a comparator, and the like are required. Many gates are spent and DC
It becomes difficult to make T an LSI. Furthermore, in image compression / expansion, two-dimensional image data is divided into 8 × 8 pixel blocks, and DCT / inverse DCT is sequentially repeated for each block. However, such a hardware configuration handles 16-bit data. For example, a two-dimensional rotation operation on one set of input data is completed by 16 clocks. For example, when repeating a two-dimensional rotation operation on 48 sets of input data, a long time of 768 clocks is required. .

On the other hand, that the second in case of realizing a conventional technique in software, for determining the calculation result of Equation 12 is not from the output type of the operation of formula 10 and formula 11 (addition or subtraction) That is, since the condition judgment is required for each operation, the function of the pipeline of the CPU or the like executing this software cannot be fully utilized. As a result, there is a problem that speeding up is hindered.

Accordingly, the present invention has been made in view of such a problem, and the multiplication required in the conventional two-dimensional rotation operation is performed only by shift and addition / subtraction, and the CORDI
To provide a C technique fast discrete cosine transform and inverse discrete cosine varying retrofit location capable of performing two-dimensional rotation operation with a small number of shift and subtraction than the number of calculations required in the first object .

Further, a second object of the present invention is to provide a conventional CO 2
Look-up tables, comparators, and the like required when implementing the RDIC method with hardware are not required.
That is, an object of the present invention is to provide a discrete cosine transform and inverse discrete cosine transform device which can be constituted by a small-scale circuit. Also,
A third object of the present invention is to provide a method for repeating a constant-angle two-dimensional rotation operation on continuous input data, in which the number of clocks required for the two-dimensional rotation operation on one set of input data is determined by the CORDIC method. An object of the present invention is to provide a high-speed discrete cosine transform and inverse discrete cosine transform device which requires less than the case.

[0031]

SUMMARY OF THE INVENTION In order to solve this problem, the present invention is a method for performing DCT / inverse DCT using a two-dimensional rotation operation at a predetermined angle (θ). A step of calculating target input data (x [0], y [0]); and, for the input data (x [0], y [0]), δ [i], p A step of executing a rotation operation at a discrete angle represented by Expression 5 expressed by using [i] and q [i] n times, and output data (x [n], y finally obtained by the step) [n]) performing the correction.

According to this method, instead of an arbitrary angle,
Since the minimum steps required to execute the rotation operation at a predetermined angle are obtained in advance based on Equations ( 2) to ( 4), and since these steps are constituted only by shift and addition / subtraction, the related art The number of multiplications required by the technique is reduced and the number of processing steps required is also reduced. Further, by adopting a pipeline configuration in which the two-dimensional rotation operation according to this method sequentially performs the rotation operation at discrete angles, the conventional COR can be used.
A look-up table, a comparator, and the like required by the DIC method become unnecessary, and a high-speed and compact DCT / inverse DCT device with a small circuit scale is realized.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION In the case of a one-dimensional N-order DCT device, its configuration (processing step) is performed in the following order.
Should be determined. (1) According to the above-mentioned theory of Loeffler et al.
Specify the type (angle) of the two-dimensional rotation calculation required for CT,
Further, a configuration for realizing each specified operation is determined in the following order. (2) in each specific angular equation 2, of n satisfying Equations 3 and 4 [delta] ([delta] [0] from δ [n-1]), p from p (p [0] [n-
1]) and q (q [0] to q [n-1]) are determined.

[0034] In this determination, [delta] [i] at a value of less than n, p [i] and q [i] is Formula 2, Formula 3, to satisfy equation 4, also, p [i + 1] - p [i] ≠ 1, q [i + 1] −q [i]
It is preferable to satisfy # 1. (3) Based on the determined n, δ [i], p [i], and q [i], determine the configuration of the pipeline that repeats the operation of Expression 5.

That is, the pipeline is composed of n stages for executing the operation of Expression 5 corresponding to each of i = 1 to n-1. Since each stage executes the operation of Equation 5 once, two registers for storing x [i] and y [i] and two adders or subtractors determined by the value of δ [i] It can be composed of vessels. 2 by p [i] and q [i]
The exponentiation operation (shift down) may be realized by devising a wiring between the register and the adder or the subtractor (connecting by shifting the corresponding digit).

The DCT device having the configuration determined as described above can perform high-speed D.sub.D processing on N input pixel data.
Perform CT.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a DCT device according to the present invention will be described in detail with reference to the drawings. (First Embodiment) The first embodiment is a DCT that performs one-dimensional 8th-order DCT at high speed.
It concerns the device. (Overall Configuration and Function) FIG. 1 is a block diagram showing the configuration of the present apparatus.

This apparatus comprises a preprocessing unit 101, three rotation calculation units 102 to 104, and six correction units 105 to 110.
Consists of f [0] to f [7] are input pixel data to the apparatus,
F [0] to F [7] indicate DCT coefficients which are outputs of the present apparatus.
FIG. 2 is a calculation flow graph showing the operation performed by the present apparatus, and corresponds to the calculation flow graph shown in FIG. 6 in the conventional method.

The pre-processing unit 101 comprises an adder, a subtractor, a selector, a register and the like, and performs the addition / subtraction 201 shown in FIG. The content of the operation in the preprocessing unit 101 is as follows:
As can be seen from FIGS. 7 and 2, this is the same as the case of the conventional method. Specifically, the DCT coefficient is calculated from eight pieces of input pixel data f [0] to f [7] by a simple operation such as addition and subtraction. F [0]
And F [4], and input data to each of the rotation calculation units 102 to 104.

The first rotation calculator 102 and the second rotation calculator 1
03 and the third rotation operation unit 104 are respectively -2π /
The two-dimensional rotation operation is performed at fixed angles of 16, −π / 16, and −5π / 16, and R ′ (−−) shown in FIG.
2π / 16), R ′ (− π / 16), R ′ (− 5π / 1
6). Note that these three types of rotation calculation units 10
Detailed configurations and operations of 2 to 104 will be described later.

Each of the six correction units 105 to 110 is composed of a multiplier or the like, and each of the six correction units 105 to 110 shown in FIG.
Perform 0. As can be seen from FIGS. 7 and 2, the contents of the calculations performed by these six types of correction units 105 to 110 are different from the conventional method only in the multiplier. Note that k shown in FIG.
2, k1 and k5 are all constants and have the following values. k2 = 0.892658, k1 = 0.968133, k5 = 0.684574 The significance of these will be described later. (Structure and Operation of Rotation Calculation Unit) The detailed configuration and operation of the rotation calculation units 102 to 104 of the present apparatus configured as described above, which are significantly different from those of the apparatus according to the related art, will be described. . Since each of the rotation calculation units 102 to 104 is configured by the same type of circuit, the second rotation calculation unit 1 is used here.
03, that is, a calculation unit that performs a rotation calculation at an angle of -π / 16 at a high speed will be described.

FIG. 3 is a circuit diagram showing the configuration of the second rotation calculation unit 103. The second rotation operation unit 103 is roughly divided into five stages of discrete angle rotation operation units 340 to 344 and an output buffer 345, and the result of the upper stage discrete angle rotation operation unit is propagated to the next stage by a clock (not shown). It has a pipeline configuration.

The discrete angle rotation operation section of each stage includes two 16
Bit registers REGx [i], REGy [i] and adder AD
Dx [i] (or ADDy [i]) and a subtractor SUBy [i] (or SUBx [i]), and the output buffer 345 has two 16-bit registers REGx [5] and REGy [5]. Consists of The wiring in the figure is basically 16 buses, and the corresponding digits are connected. When a numerical value is shown beside the wiring, the wiring is indicated by the sign of the numerical value. In the corresponding direction, the connection is shifted by the digit of the numerical value.
For example, “−2” is written beside the wiring connecting the register REGx [0] and the subtractor SUBy [0].
This means that the output data of the register REGx [0] is connected to be shifted down by 2 bits and input to the subtractor SUBy [0].

Next, a description will be given of how the second rotation calculation unit 103 configured as described above performs a two-dimensional rotation calculation of an angle of -π / 16 while ensuring 16-bit calculation accuracy. First, two input data x [0], y output from the pre-processing unit 101 by the first clock.
[0] is stored in the registers REGx [0] and REGy [0].

Next, the following operation is performed in the adder ADDx [0] and the subtractor SUBy [0] by the second clock, and the result is stored in the registers REGx [1] and REGy [1].
Is stored in REGx [1] = REGx [0] + 2-2−REGy [0] REGy [1] = REGy [0] −2−REGx [0] Similarly, the subtractor SUBx is generated by the third clock.
The following operation is performed in [1] and the adder ADDy [1], and the result is stored in the registers REGx [2] and REGy [2].

REGx [2] = REGx [1] -2-4 · REGy
[1] REGy [2] = REGy [1] + 2−4 · REGx [1] Hereinafter, similarly, when the sixth clock has elapsed, the final result R of the second rotation operation unit 103 is obtained.
EGx [5] and REGy [5] are the registers REGx [5] and REGy
Stored in [5].

Tables 2 and 3 below show the input data (x
Registers REGx [0] to REGx [5] and REGy when (50, 50) is given as [0], y [0])
Value stored in [0] to REGx [5] (in hexadecimal notation)
Shows the change for each clock.

[0048]

[Table 2]

[0049]

[Table 3] Note that "-" in the table indicates that values for other input data different from the input data (50, 50) are held. Further, the real number display column in Table 2 shows a value (in decimal notation) that represents the 16-bit data displayed in the left column as 16-bit fixed-point data with the decimal point position being the eighth bit from the lower order. I have.

The results (REGx [5], REGy [5]) finally obtained in the second rotation calculation section 103 are sent to the third correction section 107 and the fourth correction section 108, respectively, and
-Although multiplied by k1, the value obtained by multiplying (REGx [5], REGy [5]) by k1 is a value approximating the theoretical value (x ', y') to be obtained. A comparison between these values and the value C · (x [5], y [5]) according to the conventional CORDIC method is as follows.

(X ′, y ′) = (58.793780, 39.284748) k1 · (REGx [5], REGy [5]) = (58.791401, 39.288812) C (x [16], y [16]) = (58.787303) , 39.286418) As can be seen from this comparison, the data obtained by this apparatus is closer to the theoretical value than the data obtained by the CORDIC method. In other words, the present apparatus has executed a two-dimensional rotation operation with higher accuracy than the CORDIC method of performing the operation 16 times, although the apparatus has executed only the operation 5 times.

As is apparent from the configuration of the second rotation calculation unit 103, components corresponding to the LUT 721, the z calculation unit 722, and the determination unit 723 required by the CORDIC method shown in FIG. It has become. Further, in the above example, the two-dimensional rotation operation for one set of input data is completed by six clocks. However, in the case of an actual image compression / decompression process in which a large number of sets of input data are successively provided. The number of clocks required for the two-dimensional rotation operation of one set of input data approaches 1 due to the pipeline effect. In this regard, this is greatly different from a conventional device that always requires 16 clocks for the rotation operation of one set of input data.

As another method for realizing the CORDIC method by hardware, the control unit 72 shown in FIG.
It is also conceivable to adopt a configuration in which 0 is eliminated and the discrete angle rotation operation unit 710 is connected in series as a pipeline in 16 stages. However, even with such a configuration, in terms of the operation speed and the compactness of the circuit, a single shifter is not required, and a high-precision two-dimensional rotation operation can be performed using only a 5-stage addition / subtraction circuit. Needless to say, it is far from the execution unit 103 to be executed. (Theoretical Consideration) Next, the second rotation operation unit 103 of the DCT device according to the present invention
The process of determining the configuration of FIG. 3 as shown in FIG. 3 and the configuration of the other rotation calculation units 102 and 104 will be described.

[0054] First, "Formula 2, Formula 3, ([delta] from δ [0] [n-1 ]) of n defined to satisfy equation 4 δ, p (p [0 ]
To p [n-1]) and q (q [0] to q [n-1]),
(X [n], y obtained by repeating the operation of Equation 5 n times)
[n]) is the theoretical value (x ′, y ′) that should be originally obtained and Equation 17
(However, x [0] and y [0] are expressed by Expression 18)
Has the relationship shown in ) ".

[0055]

[Equation 17]

[0056]

(Equation 18) First, the subtraction value on the left side of Expression 2 is set to Δθ. That is,

[0057]

[Equation 19] Since Δθ ≒ 0, the theoretical value (x ′, y ′) can be expressed as follows.

[0058]

(Equation 20) Equation 20 can be transformed using Equation 1 to

[0059]

(Equation 21) Then, Equation 18, from Equation 19,

[0060]

(Equation 22) Decomposing into the product of n matrices,

[0061]

(Equation 23) From δ [i] = ± 1,

[0062]

(Equation 24) Equation 3, from the formula 4,

[0063]

(Equation 25) Organize k [i],

[0064]

(Equation 26) Equation 5, from Equation 6,

[0065]

[Equation 27] Therefore, it has been proved that Expression 17 holds. Next, a process for determining a specific circuit configuration of each of the rotation calculation units 102 to 104 will be described. Each rotation calculation unit 102-1
The discrete angle rotation calculation unit constituting each stage of No. 04 executes the calculation shown in Expression 5. Therefore, θ = −2π
Δ, all necessary δ (δ [0] to δ [n−1]) and p (p for three types of angles of −π / 16 and −5π / 16
By determining the values of [0] to p [n-1]) and q (q [0] to q [n-1]), the specific circuit configuration of each of the rotation calculation units 102 to 104 is univocal. Can be derived.

Hereinafter, the necessary n δ [i], p [i] and q
A process for specifically determining [i] will be described. (S
tep1) First, in order to secure at least calculation accuracy by the CORDIC method, the allowable error angle E is set to CORDI.
Absolute value of z [16] which is an allowable error angle in the C method (=
0.000005).

That is, E = 0.000005. (Step 2)
Next, let k [i] = cosθ [i]. By setting this way k [i], equation 3, since Equation 4 are each equation 28 is simplified to Equation 29, it is possible to clarify the comparison with CORDIC technique.

[0068]

[Equation 28]

[0069]

(Equation 29) From Expression 29, q [i] = 0 for all i. (Step 3) Subsequently, δ [0] and θ [0] that minimize Δθ [0] (= | θ−δ [0] · θ [0] |) are determined.

Considering δ [i] = ± 1 and the condition of Expression 28, for example, in the case of the second rotation operation unit 103 (θ = −π /
16), θ [0] = tan-12−2 and δ [0] = − 1
Thus, it can be derived that Δθ [0] can be minimized. As described above, regarding the second rotation operation unit 103, p
[0] (= -2), q [0] (= 0) and δ [0] (= -1) were determined. (Step 4) Similarly, δ [1] and θ [1] that minimize Δθ [1] (= | θ−δ [0] · θ [0] −δ [1] · θ [1] |) To determine.

In the case of the second rotation calculation unit 103, θ
By setting [1] = tan-12-4 and δ [0] = 1, Δθ
It can be derived that [1] can be minimized. Therefore, p [1]
(= -4), q [1] (= 0) and δ [1] (= 1) were determined. (Step 5) As described above, i = 0, 1, 2,.
.. P [i], q [i], and δ [i] are sequentially determined. In the case of the second rotation operation unit 103, when i = 4, Δθ [i] is obtained for the first time. <E 2, and the determination process ends.

The values of δ [i], p [i], etc. determined in this way are shown in Tables 4, 5 and 6 below.

[0073]

[Table 4]

[0074]

[Table 5]

[0075]

[Table 6] Table 4 shows the first rotation calculator 102 (θ = −2π / 16), Table 5 shows the second rotation calculator 103 (θ = −π / 16), and Table 6 shows the third rotation calculator 102 (θ = −5π). / 16). In these tables, k [i] and the value of k defined by Equation 6 are also shown.

From the above description, it has been clarified that the second rotation operation section 103 has the circuit configuration shown in FIG.
Further, according to the configuration of the second rotation operation unit 103 shown in FIG. 3 and the values of δ [i] and p [i] shown in Tables 4 to 6, (q
[i] is all zero. ), The circuit configurations of the first rotation operation unit 102 and the third rotation operation unit 104 can be easily analogized. That is, the first rotation calculation unit 102 and the second rotation calculation unit 10
3 has a five-stage pipeline configuration, and the third rotation operation unit 104 has a six-stage pipeline configuration.

As described above, the six correction units 10
5 to 110 are values according to the conventional method shown in FIG.
Correction is performed using a value obtained by multiplying 2) by constants k2, k1, and k5. This is because the theoretical value (x ′, y ′) to be obtained is a value obtained by multiplying the data (x [n], y [n]) output from each rotation operation unit by the correction value k, as can be seen from Expression 17. This is because (approximate). The specific values of k2, k1, and k5 are
These are the values described at the end of the column of k shown in Tables 4, 5, and 6, respectively, and are unambiguous when n, δ [i], p [i], q [i] are determined. It is a value that is determined. Second Embodiment A second embodiment relates to a DCT apparatus that performs DCT on input data of two-dimensional octal, that is, 8 × 8 pixels at high speed. (Overall Configuration and Function) FIG. 4 is a calculation flow graph showing the overall configuration of the present apparatus. "1-DDCT" in the figure further becomes a calculation flow graph shown in FIG. The calculation flow graph of FIG.
This is equivalent to the calculation flow graph of FIG. 2 in the first embodiment except for the correction (multiplying by √2 · k) at the last stage.

In FIG. 4, f [0] [0] to f [7] [7] are 64
The pieces of input pixel data F [0] [0] to F [7] [7] indicate DCT coefficients obtained by the present apparatus. Further, k00 to k77 are constants and satisfy Expression 30.

[0079]

[Equation 30] Although the configuration block diagram (FIG. 1) is shown in the first embodiment, the configuration block diagram is omitted in this embodiment. This is because the correspondence between each constituent block and the calculation flow graph is the same as that of the first embodiment, so that the configuration of the present apparatus can be easily derived from the calculation flow graphs of FIGS.

That is, the configuration of the portion corresponding to FIG. 5 (hereinafter referred to as “1-DDCT module”) in the present apparatus is different from the configuration shown in FIG.
Equivalent to zero. Further, as is apparent from FIG. 4, the entirety of the present apparatus is composed of eight 1-Ds arranged in the left column in the figure.
The DCT module includes a DCT module (hereinafter, referred to as a “front section”), eight 1-DDCT modules (hereinafter, referred to as a “post section”) arranged in the right column in the figure, and 64 correction sections. You.

With the present device configured as described above,
The grounds for implementing the DCT of dimension eight are as follows. In general, a two-dimensional N-order DCT is shown in Equation 31.

[0082]

(Equation 31) Then, the two-dimensional N-dimensional DCT shown on the right side of Equation 31
Is decomposed into a plurality of one-dimensional N-order DCTs. That is, 2
The N-dimensional DCT is a former stage that performs one-dimensional N-dimensional DCT on each of N sets of input data obtained by dividing N × N pieces of input data into N pieces, and further sets the output data thereof constant. Each of the N sets of output data divided into N pieces under the relationship is decomposed into a post-stage section that performs one-dimensional N-order DCT.

Since this apparatus performs two-dimensional, eighth-order DCT, by setting K = √2 and N = 8, FIG.
And the calculation flow graph of FIG. 5 is derived. Therefore,
It can be seen that a two-dimensional eighth-order DCT is realized by the configuration shown in these calculation flow graphs. Next, the significance of the 64 correction units of the present apparatus will be described.

As can be seen from the calculation flow graphs of FIG. 4 and FIG. 5, this apparatus is basically different from the apparatus of the first embodiment in that
Equivalent to six. However, in this device,
As described above, each 1-DDCT module differs from the device of the first embodiment in that it does not have a correction unit inside. This is originally required in the 1-DDCT module belonging to the preceding stage by using the property F [s · u] = s · F [u] derived from the one-dimensional N-order DCT equation of Equation 7. The correction is performed twice by combining the correction (for example, multiplying by √2 · ki) and the correction originally required by the 1-DDCT module belonging to the subsequent stage (for example, by multiplying by √2 · kj). Is corrected once (for example, multiplying by 2 · ki · kj).

Therefore, in the present apparatus, the 1-D
For the DCT output data, 64 correction units
By multiplying by the correction value shown in Expression 30, a two-dimensional eighth-order DCT coefficient can be obtained with a small number of processing steps.
The detailed operation of each 1-DDCT module is as follows.
Since it is the same as the case of the first embodiment, the description is omitted. (Comparison with Conventional Method) Next, the types and the number of operations required for the two-dimensional eighth-order DCT will be described by comparing the case of the present apparatus with the case of the conventional method.

First, for comparison with the first conventional method,
The number of times of multiplication executed in the present apparatus when input data of one block composed of 8 × 8 pixels is given. In this apparatus, two "1/1 /" shown in FIG.
{2} requires two multiplications per 1-DDCT module, and the device has 16 1-DCTs.
Since the DCT module and the 64 correction units are used, a total of 96 multiplications (= 2 × 16 + 64) are performed.

As described above, the number of multiplications is further reduced as compared with the first conventional method in which 256 multiplications are reduced to 176 times. In addition, MPE
In the standard such as G, the value of the constant K in Equation 31 is different from that of the present embodiment (K = √2), but k00 to k in the present embodiment.
This can be handled by scaling the value of 77 in advance, and this does not change the number of necessary multiplications.

In an image compression apparatus or the like, DCT
Each DCT coefficient output from the device is divided by a corresponding predetermined step size for a subsequent linear quantization process. Accordingly, 64 of the present DCT apparatus is used.
By combining the processing by the correction units and the division by the linear quantization, the number of times of multiplication in the entire image compression apparatus can be reduced.

Next, CORDIC, which is a second conventional method, is used.
Three types of angles (-2π / 16, -π / 16, -5π / 16) with a data word length of 16 bits for comparison with the method
The type and the number of calculations required to perform the rotation calculation are calculated. The processing common to the conventional method and the present apparatus, that is, the processing of multiplying the correction value (C or k) is not included in the comparison.

In the apparatus according to the CORDIC method shown in FIG. 7, two shifts and three additions / subtractions (x [i], y [i], z [i]) are performed for one calculation of the discrete rotation angle. And one condition determination is required, so that the calculation of the 48 discrete rotation angles requires a total of 96 shifts, 144 additions / subtractions, and 48 condition determinations. On the other hand, in the present apparatus, the rotation calculation of -2π / 16 is added and subtracted ten times,
Since the rotation operation of / 16 requires 10 additions and subtractions, and the rotation of -5π / 16 requires 12 additions and subtractions, only 32 additions and subtractions are required. Moreover, in this device, CO
Controls required by the RDIC method, ie, LUT, z
The calculation unit and the determination unit become unnecessary.

As described above, according to the present apparatus, the types and the number of operations required by the conventional method are remarkably reduced, and the circuit configuration becomes compact. It is considered that such an effect is based essentially on the fact that the present apparatus is configured by a process or a circuit that performs a rotation operation at a predetermined angle instead of an arbitrary angle. As described above, the DCT device according to the present invention has been described based on the embodiments, but it is needless to say that the present invention is not limited to these embodiments. (1) In the first and second embodiments, the present invention is realized by a logic circuit (hardware), but may be realized by a program (software) executed under a general-purpose CPU. It goes without saying that even with the software method, the same effect as that obtained by the hardware, that is, the effect of shortening the processing steps can be obtained. (2) In the first and second embodiments, the apparatus that performs DCT has been described. However, the same applies to an apparatus that performs inverse DCT. For example, the two-dimensional inverse DCT is
Generally, it is expressed by the equation 32, but the two-dimensional inverse DCT is also 2
This is because, similarly to the dimensional DCT, it is also expressed as a calculation flow graph using a two-dimensional rotation operation.

[0092]

(Equation 32) (3) The DCT devices of the first and second embodiments use an eighth-order DCT.
Although T is performed, the present invention is not limited to this order. That is, if the order N is determined in advance, the necessary rotation angle θ can be determined from the order N.
This is because the circuit configuration of the rotation calculation unit R ′ (θ) that performs the rotation calculation of the angle θ is uniquely determined. (4) DCT apparatus according to the first and second embodiments have been subjected to DCT defined by the respective formulas 7 and Formula 31, as long as it is expressed using a two-dimensional rotation operations, other definitions May be used. (5) In the first embodiment, when determining n, δ [i], p [i], and q [i], k [i] = cosθ [i], and Δθ for each i
The determination of δ [i] and p [i] that minimizes [i] was repeated, but is not limited to such a method.
For example, it is conceivable that k [i] = sin θ [i].

Where p [i + 1] -p [i] ≠ 1 and q [i + 1] -q
It is preferable to determine p [i] and q [i] that satisfy [i] ≠ 1. For smaller n, Formula 2, Formula 3, n satisfying Equation 4, [delta] [i], in order to determine the p [i] and q [i]. (6) Although the DCT apparatuses according to the first and second embodiments are directed to image data, the present invention is not limited to this, and may be, for example, audio data.

[0094]

As is apparent from the above description, the discrete cosine transform and the inverse discrete cosine transform device according to the present invention provide a DCT.
/ Inverse DCT is performed using a two-dimensional rotation operation at a predetermined angle (θ), and the two-dimensional rotation operation is decomposed into a minimum necessary number of rotation operations at a predetermined discrete angle. Each rotation operation is represented by multiplication by a power of 2 and addition / subtraction.

As a result, many multiplications required in the conventional method are replaced with simple repetition of logical operations (shift and addition / subtraction), and the number of operations is smaller than the number of operations required in the conventional CORDIC method. more 2-dimensional rotation operation high operation precision is performed, high-speed discrete cosine transform and inverse discrete cosine varying retrofit location is achieved.

Further, according to the discrete cosine transform and the inverse discrete cosine transform method according to the present invention, the two-dimensional rotation operation can be decomposed into a rotation operation at a predetermined discrete angle under clear guidelines. This makes it possible to easily determine the type and number of optimal logical operations required for the two-dimensional rotation operation.

Further, according to the discrete cosine transform and inverse discrete cosine transform device according to the present invention, the two-dimensional rotation operation is constituted by a pipeline for sequentially performing a rotation operation at a simple discrete angle. This eliminates the need for a look-up table, a comparator, and the like, which are required by the conventional CORDIC method, and allows a two-dimensional rotation operation unit to be constructed with a small circuit scale, thereby realizing a high-speed and compact DCT / inverse DCT device. Is done.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a DCT device according to a first embodiment of the present invention.

FIG. 2 is a calculation flow graph showing the content of a one-dimensional eighth-order DCT operation performed by the apparatus.

FIG. 3 is a circuit diagram showing a detailed configuration of a second rotation calculation unit 103 of the device.

FIG. 4 illustrates a second example of the operation performed by the DCT apparatus according to the second embodiment of the present invention.
9 is a calculation flow graph showing the contents of DCT operation of dimension 8;

FIG. 5 shows “1-D D” in the calculation flow graph of FIG.
41 is a calculation flow graph showing the details of CT "in detail.

FIG. 6 is a calculation flow graph showing the contents of a one-dimensional eighth-order DCT calculation in the related art.

FIG. 7 is a block diagram showing a configuration in a case where a two-dimensional rotation operation by a conventional CORDIC method is realized by hardware.

[Explanation of symbols]

 101 Pre-processing unit 102-104 Rotation calculation unit 105-110 Correction unit 340-344 Discrete angle rotation calculation unit 345 Output buffer 300-305, 310-315 Register 320, 322, 324, 331, 333 Adders 321 and 323, 330, 332, 334 Subtractor

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/14 H03M 7/30 H04N 1/41 H04N 7/30 JICST file (JOIS)

Claims (4)

(57) [Claims] 1. A discrete cosine transform in a data compression device.
An apparatus for performing a two-dimensional rotation operation at a predetermined angle (θ) represented by Equation 1, wherein input data (x [0]) to be subjected to the two-dimensional rotation operation is obtained from the data to be converted. , y [0]) and input data calculation circuit for calculating an input data calculated by the input data calculation circuit (x [0], with respect to y [0]), based on said predetermined angle (theta) previously obtained equation 2, of n satisfying the formula 3 and formula 4 δ (δ [0] from δ [n-1]), p (p [0] p [n-1] from) and q (q [0] to q [n-1]), a discrete angle rotation operation circuit that executes a rotation operation at a discrete angle shown in Expression 5 n times from i = 0 to i = n−1, The output data is calculated by calculating the product of the output data (x [n], y [n]) finally obtained by the discrete angle rotation operation circuit and a constant including a predetermined coefficient (k) shown in Expression 6. Correction And a correction circuit that performs the following. (Equation 1) Here, (x, y) is the data before rotation, and (x ', y') is the theoretical value after rotation. (Equation 2) (Equation 3) (Equation 4) Here, δ [i] = ± 1, p [i] and q [i] are integers, n is a positive integer, E is a predetermined tolerance angle, and k [i] is a real number. (Equation 5) (Equation 6) 2. The discrete angle rotation operation circuit is composed of n stages of rotation operation units (R (0) to R (n-1)) connected in series as a pipeline. R (i) is a register REGx [i] for storing the data x [i].
And a register REGy [i] for storing the data y [i].
And two two-input arithmetic units ALUx [i] and ALUy [i]. The register REGx [i] and the two-input arithmetic unit ALUx [i]
And ALUy [i] mean that the data x [i] output from the register REGx [i] is shifted by q [i] bits, input to one of the arithmetic units ALUx [i], and p [i]. ] And shifted so as to be input to one of the two-input arithmetic unit ALUy [i], the register REGy [i] and the two-input arithmetic unit ALUx.
[i] and ALUy [i] mean that the data y [i] output from the register REGy [i] is shifted by p [i] bits to the other one of the two-input arithmetic unit ALUx [i]. Input and shifted by q [i] bits, and the 2-input arithmetic unit ALUy
[i] is connected so as to be input to the other one of the two input arithmetic units ALUx [i] and ALUy [i] are δ [i]
The two-input arithmetic units ALUx [i] and ALUy [i] are based on the two-input arithmetic units ALUx [i] and ALUy [i] except when they belong to the last-stage rotation arithmetic unit R (n-1). hand,
The results of these calculations are respectively converted to the next-stage rotation operator R (i + 1)
Register REGx [i + 1] and REGy [i + 1] DCT device according to claim 1, characterized in that the output. 3. An apparatus for performing an inverse discrete cosine transformation in a data decompression apparatus by using a two-dimensional rotation operation of a predetermined angle (θ) shown in equation 1, wherein the two-dimensional rotation is performed based on data to be transformed. input data to be subjected to the rotation operation (x [0], y [ 0]) and input data calculation circuit for calculating an input data calculated by the input data calculation circuit (x [0], y [ 0] relative), said predetermined angle (theta formula 2 obtained in advance based on), [delta] from the n satisfying equation 3 and equation 4 δ (δ [0] [ n-1]), p (p [ 0] to p [n-1]) and q (q [0] to q [n-1]) are used to perform the rotation operation at the discrete angle shown in Expression 5 from i = 0 to i = n− a discrete angular rotation calculation circuit for performing n times until 1, wherein the discrete angular rotation calculating circuit by finally obtained output data (x [n], y [ n]) and a predetermined coefficient shown in equation 6 (k ) An inverse discrete cosine transform device, comprising: a correction circuit that corrects output data by calculating a product of the output data and a constant. Wherein said discrete angular rotation calculation circuit is configured rotation calculator of n stages connected in series as a pipeline (from R (0) R (n- 1)) from the rotation calculator for each stage R (i) is a register REGx [i] for storing the data x [i].
And a register REGy [i] for storing the data y [i].
And two two-input arithmetic units ALUx [i] and ALUy [i]. The register REGx [i] and the two-input arithmetic unit ALUx [i]
And ALUy [i] mean that the data x [i] output from the register REGx [i] is shifted by q [i] bits, input to one of the arithmetic units ALUx [i], and p [i]. ] And shifted so as to be input to one of the two-input arithmetic unit ALUy [i], the register REGy [i] and the two-input arithmetic unit ALUx.
[i] and ALUy [i] mean that the data y [i] output from the register REGy [i] is shifted by p [i] bits and sent to the other of the two-input arithmetic unit ALUx [i]. Input and shifted by q [i] bits, and the 2-input arithmetic unit ALUy
[i] is connected so as to be input to the other one of the two input arithmetic units ALUx [i] and ALUy [i] are δ [i]
And the two-input arithmetic units ALUx [i] and ALUy [i] are the same except that they belong to the last-stage rotation arithmetic unit R (n-1). hand,
The results of these calculations are respectively converted to the next-stage rotation operator R (i + 1)
4. The inverse discrete cosine transform device according to claim 3, wherein the signals are output to registers REGx [i + 1] and REGy [i + 1].