JP3095102B2 - Inrush current prevention circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inrush current prevention circuit, and more particularly to protection of an inrush current limiting resistor generated when a DC power is supplied to a switching regulator such as a capacitor input, and interruption of input voltage and current. And an improved inrush current prevention circuit.

[0002]

2. Description of the Related Art Conventionally, an inrush current prevention circuit of this kind is provided with a switching regulator (hereinafter referred to as SR) by turning on a switch 2 from a primary power supply 1 as shown in a circuit body 103 of FIG.
3), power is supplied to SR3, an inrush current is generated because the input of SR3 is a capacitor (not shown) input.
A resistor 6 is connected to limit the rush current.
On the other hand, when the charging current to the capacitor, which is an inrush current, ends, the conduction circuit 104 operates to form a bypass circuit to avoid a voltage drop of the resistor 6. Here, the time constant of the operation of the conduction circuit 104 is determined by the capacitor (C) 7 and the resistor (R) 9, the potential of the resistor (R) 13 is raised, and the gate G 1 of the MOSFET 5 is controlled so that M
The source S and the drain D of the OSFET 5 are made conductive. The time sequence of this operation is shown in FIG.
This will be described with reference to (b) and (c). As shown in FIG. 5A, the switch 2 is turned on at the time t0, the charging completion time of the capacitor of the SR3 is set to t1a, the ON time of the MOSFET 5 is set to t2a, and the ON time of the SR3 is set to t3a. However, since the conduction circuit 104 actually has a secondary inrush current of C7 in particular, there is an uncertain element in the rise of conduction, and in the worst case, the secondary inrush current to C7 shifts after the rise time of SR3. There is. In this case, the operation of the bypass was delayed and the voltage drop of the resistor R6 was not avoided.

[0003]

In the conventional rush current prevention circuit described above, when the MOSFET is in the off state due to the delay of the rise voltage of the gate of the MOSFET 5,
The input current to the switching regulator flows through the inrush current limiting resistor (R6), and in the worst case, there is a drawback that it burns out.

[0004]

An inrush current prevention circuit according to the present invention comprises a resistor for limiting an inrush current from a DC power supply to a load such as a capacitor input, and an externally connected in series between the resistor and the DC power supply. A first MOS type field effect transistor having a gate for inputting a first control signal from the first MOS type field effect transistor , the resistor and the first MOS type field effect transistor connected in series .
A second MOS field-effect transistor having a gate connected in parallel with the transistor and receiving a second external control signal;
And Njisuta, and a bias circuit for supplying said first and second control signals, the said bias circuit outputs a ground potential which is the said first and second control signals a
And controlling the gate of the first MOS-type field effect transistor to be in a conductive state, passing the second control signal through a constant current element to set the gate of the second MOS-type field effect transistor by a predetermined delay from the first control signal. It is characterized in that it is controlled while maintaining the time to make it conductive.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIGS.
FIG. 3B is an explanatory diagram of the embodiment of FIG. 1, and FIGS. 3A and 3B are circuit diagrams of the bias circuit of FIG.

In the embodiment shown in FIG. 1, a current limiting circuit 101 composed of a resistor 6 and a MOSFET 4 connected in series provides a constant rush current to the switching regulator 3 when the primary power supply 1 is turned on, as described later. To a value. Next, in the conduction circuit 102 connected in parallel to the current limiting circuit 101, the MOSFET 5 becomes conductive when the voltage across C7 reaches the on-voltage Vth between the gate and source of the MOSFET 5A at time t. This time t is t =
(Vth / i) · C. C is the capacitor 7
Is the constant current of the constant current element 8.

This operation will be described with reference to the time sequence diagram of FIG. 2 and the circuit diagram of FIG. First, FIG.
5A is an explanatory diagram corresponding to FIG. 5A described above, and the time t described above is added. The qualitative principle of the present invention is that a bias circuit 1 is used instead of the conventional power-on switch 2.
2 to operate the MOSFET 4 of the current limiting circuit 101 first, and immediately operate the MOSFET 5A of the conduction circuit 102 after the time t1 when the inrush current to the SR 3 is completed to form a bypass circuit. That is, FIG.
As shown in (b), the voltage to SR3 gradually rises from the start time t0 of the inrush current, and operates so as to become the input voltage to SR3, that is, the steady operating voltage at the time t1 when the charging of the capacitor in SR3 is completed. . Next, the bias circuit 12 for controlling the above-described operation will be described with reference to FIG.
As shown in (a), when an ON signal is input to the base of Tr12A, a short-circuit occurs, the gate G1 of MOSFET 4 of the current control circuit 101 is immediately controlled, and the resistor R6
To charge C of SR3. Next, the conduction circuit 10
Since a divided voltage corresponding to R9 and the constant current of the constant current diode 8 is applied to the gate G1A of the second MOSFET 5 via the constant current diode 8, the discharge of C7 becomes faster than in the conventional example, and the time t substantially as described above. As a result, the MOSFET 5A becomes conductive.

FIG. 3B is another circuit example of the bias circuit 12, in which a power-on signal is applied to the base of the Tr 12A to short-circuit the Tr 12A and turn on the MOSFET 4 of the current limiting circuit 101. . The ON signal gives a delay time shorter than the time t by the delay circuit 13 to control the base of the Tr 12B to make the Tr 12B short. MOSFET 5A of the conduction circuit 102
Gate G1A is turned on by the delayed limited current and performs a bypass operation. Therefore, the time t described in FIG. 2A can be reliably set to the optimum value by adjusting the delay circuit 13. When there is no ON signal to the bias circuit 12, Tr12A in FIG. 3A and Tr12A and Tr12B in FIG. 3B are turned off, so that both the MOSFETs 4 and 5 are cut off and the switching regulator 3 is turned off. Current can be cut off.

[0009]

As described above, the present invention provides switching by providing a MOSFET connected in series to a resistor of an inrush current limiting circuit, a conduction circuit connected in parallel with the current limiting circuit, and a bias circuit. It is possible to prevent an inrush current during the operation of the regulator. Further, there is an effect that a switch circuit that cuts off the input voltage to the switching regulator by turning off the bias circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram of the embodiment of FIG.

FIG. 3A is a diagram of a bias circuit of the embodiment of FIG. 1 and FIG. 3B is a circuit diagram of another type.

FIG. 4 is a circuit diagram of a conventional inrush current prevention circuit.

FIG. 5 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Primary power supply 2 Switch 3 Switching regulator (SR) 4,5 MOSFET 6,9,10,11 Resistance 7 Capacitor 8 Constant current diode 12 Bias circuit 13 Delay circuit 101 Current limiting circuit 102 Conduction circuit

Claims (3)

(57) [Claims] A resistor for limiting an inrush current from a DC power supply to a load such as a capacitor input and a gate for inputting a first external control signal connected in series between the resistor and the DC power supply. First MOS-type field effect transistor having
Star and, connected in series the resistor and the first MOS type
The second externally connected parallel to the field effect transistor
MOS-type power supply having a gate for inputting a control signal of
And a bias circuit for supplying the first and second control signals. When the bias circuit outputs a ground potential as the first and second control signals, the first MOS type The gate of the field effect transistor is controlled to be in a conductive state, and the gate of the second MOS type field effect transistor is delayed by a predetermined delay from the first control signal by passing the second control signal through a constant current element. An inrush current prevention circuit characterized in that the current is maintained while being controlled to be in a conductive state. 2. The inrush current prevention according to claim 1, wherein said bias circuit includes a delay circuit for giving a predetermined delay time to said second control signal with respect to said first control signal. circuit. 3. The first and second of the bias circuit.
The first and, if the control signal outputs a release signal
2. The rush current prevention circuit according to claim 1, wherein the current of the second MOS type field effect transistor is cut off.