JP3093585B2 - Image processing method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing method and apparatus for performing predetermined processing on input image data and outputting the processed image data.

[0002]

2. Description of the Related Art A facsimile apparatus is generally well known as an image processing apparatus which performs some processing on input image data and outputs the processed image data.

A conventional facsimile apparatus will be described below with reference to FIG.

In FIG. 10, it is assumed that each is connected by a data bus. 1001 is a scanner,
The set original is read by a CCD or the like, and image raster data is output to a data bus in order from the top data of one line to the last data. An NCU 1002 interfaces with a telephone line. Reference numeral 1003 denotes a decoder that converts data encoded by the MH code or the like received via the NCU 1002 into image information, and outputs image raster data to the data bus in order from the first data to the last data of one line. Reference numeral 1004 denotes a memory which converts image raster data output from the scanner 1001 and the decoder 1003 from a lower address to an upper address,
Accumulate in order. 1005 is a memory;
6 detects that one line of image raster data has been stored in the memory 1004, the image raster data stored in the memory 1004 is transferred to the memory 1005, and from the lower address of the memory 1005 toward the upper address.
The image data is accumulated from the head data to the last data of one line of image raster data.

Reference numeral 1006 denotes a CPU, which controls each unit of the apparatus. Reference numeral 1007 denotes a DMA controller, which performs a data interface between the memory 1005 and the printer interface 1008, and outputs address information and control signals for outputting print data from the memory 1005, and further provides a control signal for data setting to the printer interface 1008. Is output. Since the address information output by the DMA controller 1007 is sequentially updated from a lower address to an upper address of the memory 1005 every time data is transferred from the memory 1005, the printer interface 1008 inputs print data in order from the first data to the last data. Output to the printer 1009.
A printer 1009 is a printer interface 1008
The print data received via is printed out from the head data.

With the above arrangement, the image data sequentially transferred from the head data of the lower address is printed out.

[0007]

According to the above-described configuration, it is possible to perform a dual operation in which data received via the NCU 1002 by DMA transfer is printed out by the printer 1009 and another original is read by the scanner 1001. is there. However, in the above-described conventional technology, the transferred print data has a large capacity, so that a huge amount of time is required for transfer of the print data, and there is a disadvantage that the time for print output becomes long. .

Therefore, it is conceivable to compress the print data by some method. However, there is a drawback that complicated processing is required and the apparatus becomes expensive, and processing by DMA transfer becomes difficult. there were.

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks, and has as its object to provide an image processing apparatus and method capable of outputting image data at a high speed with a simple configuration or processing.

[0010]

A reading means for reading the image data inputted to the first memory in a block unit of a predetermined size composed of a plurality of bits, and a block read by the reading means are adjacent to each other. Determining means for sequentially determining whether the block and the data content are equal,
When the blocks having the same data content continue as a result of the determination, the first data indicating the data content is output to the second memory, and the first tag indicating the continuous number is determined when the continuous number is determined. When a first output sequence for outputting information to the second memory and blocks having different data contents are consecutive according to the determination, a second data string indicating the data contents is output to the second memory. And output means for executing a second output sequence for outputting second tag information indicating the number of discontinuities to the second memory when the number of discontinuities is determined, wherein the second output In the sequence, at least two adjacent block data are held for the discrimination, and the discriminated block data is output to the second memory before the number of discontinuities is determined. To.

[0011]

With the above arrangement, a block composed of a plurality of bits is sequentially judged whether or not the data content is the same as that of an adjacent block. If they are equal, a continuous number is output following the data content. By outputting the data contents, it is possible to reduce the data amount and create output data that can be restored to the original data at high speed.

[0012]

An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a facsimile apparatus according to one embodiment of the present invention.

In FIG. 1, it is assumed that each is connected by a data bus.

Reference numeral 101 denotes a scanner which reads a set original by a CCD or the like and outputs image raster data to a data bus in order from the first data to the last data of one line.

An NCU 102 interfaces with a telephone line.

Reference numeral 103 denotes a decoder which converts data encoded by the MH code or the like received via the NCU 102 into image information, and outputs image raster data to the data bus in order from the first data to the last data of one line. .

Reference numeral 104 denotes a memory for sequentially storing image raster data output from the scanner 101 and the decoder 103 from the lower address N to the upper address X as shown in FIG.

Reference numeral 105 denotes a memory which stores print data output by the printer interface 108 in FIG.
As shown in (1), print data is accumulated from the first data to the last data in order from the lower address M to the upper address Y.

Reference numeral 106 denotes a CPU, which controls each unit of the apparatus. Also, the CPU 106 has an R as a work area.
An AM (not shown) is provided.

Reference numeral 107 denotes a DMA controller, which performs a data interface between the memory 105 and the printer interface 108. DMA controller 10
Reference numeral 7 outputs address information for outputting print data from the memory 105, a control signal of the memory 105, and a control signal for data setting to the printer interface 108.

Reference numeral 108 denotes a printer interface which inputs the print data from the first data to the last data in order, and transmits the input print data to the printer 109.
Output to

A printer 109 prints out print data received from the printer interface 108.

Reference numeral 110 denotes a DMA controller, which performs a data interface between the memory 105 and the print data creating unit 111. The DMA controller 110 outputs address information for inputting print data to the memory 105, a control signal for the memory 105, and a control signal for print data output of the print data creation unit 111.

Reference numeral 111 denotes a print data creation unit which, when image raster data is input, outputs a status signal BUSY indicating that print data is being created, and creates print data from the input data. After the print data is output, the printer data creation unit 111 cancels the output of the status signal BUSY.
6 confirms that print data has been created from the input image raster data.

FIG. 3 is a flowchart showing the flow of the operation according to the above configuration.

First, in step S301, image raster data read from the scanner 101 or image raster data received by the NCU 102 and expanded by the decoder 103 is transferred from the lower address N of the memory 104 to the upper address X in one line. Are stored in order from the first data to the last data.

Next, in S302, the CPU 106
After confirming the completion of the accumulation of the one-line image raster data in the memory 104, the process proceeds to S303,
The address of the last data of the line is set in the RAM of the work area as the last address X. Then in S304, D
The MA controller 110 sets the last address Y of the memory 105.

Next, in step S305, the data stored in the address X of the memory 104 is stored in the print data creation unit 1.
11 and in S306 the print data creation unit 111
To create and output print data. Here, when the image raster data is input, the print data creating unit 111 outputs a BUSY signal indicating that print data is being created. The details of the operation of the print data creation unit 111 will be described later.

Next, in step S307, the print data output from the print data creation unit 111 is stored at the address Y of the memory 105 by the DMA controller 110. In step S308, the DMA controller 110 sequentially updates and outputs address information to be output to the memory 105 from the upper address Y to the lower address M every time data is transferred from the print data creation unit 111 to the memory 105. In other words, if the end is decremented by one from the address Y and the end is detected in S309, the process proceeds to S310, and is decremented by one from the address X in the memory 104, and the processing is performed until the print data for all the image raster data of one line is stored in the memory 105 repeat. Subsequently, in S312, the DMA
The start address M of the memory 105 is set by the controller 107.

Next, in S313, the DMA controller 1
10 transfers the leading data stored at the address M of the memory 105 to the printer interface 108.
Subsequently, in step S314, the printer interface 108 outputs print data to the printer 109. Next, S31
In step S316, the address M is incremented by one.
The process is repeated until all data of the line has been output.

The processing described above is executed for the image raster data of all the lines.

Next, the operation of the print data creation unit 111 will be described in detail.

FIG. 4 is a block diagram showing a detailed configuration of the print data creation unit 111.

In FIG. 4, it is assumed that each is connected by a data bus. This data bus is an 8-bit data bus for inputting and outputting image raster data.

The data level "high" is H and "low" is L.

Reference numerals 401 and 402 denote 8-bit registers which store input data in response to a data control signal IOW. The register 401 stores data (DFF1) input from the 8-bit data bus, and outputs the data to the register 402. The register 402 receives and stores the output data (DFF2) of the register 401 according to the data control signal IOW. The data stored in the register 402 is output to the selector 413.

A counter 403 counts the number of bytes of input data in units of one byte. Counter 403
Is cleared at the start of activation of the print data creation unit 111, and is counted each time image raster data is input from the data bus. The counter 403 outputs a count result DCNT.

Reference numeral 404 denotes an 8-bit comparator.
The data DFF1 input to the register 401 and the data DFF2 input to the register 402 are compared, and when these data are equal, H is output, and when they are different, L is output. This output data is a 1-bit register 405
Is input to

Reference numeral 405 denotes a 1-bit register which stores the input data DFF3 and outputs a signal CMP0.

Reference numerals 406, 408, and 413 are selectors for appropriately selecting and outputting an input signal.

Reference numeral 407 denotes a 1-bit register which stores the input data DFF4 and outputs a signal CMP1.

Reference numeral 409 denotes a 1-bit register which stores the input data DFF5 and outputs a signal CMP2.

Reference numeral 410 denotes a sequencer for controlling the print data creation unit 111. The output signals CMP0 and CMP of the registers 405, 407, and 409 are provided.
1, CMP2 and count output value DCN of counter 403
When requesting the up / down counter 411 to count up by T, a request signal TUP is output, when requesting a countdown, a request signal TDW is output, and when clearing the count value of the up / down counter 411, a request signal TDW is output. A count clear signal TCLR is output. The increment and decrement of the count are based on the TCNT signal. The up / down counter 411 counts the number of data when down. When there is conversion data to be output, the sequencer 410 outputs to the selector 413 a selection signal SELB for selecting one of the stored data of the register 402 and the count value DCNT of the counter 403.

The selector 413 selects output data of the register 402 when the selection signal SELB output from the sequencer 410 is H, and selects count data of the counter 403 when SELB is L, and outputs the data to the data bus.

After outputting the selection signal SELB, the sequencer 410 outputs a DMA signal to the data bus interface 412.
The data transfer request signal TRQ for performing data transfer with the controller 110 is output as H.

A data bus interface 412 receives a signal TRQ from the sequencer 410 and
A data transfer request is made to the MA controller 110, and the DM
The A controller 110 stores the print data output by the print data creation unit 111 in the memory 105 as described above.
Transfer to

The data transfer request signal TRQ becomes L when the transfer of the created conversion data to the memory 105 is completed.

Next, the operation flow of the print data creation unit 111 will be described with reference to FIG. FIG. 6 shows output signals from the registers 405, 407, and 409, the output data count value of the counter 403, and a control signal output by the sequencer 410 at that time.

In FIG. 5, since the start of the print data creation unit 111 is started in S501, the counter 40
The count value of 3 is cleared and DCNT = 0.

Next, in S502, it is determined whether or not data has been input. When the data is input, the CPU 106 sets the last data of one line stored at the address X of the memory 104 in the print data creation unit 111 as the first byte of input data. In step S503, data input is started and a BUSY signal is output.

In S504, the count value of the counter 403 is still DCNT = 0, and the flow proceeds to S505. S50
In step S507, since the input is the first data, the process proceeds to step S507. S
At 507, the outputs of the registers 405, 407, and 409 are set to L. At S508, the data is not yet stored in the register 401, so that the data is not transferred, and the one-byte data input at S509 is stored in the register 401.

Next, in S510, since the count value DCNT of the counter 403 is 0, the process proceeds to S513, where the counter 403 counts the number of bytes 1 of the input data.
In step S514, the output of the BUSY signal is released.

Next, the CPU 106 sets the data stored at the address X-1 of the memory 104 in the print data creation unit 111 as the second byte of input data.

In S504, since DCNT = 1, S505
Proceed to. In step S505, the image raster data at the address X stored in the register 401 is compared with the image raster data at the address X-1 by the comparator 404, and if they are equal, H is set.
09, and the registers 405, 407, and 409 store this.

Next, in step S508, the image raster data at the address X stored in the register 401 is transferred to the register 402, and the register 402 stores this. In step S509, the input second-byte data is stored in the register 401.

In step S510, since the count value DCNT of the counter 403 is 1, the flow advances to step S511 to output a selection signal of the register 402 to the selector 413 in order to output data of the register 402. A data transfer request signal TRQ for performing data transfer with the DMA controller 110 is output as H. Upon input of the signal TRQ from the sequencer 410, the data bus interface 412 issues a data transfer request to the DMA controller 110, and the DMA controller 110 stores print data output by the print data creation unit 111 in the memory 105. Next, S
In step 513, the count value DCNT of the counter 403 is incremented by one, and in step S514, the BUSY signal is released.

Next, the CPU 106 sets the data stored at the address X-2 of the memory 104 as the third byte of input data in the print data creating unit 111.

In S504, since the count value DCNT of the counter 403 is 2, the flow proceeds to S515. In S515, the sequencer 410 inputs the input of the register 409 to the register 4
A selection signal for setting the input of the register 407 to the register 405 is output to the selector 406 and the selector 408.

Next, in step S516, the comparator 404 compares the image raster data at the address X-1 stored in the register 401 with the image raster data at the address X-2. If they are equal, H is determined (S517). (S5
18) Output to the register 405. The register 405 accumulates this by the image raster data setting signal WR.
At the same time, the stored data CMP0 of the register 405 at the time of inputting the image raster data of the address X-1 is replaced with the stored data CMP1 of the register 407 and the stored data
P1 is stored in the register 409, and the stored data CMP0 and CMP1 when the image raster data of the address X is input become CMP1 and CMP2, respectively.

Next, in step S519, the image raster data of the address X-1 stored in the register 401 is transferred to the register 402 simultaneously with the storage in the register 405, and the register 402 stores this. In step S520, the register 401 stores the image raster data at the address X-2. Subsequently, the sequencer 410 stores the stored data CMP0, C
It operates as follows based on the inputs of MP1 and CMP2.

First, in step S521, CMP0 = CMP1 = C
When MP2 = L, the image raster data at address X-1 and the image raster data at address X-2 are different,
This is the case where the image raster data at the address X is continuously different. At this time, the sequencer 41
A value of 0 is output to the up / down counter 411 in S523 as a setting for increasing the TCNT by setting the count-up signal TUP to H and the count-down signal to L.

Next, a selection signal of the register 402 is output to the selector 413, and a data transfer request signal TRQ for performing data transfer with the DMA controller 110 is output to the data bus interface 412 as H. When the data bus interface 412 receives the data transfer request signal TRQ from the sequencer 413, it issues a data transfer request to the DMA controller 110, and the DMA controller 110 accumulates the output data of the register 402 output from the print data creation unit 111 in the memory 105.
After transferring the output data of the register 402, the BUS is
The Y output is canceled, and the process proceeds to the setting of the next image raster data.

If it is determined in S525 that CMP1 = H, the image raster data at address X-1 and the address X
-2 image raster data are equal. At this time
At 527, the sequencer 410 sets the up / down counter 41
The setting is made such that the countdown signal TDW is set to H to bring TCNT down to 1. Here, the same number of bytes of the image raster data is counted by the up / down counter 411, and the process is terminated. In S514, the BUSY output is released, and the next data input is awaited. At this time, since the data has not yet been stored in the memory 105, the sequencer 410 does not output a selection signal to the selector 413.

When it is determined that CMP1 = L in S525, the input image raster data is different from the previous image raster data. This is a case where different data is continuously input or a case where the same data is continuously output and the process is ended. In the latter case, the continuous number is output.

At this time, the sequencer 410 sends the count-up signal TUP to the up-down counter 411 at S526.
The countdown signal TDW is both output as L. Thus, the counter TCNT is not counted. Further, a counter TCNT selection signal is output to the selector 413, and a data transfer request signal TRQ for performing data transfer with the DMA controller 110 is output to the data bus interface 412 as H. Upon input of the data transfer request signal TRQ from the sequencer 410, the data bus interface 412 issues a data transfer request to the DMA controller 110, and the DMA controller 110 stores continuously equal data counted by the up / down counter 411 in the memory 105. Then, the number of subsequent equal data is accumulated. When the output of the data to be stored in the memory 105 is completed in S528, the sequencer 410
A counter clear signal TCLR for clearing NT is output.

Next, a selection signal of the register 402 is output to the selector 413 and the data bus interface 412 is output.
Outputs a data transfer request signal TRQ for performing data transfer with the DMA controller 110 to H.
The data bus interface 412 is connected to the sequencer 410
When the data transfer request signal TRQ is input from the CPU, a data transfer request is made to the DMA controller 110, and the DMA controller 110 stores the image raster data of the register 402 output from the print data creation unit 111 in the memory 105 (S530). After transferring the output data of the register 402 in S531, the BUSY output is released in S514, and the next data input is awaited.

Since the operation of the print data creation unit 111 in the subsequent data input is the same as the data input of the third byte, the description is omitted here.

The image raster data stored in the memory 104 by the above processing is converted into print data and stored in the memory 105.

FIG. 7 shows an example of the input image raster data and the created print data. Here, for convenience, 1
Data for each byte is indicated by a decimal number. FIG. 7A shows input image raster data stored in the memory 104. FIG. 7B shows print data stored in the memory 105. In FIG. 7B, -2 is an identifier indicating that the data stored next is to be read two more times.
The blocks divided into three bytes in FIG. 7A are collectively stored as one block as 2-byte data.

FIG. 7C shows an example in which print data is created by reading data from the head data as usual. In this case, after reading data 35, it is known that equal data is continuous. The processing that cannot be done becomes complicated. However, in this embodiment, since the data is rearranged by a simple method as shown in FIG. 7B, no complicated processing is required. In this embodiment, one byte (8 bits) is defined as one unit, so that the CPU 106 can easily handle the data.

The print data stored in the memory 105 shown in FIG.
The printer 109 converts the data into image raster data and prints out the data.

Next, the operation of the printer 109 will be described. FIG. 8 is a block diagram showing the configuration of the printer 109.

In FIG. 8, reference numeral 801 denotes a receiving circuit which receives print data via the printer interface 108. A CPU 802 controls the operation of the printer.
It is. Reference numerals 803 and 804 denote memories that store print data. Reference numeral 805 denotes a print control unit that prints out and prints on recording paper. A line feed control unit 806 includes a motor and a drive unit for line feed of recording paper. 8
A carriage driving unit 07 includes a motor for driving the carriage for printing and a driving unit.

In the configuration described above, print data input via the printer interface 108 is sequentially stored in the memory 803 by the receiving circuit 801. FIG. 9A shows data stored in the memory 803. The count value is stored in the lower address,
Bytes of image data are accumulated, and thereafter, received data is successively accumulated in the order of higher addresses.

When the CPU 802 detects that the memory 803 has received the print data, the CPU 802 reads the count value stored in the lower part of the address. If the count value is a negative count, it indicates that the image data stored at the next higher address continues for the negative count. Therefore, the image raster data is developed and stored in the memory 804 accordingly. When the count value is positive, the image data stored at the next upper address is different data, and is sequentially read out until the next count value appears. The processing is performed as described above, and image raster data to be printed out is developed and stored in the memory 804 as shown in FIG. 9B.
The image raster data stored in the memory 804 is CP
Under the control of U802, the print control unit 801, the line feed control unit 806, the carriage drive unit 807, and the like read and print out the head data.

As described above, according to the present embodiment, when data is equal and continuous, this is regarded as one block, and when reading this data by adding an identifier before this block, first, Knowing that the following data is equal and continuous by the identifier,
It only needs to be read according to the identifier. The order of the data can be realized by a simple method such as reading from the last data of one line. Therefore, no complicated processing is required. Also, since the data capacity can be reduced, the data transfer time can be greatly reduced. Further, since the processing can be easily performed, the DMA transfer can be easily realized, and the dual operation can be easily performed without imposing a large load on the CPU. Further, since one byte is defined as one unit, the block can be easily handled by the CPU.

[0078]

As described above, according to the present invention, each block constituting the input image data is sequentially judged whether the data content is equal to that of the adjacent block, and if so, the data content and the number of continuations are output. Therefore, the output data amount can be reduced while making the output data easy.
Moreover, since each block is a block of a predetermined size composed of a plurality of bits, the processing can be performed easily and at high speed. Then, when restoring the original data, the data content is read out and the data is output for the number of times following the continuous number, so that the processing is also facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a facsimile apparatus according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating a memory management method of the facsimile machine.

FIG. 3 is a flowchart illustrating a flow of an operation of the facsimile apparatus.

FIG. 4 is a block diagram illustrating a configuration of a print data creation unit 111.

FIG. 5 is a flowchart showing the flow of the operation of the print data creation unit 111.

FIG. 6 is a diagram showing output signals of a sequencer 410 with respect to input data.

FIG. 7 is a diagram showing an example of the contents of memories 104 and 105.

FIG. 8 is a block diagram illustrating a configuration of the printer 109.

FIG. 9 is a diagram showing an example of the contents of memories 803 and 804.

FIG. 10 is a block diagram showing a configuration of a conventional facsimile machine.

[Explanation of symbols]

 101 scanner 102 NCU 103 decoder 104 memory 105 memory 106 CPU 107 DMA controller 108 printer interface 109 printer 110 DMA controller 111 print data creation unit

Claims (4)

(57) [Claims] An image data input to a first memory is duplicated.
Read in blocks of a certain size consisting of several bits
Read out step; and for the block read out in the read step ,
Determine sequentially whether the data content is the same as the adjacent block
Discriminating step; blocks having the same data content by the discrimination continue.
In this case, the first data indicating the data content is
Output to memory, and when the number of consecutive
Outputting first tag information indicating a number to the second memory
The first output sequence and blocks having different data contents are continuous according to the determination.
In such a case, the second data string indicating those data contents
Output to the second memory, and the number of discontinuities is determined
The second tag information indicating the number of discontinuities in the second memo.
Control step for executing a second output sequence for outputting to a memory
And in the second output sequence, at least
Also stores two adjacent block data for the above-mentioned determination.
The number of discontinuities determines the block data that has been
Output to the second memory before the
Image processing method. 2. The method according to claim 1, wherein the image data input to the first memory is duplicated.
Read in blocks of a certain size consisting of several bits
Reading means for reading out; and for the block read by the reading means,
Determine sequentially whether the data content is the same as the adjacent block
Determining means; blocks having the same data content as a result of the determination continue
In this case, the first data indicating the data content is
Output to memory, and when the number of consecutive
Outputting first tag information indicating a number to the second memory
The first output sequence and blocks having different data contents are continuous according to the determination.
In such a case, the second data string indicating those data contents
Output to the second memory, and the number of discontinuities is determined
The second tag information indicating the number of discontinuities in the second memo.
Control means for executing a second output sequence for output to the memory
And in the second output sequence, at least
Coercive also two adjacent blow Kkudeta for the determination
The number of discontinuities determines the block data that has been
Output to the second memory before the
Image processing device. And reading data output to said second memory.
Restoring means for reading out and restoring, wherein the read address of the second memory in the restoring means
The second direction in the reading means based on the
1 to determine the read address direction of the memory.
3. The image processing apparatus according to claim 2, wherein 4. The method according to claim 1, further comprising the step of :
And printing means for executing printing based on the
The image processing apparatus according to claim 3, wherein