JP3092536B2 - Parallel pixel value interpolation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pixel value interpolation method for expanding compressed moving image data, and more particularly to a parallel pixel value interpolation method for processing a plurality of sets of pixel values in parallel.

[0002]

2. Description of the Related Art Conventionally, specially designed hardware has been used for compression and decompression devices for storing and communicating high-quality moving image data. that is,
MPEG (Moving Picture codin) is an international standard
g Experts Group).
This is because a huge amount of calculation is required to decompress moving image data compressed in accordance with the MPEG standard in real time. However, due to the recent high performance of microprocessors, it is becoming possible to realize the microprocessor only with ordinary microprocessor software without special hardware.

The compression and decompression algorithms of MPEG are described, for example, in "Communications of the ABCM, Vol. 34, No. 4, April 1991 (Co.
mmunications of the ACM, Vol. 34, No. 4, April, 1991)
Is described in detail. MPEG decompression algorithms are roughly the decoding processing of variable length codes, inverse quantization processing,
It consists of an inverse discrete cosine transform process and a motion compensation process. Among them, the motion compensation process utilizes temporal redundancy of a moving image, and is a process of extracting a part of an image from a previously expanded frame and restoring the image. The position of the image to be clipped is determined by a parameter called a motion vector.

An image that is cut out and restored is a square area called a macroblock consisting of 16 pixels in the vertical direction and 16 pixels in the horizontal direction, and the value of each pixel is represented by 8 bits. At this time, pixel value interpolation processing may be required. This processing is equivalent to calculating the average value of the pixels at the corresponding positions in two square images each having 16 pixels vertically and 16 pixels horizontally.

Conventionally, when pixel value interpolation processing is performed by software of an ordinary microprocessor, calculation is performed for each pixel. A conventional calculation procedure will be described with reference to the flowchart of FIG. In order to calculate an average value of two 8-bit pixel values x0 and y0, first, two values are read from a memory into a register (501 and 50).
2) The sum sum is obtained (503), a constant 1 is added for rounding (504), and a bit is shifted right by one bit to obtain a0 (505). By the above procedure, the average value a0
Is stored in the memory (506). Here, the step of calculating the address of the memory is omitted for simplicity. As described above, according to the conventional calculation procedure, the interpolation processing of two pixel values can be executed in six steps.

[0006]

However, as described above, in the conventional calculation procedure, since the pixel value interpolation processing is executed for each pixel, the number of steps required to execute the software by the microprocessor becomes enormous. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a parallel pixel value interpolation system which realizes a pixel value interpolation process with a smaller number of steps.

[0008]

In order to achieve this object, a parallel pixel value interpolation method according to the present invention employs a 32-bit value X and Y consisting of four sets of 8-bit values of predetermined image data.
A 32-bit data reading means for reading the data, an odd sum detecting means for detecting whether or not the result of adding the 8-bit values at the same position of X and Y becomes an odd number, and X and X based on the detected result. Bit correction means for adding 8-bit values at the same position of Y and correcting X and Y to generate #X and #Y so that the addition result is an even number; #X and #Y
, And a shift means with a carry that collectively executes pixel value interpolation processing for four pixels by shifting one bit to the right including the added result and the carry thereof.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a parallel pixel value interpolation system according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 4, there is shown an embodiment of the parallel pixel value interpolation method according to the present invention. Hereinafter, the present invention is described as MP
One embodiment applied to a case where a pixel value interpolation process is performed in a motion compensation unit of a decoder that expands moving image data compressed in accordance with the EG standard will be described.

FIG. 1 is a block diagram showing a functional configuration of a pixel value interpolation system according to the present embodiment. Here, it is assumed that the values of adjacent pixels on the screen are arranged at consecutive addresses on the memory.

The 32-bit data (X) reading means 101 and the 32-bit data (Y) reading means 10 shown in FIG.
2 is a data reading means for loading a register with a 32-bit value X consisting of four sets of 8-bit values and a 32-bit value Y consisting of four sets of 8-bit values stored in consecutive addresses of a memory, respectively. It is.

The odd sum detecting means 103 reads the 2
This is an odd sum detecting means for detecting whether or not the result of adding the 8-bit values at the same position of the two 32-bit values X and Y becomes an odd number.

The bit correction means 104 and 105 calculate the values of X and Y based on the result of the odd number sum detection means 103 so that the result of adding the 8-bit values at the same positions of X and Y becomes an even number. This is a means for correcting a bit value to be corrected. The results corresponding to the uncorrected X and Y after the correction are #X and #
Notated as Y.

The adding means 106 calculates the corrected values #X and #X
This is a means for adding Y. Shift means with carry 10
Reference numeral 7 denotes a shift unit with a carry that shifts one bit to the right, including the result added by the adder 106 and its carry. Therefore, according to this means, a result obtained by dividing by "2" is obtained. The average storage unit 108 is a storage unit for storing the calculated average in a memory.

The principle of operation of the pixel value interpolation method according to this embodiment will be described with reference to FIG. In a microprocessor having a 32-bit wide register and a 32-bit wide arithmetic unit, four sets of 8-bit values (x3, x2, x1,.
x0) and (y3, y2, y1, y0) are 32
It is stored in registers 201 and 202 having a bit width.
In this case, the average value of the 8-bit values x3 and y3, the average value of the 8-bit values x2 and y2, the average value of the 8-bit values x1 and y1, and the average value of the 8-bit values x0 and y0 are calculated. The procedure will be described. Here, only the calculation of the average value of the 8-bit values x3 and y3 and the average value of the 8-bit values x2 and y2 will be focused.

First, four sets of 8-bit values (x3, x2, x
1, x0) and four sets of 8-bit values (y3, y2, y1, y
0) with an ordinary ALU, an 8-bit value x
Consider the value of the sum of 3 and y3 and the value of the sum of the 8-bit values x2 and y2. The sum of the 8-bit values x2 and y2 is the addition result 2
As shown in 08, it is a 9-bit value.

Similarly, the sum of the 8-bit values x3 and y3 is a 9-bit value as shown in the register 211. But,
Here, when the most significant bit 210 of the addition result 208 is “1”, since the position overlaps with the least significant bit 212 of the register 211, if the least significant bit 212 of the register 211
Is “1”, a carry occurs, resulting in an 8-bit value x
The sum of 3 and y3 may be destroyed.

If the least significant bit 212 of the register 211 storing the sum of the 8-bit values x3 and y3 is always "0"
Then such a problem does not occur. Therefore, if the least significant bits of the 8-bit values x3 and y3 can be set as corrected # x3 and # y3 in advance so that the least significant bit 225 of the addition result 224 is always "0", a normal ALU is used. Four sets of corrected 8-bit values (#x
3, # x2, # x1, # x0) and four sets of the corrected 8-bit values (# y3, # y2, # y1, # y0), the corrected 8-bit values # x2 and # x2 The value of the sum of y2 does not destroy the value of the sum of the corrected 8-bit values # x3 and # y3.

The addition result 227 includes four sets of corrected 8-bit values (# x3, # x2, # x1, # x0) and four sets of corrected 8-bit values (# y3, # y2, # y1,. # Y0). Where the most significant bit 229
Are stored as carry, and the other 32 bits are stored in registers. 33 of the addition result 227
If the bit value is shifted right by one bit, as shown in the 32-bit register 230 storing the result of shifting right by one bit with carry, (# x3 + # y3) / 2 and (# x2 + # y2) / 2 And (# x1 + # y1) / 2 and (# x0 + # y0) / 2 are obtained.

The least significant bits of the corrected 8-bit values # x3 and # y3 are compared with the least significant bits of x3 and y3 such that if either one is "1", both are "1". I do. By doing so, the least significant bit of the sum of the corrected 8-bit values # x3 and # y3 is always "0", and the result of (x3 + y3) / 2 matches the result of (# x3 + # y3) / 2. 8-bit values # x2, # y2, # x1 after correction
And # y1 and # x0 and # y0.

FIG. 3 is a flowchart showing a processing procedure in the parallel pixel value interpolation method according to the present embodiment. First, 32-bit data X and data Y are read from a memory into registers (301 and 302). Here, each bit of the data X and Y is represented as follows.

X = x ₃ ⁷ , ..., x ₃ ¹ , x ₃ ⁰ , x ₂ ⁷ , ..., x ₂ ¹ , x ₂ ⁰ , x ₁
⁷ , ..., x ₁ ¹ , x ₁ ⁰ , x ₀ ⁷ , ..., x ₀ ¹ , x ₀ ⁰ Y = y ₃ ⁷ , ..., y ₃ ¹ , y ₃ ⁰ , y ₂ ⁷ , ..., y ₂ ¹ , y ₂ ⁰ , y ₁ ⁷ , ..., y ₁ ¹ , y ₁
⁰ , y ₀ ⁷ , ..., y ₀ ¹ , y ₀ ⁰

X and Y each store four sets of 8-bit values. The pixel value data is composed of 8 bits, and the pixel values at adjacent positions are stored at adjacent addresses on the memory. Thus, the four pixel values can be read from the memory to the register in one step. Next, X
32-bit value #mask for bit correction from Y and Y
Is calculated (304). Here, each bit of #mask is represented as follows.

[0024] ^{_{# mask = m 3 7, ...}} , m 3 1, m 3 0, m 2 7, ..., m 2
¹ , m ₂ ⁰ , m ₁ ⁷ , ..., m ₁ ¹ , m ₁ ⁰ , m ₀ ⁷ , ..., m ₀ ¹ , m ₀ ⁰

Each bit of #mask satisfies the following equation. If _{^{m i j = x i j XOR}} y i j if j = 0 = 0 otherwise

That is, when the least significant bits of the pixel values at the positions corresponding to X and Y are compared with each other, if either one is "1", the bit at the corresponding position of #mask becomes "1". . A bit-corrected #X is calculated by calculating a bitwise OR of X and #mask (306),
A bit-corrected #Y is calculated by calculating a bitwise OR of Y and #mask (307), a sum sum of #X and #Y is calculated (308), and the sum is calculated. The sum is shifted right by one bit including the carry bit to calculate average (309), and average is calculated.
ge is stored in the memory (310).

FIG. 4 is a flowchart showing the operation of # in step 303 of FIG.
This is a detailed description of a method of calculating a mask value. Registers 401 and 402 represent the read 32-bit data X and Y. The result of calculating the exclusive OR for each bit of the registers 401 and 402 is the register 403.
In order to extract only the least significant bit when the register 403 is divided every 8 bits, 0 is expressed in hexadecimal notation.
When the value of the register 404 that is x01010101 and the logical AND for each bit are taken, #mask is obtained in the register 404.

That is, as described in the section of [Prior Art], in the related art, six steps were required for pixel value interpolation for one pixel, but if the pixel value interpolation method in the present embodiment is used, Processing for four pixels can be executed in nine steps. Therefore, only 2.25 steps are required for one pixel. Therefore, the speed is twice or more as compared with the conventional technology. The operations required for the present embodiment are only addition, bit-by-bit logical operation, and bit shift with carry, and can be executed by a general microprocessor having a 32-bit register.

Further, if the method described here is applied to a microprocessor having a 64-bit register, pixel value interpolation processing for eight pixels can be executed in nine steps.

In the above-described embodiment, the pixel value interpolation processing for four pixels is executed in parallel by effectively using the 32-bit width register of the microprocessor. It is easy to collectively store four sets of 8-bit data in a 32-bit register. However, if the 32-bit data are added together by the normal microprocessor ALU to obtain the addition result of the 8-bit data, the carry of the addition result of the 8-bit data stored in the lower bit is changed to the upper bit. Will destroy the addition result of the 8-bit data stored in, and a correct result cannot be obtained. In the present embodiment, the effect of carry does not propagate to the higher order by correcting data before addition in advance. Further, a correction process for rounding is performed at the same time. As a result, the number of steps required for calculation per pixel in the pixel value interpolation processing can be significantly reduced.

Although the above embodiment is an example of a preferred embodiment of the present invention, the present invention is not limited to this embodiment, and various modifications can be made without departing from the gist of the present invention.

[0032]

As is apparent from the above description, the parallel pixel value interpolation method of the present invention employs four sets of eight image data of predetermined image data.
The 32-bit values X and Y consisting of bit values are read, and it is detected whether or not the result of adding the 8-bit values at the same position of the read X and Y becomes an odd number. Based on the detected result, 8-bit values at the same position of X and Y are added together, and X and Y are corrected so that the added result becomes an even number to generate #X and #Y. Further, #X and #Y are added, and 1 is added to the right including the added result and its carry.
By performing bit shifting, pixel value interpolation processing for four pixels is collectively executed. Therefore, data before addition is corrected in advance, and a correction process for rounding is also performed at the same time.

As a result, the influence of carry does not propagate to higher places. In addition, since the pixel value interpolation processing for four pixels is performed collectively, the number of steps can be reduced to less than half of the conventional calculation procedure. In other words, it is possible to greatly reduce the number of calculation steps required for motion compensation processing and the number of steps required for calculation per pixel in pixel value interpolation processing in the decompression processing of moving image data compressed in accordance with MPEG. Becomes

[Brief description of the drawings]

FIG. 1 is a block diagram showing a functional configuration of an embodiment of a parallel pixel value interpolation method according to the present invention.

FIG. 2 is an explanatory diagram showing an operation principle.

FIG. 3 is a flowchart illustrating an example of a calculation procedure.

FIG. 4 is an explanatory diagram showing an operation example of the odd sum detecting means of FIG. 1;

FIG. 5 is a flowchart illustrating an example of a calculation procedure of a conventional pixel value interpolation method.

[Explanation of symbols]

101, 102 32-bit data reading means 103 Odd sum detection means 104, 105 Bit correction means 106 Addition means 107 Shift means with carry 108 Average value storage means 201, 202 32-bit registers 203, 205, 208, 209 Addition results 213, 214 32-bit registers 215, 218, 221 and 224 storing bit-corrected values Addition result 227 Addition result 230 32-bit registers 301 and 302 storing the result of shifting right by one bit with carry 32-bit data read processing 303 #mask calculation processing 306, 307 Bit correction processing 308 Addition processing 309 Right 1-bit shift processing with carry 310 Average value storage processing 401, 402 32-bit register in which data X and Y are stored 403 32-bit register storing mask 404 3 storing hexadecimal 0x010101
2-bit register 405 32-bit register in which #mask is stored

Claims (1)

(57) [Claims] 1. 32-bit data reading means for reading 32-bit values X and Y consisting of four sets of 8-bit values of predetermined image data, and adding 8-bit values at the same position of X and Y to each other An odd sum detecting means for detecting whether or not the result is an odd number; and adding the 8-bit values at the same positions of X and Y based on the detected result so that the added result becomes an even number.
A bit correcting means for correcting X and Y to generate #X and #Y, adding #X and #Y, and shifting right by one bit including the added result and its carry. A parallel pixel value interpolation method comprising: a shift unit with a carry that collectively executes pixel value interpolation processing for four pixels.