JP3088472B2 - Fourier transform device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Fourier transform apparatus for performing a discrete Fourier transform at a high speed. The Fourier transform apparatus includes a method of inputting and transforming N data to be subjected to Fourier transform in parallel at multiple points, and a butterfly circuit shown in FIG.
Multiple units are cascaded via a data rearrangement circuit.
Radix consisting formation 2 Fourier transform pipeline (base 2F
FT pipeline).

In the former, when the number of Fourier transform points (the number of FFT points) increases, the degree of parallel input increases, and a large number of hardware is required. Even if such hardware is prepared, fast conversion may not be required depending on input data, and preparing a Fourier transform circuit (FFT) with high parallelism is a waste of hardware. May be.

In the latter case, the amount of hardware is smaller than that in the former case, but the degree of parallelism is low. An object of the present invention is to provide a Fourier transform apparatus that can flexibly determine the degree of parallelism according to the number of FFT points and the required processing speed so as not to waste hardware.

[0004]

2. Description of the Related Art FIG. 4 shows a conventional arrangement for performing Fourier transform on data input in parallel at multiple points. The figure shows a configuration in which the number of FFT points N = m × n (where m and n are positive integers) are input in parallel for each m points and converted. When performing Fourier transform on N data, first, m-point Fourier transform is performed on m points of N = m × n (m and n are positive integers). next,
The obtained m pieces of data are multiplied by a twist coefficient. The above processing is performed n times, and the obtained data of N points are rearranged. Then, for the data at the N points, m = n × k
(N and k are positive integers), and the data of n pieces is converted in k parallel n-point FFTs. By performing this processing n times, N Fourier transform results are obtained.

In FIG. 1, reference numeral 31 denotes a data rearrangement circuit which rearranges time-series data in parallel. Reference numeral 32 denotes an m-point FFT circuit that inputs m-point data in parallel and performs Fourier transform on the m-point. 33 is the m-point FF
A torsion coefficient multiplying unit for multiplying the output of T by a torsion coefficient, 34 is a data rearranging circuit for N results of performing m-point Fourier transform n times, and 35 to 36 are n-point Fourier transform circuits (n-point F
FT circuit). Time series data (N = m × n)
Are rearranged into parallel data in the data rearrangement circuit 31 and input to the m-point FFT circuit 32 in m-point parallel.

The data obtained by the m-point FFT circuit 32 is multiplied by a coefficient in a torsion coefficient multiplier 33. The N pieces of data obtained by performing the m pieces of parallel data n times by the m-point FFT are rearranged in the data rearranging circuit 34 to obtain k n-point FFT circuits 3.
5 to 36 and Fourier-transformed. The processing is n
By performing the conversion twice, N conversion results are obtained.

When the number of input points is represented by m = 2 ^s , a conversion result can be obtained by repeating the radix-2 Fourier transform s times. A radix-2 FFT pipeline for processing 16 points will be described with reference to FIGS. FIG.
Indicates a butterfly circuit used in the radix-2 FFT pipeline. The operation of the butterfly circuit 38 shown in the figure is based on two inputs A and B as outputs A + W ^S × B and A−W.
^S × B is obtained (where W = exp (−2π × j
/ N), s is an integer).

FIG. 6 shows the flow of processing in a 16-point radix-2 FFT pipeline. In the figure, 40 to 41 are registers for storing input data of 16 points each of 8 points (SR1A and SR1B will be described later).
50 is a butterfly circuit (BUT1), where W = ex
p (−2πj / 16) and s = 0.

Registers 42 to 43 store data converted by the butterfly circuit 50 (SR2A, SR2).
2B will be described later). The meaning of the figure is as follows. The input data of 16 points is input to the registers 40 and 41. The data at points 0 and 8 of the registers 40 and 41 are input to the butterfly circuit 50, and the sum is stored at point 0 of the register 42. The difference data is stored at point 0 of the register 43. Each process is represented by 1C0 and 1D0.

Similarly, point 1 of register 40 and register 4
The point 9 of 1 is subjected to arithmetic processing in the butterfly circuit 50, the sum is stored in the point 1 of the register 42, and the difference is stored in the register 4
3 at point 1. 1C1, 1D1 for each processing
And The same processing is performed for points 2 to 7 of register 0 and points 10 to 15 of register 41,
7. Stored in points 2 to 7 of register 43. The respective processes are designated as 1C2 to 1C7 and 1D2 to 1D7.

FIG. 7 shows a part following the processing in FIG. In the figure, 42 and 43 are registers, which indicate the registers 42 and 43 in FIG. Reference numerals 44 and 45 denote registers for storing the results obtained by calculating the data at the points of the registers 42 and 43 by the butterfly circuit (SR3A, S3).
R3B will be described later). Reference numeral 51 denotes a butterfly circuit (W = exp (-2πj / 16), s = 0 or 4). The sum and difference of the value obtained by multiplying the data at point 0 of the register 42 and the data at point 4 of the register 42 by W ⁰ are obtained, the sum is stored at the point 0 of the register 44, and the difference is stored at the point 4 of the register 44. I do. Similar processing is performed for points 1 to 3 of the register 42 and points 5 to 6 of the register 42, and the sum is stored in points 1 to 3 of the register 44 and the difference is stored in points 5 to 7 of the register 44. The processing for each sum is 2C0 to 2C3, and the processing for the difference is 2D0 to 2D3.

In the processing for each point of the register 43,
And data points 0-3 in the butterfly circuit 51, the data points 4-7 of the register 43 is performed by taking the sum and difference for values multiplied by W ^4, point a sum of the operation result register 45 0 3 and the differences are stored at points 4-7.
In each process, the sum process is 2C4 to 2C7, and the difference process is 2D4 to 2D7.

FIG. 8 shows a process following the result of FIG. 4
Reference numerals 4 and 45 denote registers 44 and 45 in FIG. 4
Reference numerals 6 and 47 are registers for storing the results of arithmetic processing of the data stored in the registers 44 and 45 by the butterfly circuit (SR4A and SR4B will be described later). 52 is a butterfly circuit. The sum and difference of values obtained by multiplying the data at point 0 of the register 44 and the data at point 2 of the register 44 by W ⁰ are stored at points 0 and 2 of the register 46. Similarly, register 4
The data obtained by multiplying the data at point 1 of point 4 and point 3 of register 44 by W ⁰ is added to the difference and the difference in butterfly circuit 52 and stored in points 1 and 3 of register 46. 3C for each process
0 to 3C1 and 3D0 to 3D1.

At points 4 to 7 of the register 44, the points 6 to 7 are multiplied by W ⁴ and placed in the butterfly circuit 52, and the same processing is performed. Store. Each processing is 3C2-3C3,
3D2 to 3D3. In the processing of points 0 to 3 of the register 45, the points 2 to 3 are multiplied by W ² , the same processing is performed in the butterfly circuit 52, and the sum and difference calculation results are stored in the points 47 to 0 of the register 47. I do. These processes are 3C4 to 3C5 and 3D4 to 3D5. Register 45
In the points 4 to 7, the value of the data in the points 6 to 7 is changed to W ⁶
And the same processing is performed in the butterfly circuit 52, and the sum and difference calculation results are stored in points 4 to 7 of the register 47. 3C6-3C7, 3D6-3D
7 is assumed.

FIG. 9 shows a continuation of the processing in FIG. In the figure, 48 and 49 are registers, which indicate the registers 46 and 47 in FIG. 8 (SR4A and SR4B will be described later). Reference numerals 50 and 51 denote registers for storing the operation results in the butterfly circuit. 53 is a butterfly circuit. The sum and difference of the values obtained by multiplying the data at point 0 and the data at point 1 of the register 48 by W ⁰ are calculated by a butterfly circuit, and the results are stored at points 0 and 1 of the register 50, respectively. As a result, at point 0 of the register 50, a result is obtained in which X (n) as a result of Fourier transform corresponds to n = 0. Similarly, at point 1, a result corresponding to n = 8 is obtained.

Regarding the other points of the registers 48 and 49,
Multiplied by W ^s of the s shown which is determined for each treatment, a sum and difference in the butterfly circuit 53 is stored in the register 50. At each point in the register 50, a Fourier transform result X (n) corresponding to each n is obtained.

FIGS. 10 to 11 show a 16-point radix 2 of one input.
1 shows an apparatus configuration of an FFT pipeline. In FIG. 10, reference numeral 801 denotes serial bit input data, and 801 'denotes a demultiplexer (DMX) for distributing input data of 16 points to the registers SR1A and SR1B. Reference numerals 802 and 803 denote registers (SR1A) for storing the upper half and the lower half of the 16-point data, respectively.
Reference numerals 4805 denote registers (SR1B) for storing upper half data and lower half data of 16 points of data, respectively.
The registers SR1A and SR1B store 16 pieces of data alternately for each storage cycle.

Reference numeral 806 denotes a switch (SW) for switching data input to the butterfly circuit (BUT1) to data from the register SR1A or SR1B. 80
Reference numerals 7 and 808 denote multiplexers (MPXs) which store data to be input to the butterfly circuit in registers SR1 and SR8, respectively.
A or switch to data from SR1B. 809 is a butterfly circuit (BUT1),
A data input A, a circuit taking the sum and difference for multiplied by a factor W ⁰ twist to the input B data. 810 is a torsion coefficient for multiplying the input data.

Reference numeral 811 denotes a register (SR2B) for storing a calculation result of the difference of the butterfly circuit 809. A switch 812 is used to switch data to be selected.
Numerals 813 and 814 are multiplexers (MPX) of changeover switches. 815 is a register (SR2A) for storing data on the side selected by the MPX 813, and 816 is a butterfly circuit (BUT2), which is a register SR2A.
And the data selected by the multiplexer 814 (input B) are input, the input B is multiplied by the torsional coefficients (W ⁰ , W ⁴ ), and the sum and difference of the inputs A and B are calculated. 81
7 is a as a definition of the multiplication twist coefficient of the input B (W ^0, W ^4), for example, multiplied by W ⁰ for 4 cycles in the processing clock cycle of the pipeline, so multiplying W ⁴ in the subsequent 4 cycles It circulates in

In FIG. 11, reference numeral 901 denotes a register (SR
3B) and 902 are changeover switches (SW) for selecting data, and 903 and 904 are multiplexers (MPX) for selecting data. 905 is a shift register (S
R3A), 906 is a butterfly circuit for calculating the input A ^data, the sum and difference for multiplied by a factor twist to the input B data. 906 ′ is the torsion coefficient (W ⁰ , W ⁴ , W
² , W ⁶ ), and circulates in the above order according to the clock of the pipeline.

Reference numeral 907 denotes a shift register (SR4A). A switch 908 for selecting data (S
W), 909 and 910 are multiplexers (MPX) for selecting data. 911 is a shift register (SR4
B) and 912 are butterfly circuits that take the sum and difference of the result of multiplying the input A data and ^the input B by the torsion coefficient. Reference numeral 913 denotes a torsional coefficient (W ⁰ , W ⁴ , W ² , W
^6, there is the ^{W 1, W 5, W 3} , defining a W ^7),
It circulates in the above order according to the pipeline clock.

FIGS. 12 and 13 show two of FIGS. 10 and 11.
The operation of the point radix FFT pipeline will be described. FIG. 12 shows the first cycle in the pipeline, and FIG. 13 shows the second cycle.

In FIGS. 12 and 13, SR1AW, S
R2AW and SR3AW are registers SR1A and S1, respectively.
Indicates writing of R2A and SR3A. SR1BW, S
R2BW and SR3BW are SR1B, SR2B,
Indicates writing of SR3B. SR1AR, SR2A
R and SR3AR are registers SR1A and SR2, respectively.
A, reading of SR3A. SR1BR, SR2
BR and SR3BR are SR1B, SR2B, and SR, respectively.
3B represents readout.

BUT1out, BUT2out, BUT
3out is a butterfly circuit BUT1, BUT, respectively.
2 and BUT3. 1st cycle (1st)
In the clock cycles 1 and 2, the SR1B reads the 0th (0-point data) and the 8th (8-point data) (each stored in the SR1B in the previous processing cycle). Then, each data is input to the butterfly circuit (BUT1), and the operation (1C0, 1D0) is performed in clock cycles 3 and 4, and the clock cycles 4 to 5 are performed.
Store the result in SR2A, SR2B. The same processing is performed up to clock C, and each operation result is output to SR2A, S2
Each data is stored in R2B.

In clocks D and E in the first cycle, the data in process 1C0 stored in SR2A and the data in process 1C4 output from BUT1 are input to BUT2 (816), respectively. The data of SR2A is input to the BUT2 input terminal A via the input to the terminal B of the BUT2. Then, processes 2C0 and 2D0 are performed in the first cycle clock F to the second cycle clock 0, and stored in the registers SR3A and SR3B in the second cycle clocks 1 and 2, respectively.

In the first cycle of clocks D to E, S
The data written in R2B is transferred to SR2A, and data (1D0) stored in SR2A is input to input A of BUT2 in clocks 5 to 6 in the second cycle,
At the same time, the data (1D4) of SR2B is input to BUT2. Then, the data is read out at clocks 5 and 6 in the second cycle and arithmetically processed at clocks 7 and 8, and the results are stored in SR3A and SR3B at clocks 9 to A. Similar processing is sequentially performed in each clock cycle, and the final calculation result is output from the BUT 4.

[0027]

As described above, configuring hardware with a high degree of parallelism can increase the processing speed, but requires a large amount of hardware and requires a high data input speed. In some cases, the radix-2 FFT pipeline may not be able to cope sufficiently. SUMMARY OF THE INVENTION It is an object of the present invention to provide a Fourier transform apparatus that can flexibly determine a required degree of parallelism so as not to waste hardware, according to the number of FFT points and a required processing speed.

[0028]

SUMMARY OF THE INVENTION According to the present invention, a radix 2F is provided at a stage before input data to be Fourier-transformed is first inputted.
A plurality of FT pipelines are arranged in parallel to perform parallel processing, and two parallel FFTs having a score equal to the number of radix-2 FFT pipelines arranged in parallel in the preceding stage are arranged in the subsequent stage, and high-speed processing can be performed with relatively few hardware. I did it.

FIG. 1 shows a basic configuration diagram of the present invention. The figure is m
A number of point radix-2 FFT pipelines are arranged in parallel and N =
The configuration in the case of performing Fourier transform of mxa data is shown. The number of input data points and the degree of parallelism are not limited to this example.

In the figure, reference numeral 1 denotes input data to be Fourier-transformed, where N = m × a. 2 is base 2
This is a preceding stage in which a number of FFT pipelines are arranged in parallel.
Reference numeral 3 denotes a multiplication unit that multiplies data output in parallel from the preceding stage by a torsion coefficient. Reference numeral 4 denotes two parallel FFTs having the same number of processing points (point a) as the number of radix-2 FFT pipelines arranged in parallel in the preceding stage. 5-0 to 5- (a-1) are radix-2 FFT pipelines. Reference numerals 7 to 8 denote a point FFT circuits.

[0031]

[Function] Fourier transform of N points,

[0032]

(Equation 9)

(However, n = 0 to N-1, k = 0 to N-1
), The N points to be transformed are decomposed into m × a (m and a are integers). And n = m × ni + n
j, k = a × ki + kj (where ni = 0 to (a−
1), nj = 0 to (m-1), ki = 0 to (m-1),
If kj = 0 to (a-1)), Equation 1 becomes

X (n) = X (ni, nj)

[0035]

(Equation 10)

(Where, W _N = exp
_{(-2πj / N), W m} = exp-2πj / m), W a
= Exp (-2πj / a)). In the above equation,

[0037]

[Equation 11]

[0038]

(Equation 12)

[0039]

(Equation 13)

## EQU4 ##

Equation (3) represents the Fourier transform of a set m of m points. If it is determined that m = 2 ^s , X1 can be processed by a radix-2 FFT pipeline. Therefore, the above equation (3) is processed by arranging a plurality of a m number of radix-2 FFT pipelines in parallel in the preceding stage of the present invention.

Next, Equation 4 can be processed by inputting the outputs of the radix-2 FFT pipeline of the preceding stage in parallel and multiplying by the torsional coefficient (twisting coefficient multiplication processing). Next, since Equation 5 means an a-point FFT, 2a parallel data output from the torsion coefficient multiplication unit can be processed by two a-point parallel FFTs.

That is, a number m of m-point radix-2 FFTs in the preceding stage
When a pipeline is used, 2a parallel outputs are obtained because two parallel outputs are provided per pipeline.
Data is multiplied by a torsion coefficient, and two a-point parallel FFTs are performed.
To get the final result.

[0044]

FIG. 2 shows an embodiment in which a 16-point FFT is performed.
Shown in Assume that a 16-point FFT is processed with a parallelism of 4 wide. Since the degree of parallelism of the radix-2 FFT pipeline is 2 wide, two radix-2 FFT pipelines are required in parallel. Radix 2 FFT because 16 data are divided into two
The score of the pipeline will be 8 points. Accordingly, the score of the two subsequent parallel FFTs is 2. FIG. 2 shows a configuration for performing the above 16-point processing.

In the figure, 20 is input data of 16 points,
Reference numeral 21 denotes a pre-stage unit for processing 16 points of input data with a degree of parallelism of 4, 22 denotes a torsion coefficient multiplying unit for performing 4-parallel processing, 23
Is the latter part for obtaining the final result of 16 points from the data of 4 parallel. 24, 25 are 8-point radix-2 FFTs
It is a pipeline. 26 to 29 multiply the four parallel input data by a torsion coefficient, and 30 to 33 cyclically move the torsion coefficient to sequentially multiply the input data by the torsion coefficient. 34 and 35 are two 2-point FFTs
It is. 36 is the final calculation result of 16 points. 16 points F
Decomposing the FT into 8 × 2 is as follows.

[0046]

[Equation 14]

(Where n = 0 to 7, k = 0 to 1)
Integer, W = exp (-2π × j / 16)) n = 8 × n
i + nj, k = 2 × ki + kj (where ni = 0 to 1,
nj = 0-7, ki = 0-7, kj = 0-1), X (n)

[0048]

(Equation 15)

[0049]

(Equation 16)

In the above equation,

[0051]

[Equation 17]

[0052]

(Equation 18)

[0053]

[Equation 19]

In the former part,

[0055]

(Equation 20)

In the conversion process of the torsion coefficient multiplication unit,

[0057]

(Equation 21)

Is performed. In the latter part,

[0059]

(Equation 22)

Is performed.

In the preceding part, [X1 (nj, 0)] is obtained in an 8-point radix-2 FFT pipeline (0). [X1 (nj, 1)] is obtained in the 8-point radix-2 FFT pipeline (1).

FIG. 3 shows the input processing of the preceding stage of the embodiment of the present invention. In the figure, 37 is input data of 16 points,
Reference numerals 0 and 37-1 denote 8-point radix-2 FFT pipelines, respectively, and 37-0 inputs data of a point of kj = 0,
37-1 inputs the data of the point of kj = 1.

[X1 (nj, 0)] is obtained by [X1 (nj, 0)] by the 8-point radix-2 FFT pipeline 37-0 in the preceding stage.
(0,0), X1 (4,0)], [X1 (2,2)
0), X1 (6, 0)], [X1 (1, 0), X1
(5,0)], [X1 (3,0), X1 (7,
0)].

[X1 (nj, 1)] is converted to [X1 (nj, 1)] by the 8-point radix-2 FFT pipeline 37-1 in the preceding stage.
(0, 1), X1 (4, 1)], [X1 (2,
1), X1 (6, 1)], [X1 (1, 1), X1
(5,1)], [X1 (3,1), X1 (7,
1)]. By inputting the data of each of the above sets in the output of the preceding stage, the torsion coefficient multiplying unit can process Equation 4 above.

That is, the output result is input as it is in four parallels, and the output is obtained in the following order. [X2 (0,0), X2 (4,0), X2 (0,1),
X2 (4,1)] [X2 (2,0), X2 (6,0), X2 (2,1),
X2 (6, 1)] [X2 (1, 0), X2 (5, 0), X2 (1, 1),
X2 (5,1)] [X2 (3,0), X2 (7,0), X2 (3,1),
X2 (7,1)] The 4-parallel data of the above-mentioned torsion coefficient multiplying unit is input to the subsequent stage and output in the following order to obtain an operation result.

That is, in the two-point FFT circuit (a),
[X2 (0,0), X2 (0,1)], [X2
(2,0), X2 (2,1)], [X2 (1,
0), X2 (1, 1)], [X2 (3.0), (3,
1)] are sequentially input, and [X3 (0,0), X3
(0,1)], [X3 (2,0), X3 (2,2)
1)], [X3 (1,0), X3 (1,1)],
A set of [X3 (3,0), X3 (3,1)] is sequentially output.

In the two-point FFT circuit (b), [X2
(4,0), X2 (4,1)], [X2 (6,6)
0), X2 (6, 1)], [X2 (5, 0), X2
(5,1)] and [X2 (7,0), (7,1)] are input in order, and [X3 (4,0), X3 (4,1)], [X3 (6 , 0), X3 (6, 1)], [X3
(5, 0), X3 (5, 1)], [X3 (7, 0), X
3 (7, 1)] are sequentially output.

[0068]

According to the present invention, the degree of parallelism for performing Fourier transform can be flexibly determined according to the relationship between the number of FFT points and the required processing speed. Therefore, FF
In the Fourier transform with a large number of T points N, the degree of the square root of N is not required as the degree of parallelism, but it is possible to set a device configuration that is not wasted when processing data that cannot be handled by the degree of parallelism 2. become.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 shows an input process in a preceding part of the present invention.

FIG. 4 is a diagram showing a configuration of a conventional multipoint parallel FFT.

FIG. 5 is a diagram illustrating a butterfly circuit.

FIG. 6 is a flowchart (1) of a 16-point radix-2 FFT pipeline.

FIG. 7 is a flowchart (2) of a 16-point radix-2 FFT pipeline;

FIG. 8 is a flowchart (3) of a 16-point radix-2 FFT pipeline;

FIG. 9 is a flowchart (4) of a 16-point radix-2 FFT pipeline;

FIG. 10 is a diagram illustrating a configuration (1) of a radix-2 FFT pipeline.

FIG. 11 is a diagram illustrating a configuration (2) of a radix-2 FFT pipeline.

FIG. 12 is an explanatory diagram (1) of the operation of the radix-2 FFT pipeline.

FIG. 13 is an explanatory diagram (2) of the operation of the radix-2 FFT pipeline.

[Explanation of symbols]

Reference Signs List 1 input data 2 front part 3 multiplication part 4 rear part 5-0 to 5- (a-1) m-point radix 2 FFT pipeline 7 to 8 a-point FFT circuit 9 Final operation result.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-114675 (JP, A) JP-A-60-1444872 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/14 JICST file (JOIS)

Claims (3)

(57) [Claims] [Claim 1 further comprising a plurality of radix-2 Fourier transform pipeline with the same Fourier transform points, multiplied for multiplying a first part for inputting input data in parallel, the coefficients twist to each data output from the preceding stage in parallel And a parallel Fourier transform circuit having a number of Fourier transform points equal to the number of radix-2 Fourier transform pipelines in the preceding stage.
And a post-stage unit for inputting data output in parallel from the multiplication unit in parallel. 2. The discrete Fourier transform according to claim 1, wherein a function value of a k-th point of the N-point data is represented by x (k). (However, a Fourier transform device for n = 0 to N-1, k = 0 to N-1) is decomposed into N = m × a (m is a power of 2 and a is a positive integer of 2 or more ). possible time, the first part is provided with a number a number of 2 parallel input / 2 parallel output m point radix 2 Fourier transform pipeline,
The multiplication unit inputs the 2a converted data at N points in parallel and inputs 2a data in parallel, and multiplies the 2a data in parallel by the torsion coefficient. The subsequent stage is provided with two a-point parallel Fourier transform circuits of a-point parallel input / a-point parallel output in parallel, and outputs 2a data output in parallel from the multiplication unit in the m-point radix-2 Fourier transform source. Fourier transform device transform pipeline is inputted in parallel by a single in each so different a number respectively, and obtaining the final result by performing a Fourier transform. 3. The method according to claim 2, wherein n = m × ni + nj, k = a × ki + kj (where ni = 0 to (a−1), nj = 0 to (m−
1), ki = 0 to (m-1), kj = 0 to (a-1))
The Fourier transform equation to be transformed is expressed as And in the above equation: (Equation 4) (Equation 5) (However, W = exp (−2πj / N), W _m = exp
(−2πj / m), W _a = exp (−2πj / a)) In the preceding part, Performs the conversion process at a particular point m radix-2 Fourier transform pipeline which is corresponding to one-to-one to each value of kj, in the multiplication unit, Equation 7] Is provided with two multiplication means each corresponding to the kj value, and a specific m-point radix 2 of the preceding stage corresponding to the kj value is provided.
For data output Fourier transform pipeline or et two by two, performed in parallel, the rear stage, Equation 8] Is performed in parallel by two a-point parallel Fourier transform circuits as a separate set of a piece of data that is output in parallel from the multiplication unit for each kj value two by two. Fourier transform device.