JP3086570B2 - Video signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit, and more specifically, to a CCD (Charge Coupler) in a light receiving section.
The present invention relates to an improvement in a video signal processing circuit that processes a video signal, particularly a color signal, used in an imaging device such as a video camera (hereinafter, referred to as a CCD camera) using a led device.

[0002]

2. Description of the Related Art Recently, a CCD using an analog system has been developed.
The transition from a camera to a CCD camera using a digital system that is easy to adjust has been promoted. Hereinafter, a video signal processing circuit according to a conventional example will be described with reference to FIGS. FIG. 4 is a configuration diagram of a CCD camera using a general digital system.

As shown in FIG. 4, a general CCD camera includes a vertical driver (22), a horizontal driver (23), a synchronization signal timing generator (25), and an oscillator (hereinafter referred to as an OS).
The CCD (24) is driven by a drive block (19) consisting of (26), a correlated double sampling circuit (hereinafter referred to as CDS) (27), a color signal processing circuit (28), and a color difference matrix circuit. (2
9) and a synchronizing signal used in a video signal processing system including the encoder circuit (30) has been generated.

According to the apparatus, a video signal is output in response to a subject video illuminated on the CCD (24) via the lens (20) and the optical block (21). The video signal is preprocessed by the CDS (27) and output to the color signal processing circuit (28).
A video output signal is generated by performing predetermined processing sequentially by the color signal processing circuit (28), the color difference matrix circuit (29), and the encoder circuit (30).

A video signal processing circuit according to a conventional example is a partial circuit inside the above-mentioned color signal processing circuit (28), and obtains color data (Rd
1) is a circuit for multiplication processing for multiplying a gain for adjusting a white balance of an image. This circuit is provided one for each of the three colors of each color component [R, G, B] (or two colors of [R, B]). Only circuits of the [R] system will be described, and description of circuits corresponding to other colors will be omitted.

A video signal processing circuit according to a conventional example is shown in FIG.
As shown in the figure, the white balance control block (1), a 5-bit up / down counter (2), a multiplier (3) and a selector (4), and 6-bit color data ( Rd1), the color difference signal (R
-Y) is a circuit that performs multiplication processing on 6-bit gain data (GD) generated based on -Y) to calculate white balance data (WD) with white balance, and outputs the white balance data (WD) to the color difference matrix circuit.

The operation of the circuit is as follows. First, the counter control signal (UD1) generated by the white balance control block (1) based on the color difference signal (RY) output from the color difference matrix circuit (not shown) is 5 Output to the bit up / down counter (2). The counter control signal (UD1) is generated so that the integrated value of the color difference signal (RY) in one screen unit approaches a predetermined value. Next, the 5-bit up / down counter (2) is counted up / down by the counter control signal (UD1), and 1-bit "1" is added to the highest order of the count value [32-63]. The bit gain data (GD) [this corresponds to the gain to be applied to achieve white balance] is output to the multiplier (3), and at the same time, the 6-bit color data (Rd
1) is input. Next, the color data (Rd1) and the gain data (GD) are multiplied by the multiplier (3) to obtain 12-bit data. The 12-bit data is data multiplied by a gain for obtaining white balance, and is hereinafter referred to as balance gain data (WB1). The balance gain data (WB1) thus obtained is bit-shifted by 3 bits by the selector (4) to become 9-bit data. Shifting data by three bits is equivalent to dividing the data by eight. Therefore, the selector (4) performs a division process of dividing the balance gain data (WB1) by eight.

With the above operation, the arithmetic processing of 6-bit color data (Rd1) × 6-bit gain data (GD) / 8 is performed on the 6-bit color data (Rd1). If the multiplication process of 6-bit color data (Rd1) × 6-bit gain data (GD) is simply performed, the gain data (GD) becomes (0 to 0).
64) can be selected in the range up to 63).
At this time, the gain step [gain data (GD) is 1
A value indicating how much changes occur in steps] is 1.0. In general, however, such a high gain is not required in white balance, and thus the above-described circuit uses 6-bit color data (Rd1) and 6-bit gain data (Gd).
The data after the multiplication process with D) is divided by 8. This is equivalent to multiplying the gain of {6-bit gain data (GD) / 8} by the 6-bit color data (Rd1). Therefore, the gain data (G
D) is 1/8 of (0-63) (0, 0.125,
0.25, 0.375, ... 7.875)
The 64 kinds of data at intervals are selected. The gain step at this time is 7.875 / 63 = 0.12
5

[0009]

However, according to the conventional video signal processing circuit, the following problems occur. As an example, consider a case where the value of data indicating G [green] (hereinafter referred to as a G signal) is 100 and the value of data indicating R [red] (hereinafter referred to as an R signal) is 20 or 200.

Normally, when adjusting the white balance, a gain is applied so that the R signal matches the level of the G signal. Therefore, the gain is (5) when the (1) R signal is 20 and (2) when the R signal is 200, respectively. The two cases will be discussed below. In both cases (1) and (2), the gain step is constant at 0.125.

(1) When the R signal is 20 and the gain is × 5 [when the gain is large] Here, looking at the data after the multiplication process in the case where the gain is shifted by one step before and after, the following is obtained: 20 × (5 -0.125) = 97.5 20 x (5 + 0.125) = 102.5. The result after the multiplication process is 1 which is the value of the G signal.
The value is almost close to 00, and there is no problem in white balance.

(2) When the R signal is 200 and the gain is × 0.5 [when the gain is small] Looking at the case where the gain is shifted by one step each before and after, 200 × (0.5−0.125) = 75 200 × (0.5 + 0.125) = 125. The result after the multiplication process is 1 which is the value of the G signal.
It is quite far from 00, and it is hard to say that white balance is achieved. Therefore, it can be said that when the gain is small, it is difficult to adjust the gain to an appropriate value.

On the other hand, when the white balance is automatically controlled by a feedback system as in the above-described conventional circuit, when the gain of (2) is small, the gain is set to 0.
Since the gain step is 0.125 and the gain change rate is relatively large at 5, the gain becomes 0.5 with a small number of steps, and the R signal becomes equal to 100 which is the value of the G signal. On the other hand, when the gain of (1) is large, the gain change rate is relatively small because the gain is 5 and the gain step is 0.125, and the gain becomes 5 and the R signal becomes the G signal. It takes many steps to reach the value of 100. Therefore, when the gain is large, the gain step becomes relatively fine, and it takes much time until the white balance is in an appropriate state.

That is, according to the above-mentioned conventional circuit, the gain step is kept constant regardless of the gain value. Therefore, when the gain is small, it becomes difficult to adjust the white balance to an appropriate value. When the gain is large, the gain step becomes relatively small, so that the time required for obtaining an appropriate white balance becomes long, and there has been a problem that it is not possible to respond quickly.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and as shown in FIG. 1, a white balance gain (WG) based on a color difference signal (C-Y).
And the second gain data (GD2) by multiplying the first gain data (GD1), which is the lower bit of the white balance gain (WG), by the color data (C). The second gain data (GD2) is divided based on a multiplication means (12) and a division control signal (SS), which is a higher-order bit of the white balance gain (WG), to obtain white balance data (W
A video signal processing circuit comprising: a dividing means (13) for generating D), whereby the white balance can be easily adjusted and the white balance can be quickly obtained when the adjustment is performed by a feedback system circuit. Is provided.

[0016]

The video signal processing circuit according to the present invention includes, as shown in FIG. 1, a gain generating means (11), a multiplying means (12), and a dividing means (13). For example, the color difference signal (C-
Y), a white balance gain (WG) is generated, and first gain data (GD1), which is the lower bit of the white balance gain (WG), is multiplied by the multiplication means (12).
And a division control signal (SS), which is the upper bit of the white balance gain (WG),
3), the first gain data (GD1) is multiplied by the color data (Cd) by the multiplication means (12) to generate second gain data (GD2), and the division means (13) The second gain data (GD2) is subjected to division processing based on the division processing control signal (SS) to generate white balance data (WD). For this reason, when the white balance gain (WG) is large based on the division processing control signal (SS), the gain step, which is the width value for changing the white balance gain (WG) for each field, is increased, and the white balance gain (WG) Is smaller, the gain step can be made smaller. Accordingly, when the white balance gain (WG) is large, by increasing the gain step, the time until the white balance is obtained can be shortened, so that it is possible to respond quickly, and when the white balance gain (WG) is small, the gain step is reduced. By making the size smaller, the white balance can be easily adjusted.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a video signal processing circuit according to an embodiment of the present invention will be described with reference to the drawings. The video signal processing circuit according to the embodiment of the present invention is a partial circuit of the above-described color signal processing circuit, and as shown in FIG. 2, color data (Rd1) obtained from the output of a CDS (not shown).
And a multiplication process for applying a gain for obtaining a white balance. Note that this circuit is provided for each of the three colors of each color component [R, G, B], but the configuration and function are almost the same.
Only the circuit of red [R] will be described, and description of the other colors will be omitted.

The video signal processing circuit according to the present embodiment has the configuration shown in FIG.
As shown in the figure, a gain generation circuit (11) and a multiplier (12)
And a division circuit (13), wherein a red [R]
Is multiplied by 6-bit color data (R) corresponding to the color No. of color and white balance gain data (WG) of 6 bits generated based on the color difference signal (R-Y), and then divided to obtain white data. This is a circuit that calculates balanced white balance data (WD) and outputs it to a color difference matrix circuit (not shown).

The gain generating circuit (11) is an embodiment of a gain generating means, and includes a white balance control block (11A) and a 7-bit up / down counter (1).
1B). The white balance control block (11A) includes an integration circuit and the like, generates a counter control signal (UD) that is 1-bit data based on a 6-bit color difference signal (RY), and generates a 7-bit up / down counter. (11B). In addition,
The above-mentioned counter control signal (UD) is generated so that the integrated value per one screen of the color difference signal (RY) generated by the integration circuit approaches a predetermined value. Further, since the color difference signal (RY) is generated by a color difference matrix circuit (not shown) which is an output destination of the circuit,
This means that a feedback circuit is formed along the path of the circuit, the color difference matrix circuit, and the circuit. 7
The bit-up / down counter (11B) generates 7-bit white gain data (WG) by counting the counter control signal (UD), and divides the upper two bits into the selector control block (1) of the division circuit (13).
3A) and the lower 5 bits to the multiplier (12). The multiplier (12) is an embodiment of a multiplying means, and adds 6 bits of color data (R) and 5 least significant bits of white gain data (WG) to the most significant bit “1”. It outputs balance gain data (WB) multiplied by the bit data to the selector (13B).

The division circuit (13) is an embodiment of the division means and comprises a selector control block (13A) and a selector (13B), and is based on the upper 2 bits of the 7-bit white gain data (WG). The division processing is performed on the balance gain data (WB). The selector control block (13A) is a decoder circuit and outputs an internal control signal (IS) that determines the degree of bit shift by the selector (13B) based on the upper two bits of the white gain data (WG).
B). The selector (13B) shifts the balance gain data (WB) by several bits based on the internal control signal (IS), calculates white balance data (WB) with white balance, and calculates a color difference (not shown). This is a circuit that outputs to a matrix circuit.

First, the operation of the circuit is based on a white balance control block (11A) based on a color difference signal (RY) output from a color difference matrix circuit (not shown).
Is output to the 7-bit up / down counter (11B). Next, the counter control signal (UD) of the 7-bit up / down counter (11B) is generated by the counter control signal (UD).
D) is counted to generate 7-bit white gain data (WG), the upper 2 bits of which are output to the selector control block (13A) and the lower 5 bits are output.
The bits are output to a multiplier (12). Next, 6-bit data [hereinafter referred to as gain data (BG)] having a range of [32 to 63], which is data in which the most significant bit of “1” is added to the lower 5 bits of white gain data (WG) , And 6-bit color data (R1) obtained from the output of a CDS (not shown) is multiplied to obtain 12-bit data. The 12-bit data is multiplied by a gain for adjusting the white balance, and is hereinafter referred to as balance gain data (WB).

On the other hand, the selector control block (1
3A), the upper 2 bits of the white gain data (WG) are input, and based on the value of the upper 2 bits, an internal control signal (IS) for determining the number of bits of the bit shift by the selector (13B) is selected. (13B). Next, the balance gain data (WB) is bit-shifted by several bits by the selector (13B) based on the internal control signal (IS), and is output as white balance data (WD) to a color difference matrix circuit (not shown). This selector control block (13A)
And a series of operations of the selector (13B) will be described in detail with reference to Table 1 below. Table 1 is a table showing the relationship between the upper two bits of the white gain data (WG) and the bit number of the bit shift of the balance gain data (WB) corresponding to the value.

[0023]

[Table 1]

Selector control block (13A)
Outputs, to the selector (13B), an internal control signal (IS) that determines the number of bits for shifting the balance gain data (WB) based on the upper two bits of the white gain data (WG). As shown in Table 1 above, for example, if the upper 2 bits of the white gain data (WG) are “10”, “4”
The internal control signal (IS) having the content "bit shift by bits" is output to the selector (13B), and based on this, the balance gain data (WB) is bit-shifted to the lower side by 4 bits. If the upper two bits of the white gain data (WG) are “00”,
The internal control signal (IS) having the content "bit shift by 6 bits" is output to the selector (13B), and based on this, the balance gain data (WB) is bit shifted downward by 6 bits. .

As shown in Table 1, shifting the bit of the balance gain data (WB) by 4 bits has the same value as performing the division process of dividing the balance gain data (WB) by 16. In addition, shifting the balance gain data (WB) by 6 bits is equivalent to performing the division process of dividing the balance gain data (WB) by 64. Hereinafter, the number of divisions of the balance gain data (WB) is referred to as a division number (n).

The white gain data (WG) whose upper two bits are "00" is naturally smaller than the white gain data (WG) whose upper two bits are "10". In the circuit of this embodiment, when the high-order 2 bits are white gain data (WG) having a small value of “00”, the balance gain data (WB) is divided by 64, and the high-order 2 bits are set to a large value of “10”. Certain white gain data (W
In the case of G), since the balance gain data (WB) is divided by 16, even if this example alone is compared, when the white gain data (WG) is small, the divisor (n) is increased and the balance gain data (WB) is increased. , And when the white gain data (WG) is large, the divisor (n) is reduced to perform the division process of dividing the balance gain data (WB). " This fact is more apparent with reference to Table 1. By the above operation, 6-bit color data (R) × 6-bit gain data (BG) /
The divisor (n) operation is performed. This is equivalent to multiplying the gain of {6-bit gain data (BG) / divisor (n)} by the 6-bit color data (R). Therefore, the gain data (GD) is 1 / n of (0 to 63) (0, 1 /
n / 2 / n, 3 / n,... 63 / n)
Four types of data are selected, and the gain step at this time is [1 / n], which is the reciprocal of the divisor (n).

As described above, the divisor (n) is small when the white gain data (WG) is large, and the divisor (n) is large when the white gain data (WG) is small. (N)
It can be understood that the gain step having the reciprocal of is performed such that the gain step is large when the white gain data (WG) is large and the gain step is small when the white gain data (WG) is small. .

As described above, according to the video signal processing circuit of the present embodiment, the white balance gain (WG)
When the white balance gain (WG) is small, it is possible to reduce the time required for obtaining the white balance and quickly respond to the white balance gain (WG). It becomes easy to adjust the white balance.

Further, according to the circuit of this embodiment, when the white balance gain (WG) is large, the gain step for changing the white balance gain is increased, and when the white balance gain (WG) is small, the gain step is decreased. However, by taking such a white balance gain (WG), the following operational effects are also produced. FIG. 3 is a graph for explaining the secondary operation and effect. The horizontal axis indicates the output value of the 7-bit up / down counter (11B) according to the present embodiment.
7 indicates white gain data (WG) having a range up to 7, and the vertical axis indicates a value obtained by calculating suppression reference data (Glim), which is a constant value set for suppressing highlight green, based on the data. Is shown.

The suppression reference data (Glim) is data devised by the inventor of the present invention.
Glim = SL × {Rg / (Rg + 1)}, which is a reference value for removing a color component in order to suppress a highlight green phenomenon in which the screen changes to green with an increase in luminance. It is a value obtained by the following equation. In the above equation, Rg is white gain data (WG) for obtaining a white balance corresponding to red, and SL is a saturation value of the output level of the CCD.

In FIG. 3, a curve represented by represents white balance data (W
D) and the suppression reference data (G
lim). Note that the output value of the multiplier (3), which is the output value of FIG. 5, is 1/8 times the balance gain data (WB1) that is the result of multiplication of the color data (Rd1) and the gain data (GD). In the same manner, the balance gain data (WB
1) corresponds to white gain data (WG) obtained as a result of multiplying by 1/16, 1/32 and 1/64, respectively.

Further, the relationship between the white gain data (WG), which is the output value of the 7-bit up / down counter (11B), and the suppression reference data (Glim) obtained on the basis of the output value of the circuit of this embodiment. FIG. As shown in FIG. 3, this curve is close to a linear approximation in the range of white gain data (WG) [0 to 31], [32 to 63], and [63 to 95]. ing. From the graph in FIG. 3, it can be seen that the data up to [32-63] of the curves up to apply. That is, [32-
63], the curve corresponding to the data [0]
To 31], corresponding to the data curves from [32 to 6].
Curves corresponding to data up to 3] are [32 to 63].
The curves corresponding to the data up to [32-63] correspond to the graphs up to [64-95] of the curve, and the curves corresponding to the data up to [32-64]. The curve corresponding to the curve is [96-1]
27]. Therefore, according to the circuit of FIG. 5 described in the conventional example, a complex such as a divider necessary for obtaining the suppression reference data (Glim) from Rg is obtained by the following equation: Glim = SL × {Rg / (Rg + 1)} Although it was necessary to adopt a circuit configuration, according to the circuit of the present embodiment, the circuit shown in FIG.
By using the white gain data (WG) which is the output value of the bit up / down counter (11B), it is possible to easily obtain the suppression reference data (Glim) with an approximate straight line, and the circuit configuration is simplified. It can be seen that the following effects occur.

In this embodiment, the color difference signal (R-
(Y) is an example of the color difference signal (C-Y), and the color data (R) is an example of the color data (C). The gain data (BG) is an example of first gain data (GD1), and the balance gain data (WB) is an example of second gain data (GD2). The upper two bits of the white gain data (WG) are divided by the division control signal (S
S) is an example.

In this embodiment, 6-bit gain data (BG) is obtained by using 6-bit color data (R).
However, the present invention is not limited to this. For example, 8-bit data may be used for each. Also,
The bit shift at the time of the division process is also performed with 3 to 6 bits, but the present invention is not limited to this.

[0035]

As described above, according to the video signal processing circuit of the present invention, the white balance gain (W
When G) is large, the time until white balance can be reduced by increasing the gain step, and when the white balance gain (WG) is small, the gain step is reduced, so that the white balance can be adjusted to an appropriate value. Is easier to adjust.

[Brief description of the drawings]

FIG. 1 is a principle diagram of a video signal processing circuit according to the present invention.

FIG. 2 is a circuit diagram of a video signal processing circuit according to an embodiment of the present invention.

FIG. 3 is a graph illustrating the operation and effect of the video signal processing circuit according to the embodiment of the present invention.

FIG. 4 is a configuration diagram of a general CCD camera.

FIG. 5 is a circuit diagram of a video signal processing circuit according to a conventional example.

[Explanation of symbols]

 (11) Gain generation circuit [Gain generation means] (11A) White balance control block (11B) 7-bit up / down counter (12) Multiplier [Multiplication means] (13) Divider circuit [Division means] (13A) Selector control block (13B) Selector

Claims (1)

(57) [Claims] 1. A gain generation means for generating a white balance gain (WG) of an appropriate number of bits for multiplying each color component of a quantized video signal to adjust a mutual balance of each color component.
(11) and several lower bits of the white balance gain (WG) are taken in as first gain data (GD1), and the first gain data (GD1) is multiplied by the color data (C) to obtain a second gain data. Multiplication means (12) for obtaining the gain data (GD2) of the white balance gain (WG)
Dividing means for obtaining the white balance data (WD) by dividing the second gain data (GD2) based on the division processing control signal (SS), and (13), the provided
And the dividing means (13) is provided with the white balance gay.
When the weight (WG) is large, the second
The divisor for the gain data (GD2) of
When the white balance gain (WG) is small,
A video signal processing circuit characterized by increasing a divisor.