JP3085843B2 - Semiconductor memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as a dynamic random access memory (hereinafter referred to as a DRAM), and more particularly to a semiconductor integrated circuit having a storage means at an output node of a sense amplifier.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit having a sense amplifier cache hit operation has been proposed to enable high-speed reading. This sense amplifier cache hit operation is performed when the same row address as in the previous cycle is input and the same word line is selected. At this time, the sense amplifier is kept active while the bit line pair is connected to the output node of the sense amplifier, and the previous amplification result is stored in the sense amplifier row. As a result, the information of the bit line pair selected based on the column address is transferred to the data line at high speed without waiting for the timing when the word line rises again and the reading and amplification operations are completed.

[0003]

However, since only the information of the memory cell corresponding to one word line can be stored in the sense amplifier, the probability that a cache hit operation for reading information at high speed is performed is low. There was a problem. Furthermore, if a refresh operation unique to the DRAM required to hold the information of the memory cell is performed, the information of the memory cell cannot be stored in the sense amplifier, and the probability of the cache hit operation is further reduced.

[0004]

In order to solve the above-mentioned problems, a semiconductor memory circuit according to the present invention outputs a selection signal, a switch control signal, a storage element control signal, and a sense amplifier activation signal in response to a row address signal. Row address storage circuit, a row decoder for selecting a word line in response to a selection signal, a memory cell array having a plurality of memory cells, and a sense amplifier having a plurality of sense amplifiers operating in response to a sense amplifier activation signal Switch means provided between the column and one set of bit lines and one set of sense lines for connecting them in response to a switch control signal; and a first terminal connected to at least one of the set of sense lines. Storage element switch means connected to the storage element and performing on / off operation in response to a storage element control signal and a refresh cycle detection signal; Is connected to the second terminal of the slave switch means, it provided a memory element for storing the potential appearing on the sense line.

[0005]

After the storage element stores the potential appearing on the sense line, it is disconnected from the sense line by the storage element switch means, so that the sense amplifier reads out and amplifies the amplified information in the next cycle, for example, the previous cycle in the refresh cycle. I remember.

[0006]

FIG. 1 is a block diagram showing a DRAM according to a first embodiment of the present invention. Hereinafter, the configuration of the first embodiment will be described with reference to FIG. An external address ADD composed of a row address and a column address is input to an address multiplexer 103 via an address buffer 101. The output of the address multiplexer 103 based on the row address is input to the row address storage circuit 105. The row address decoder 107 selects a word line (for example, WL1, WL2) of the memory array 109 based on the output of the row address storage circuit 105. A memory cell 111 for storing information is provided at an intersection of a word line and a bit line (for example, BL and bar BL). Note that the memory array 109 has word lines, bit lines, and memory cells other than those shown in FIG. 1, but these are omitted for simplification of description.

When a word line is selected by the row decoder 107, the memory cell 111 is selected and read out to the bit line pair BL and / BL. In response to a signal output from the row address storage circuit 105 to the first signal output line 133, the switch SW1
Is turned on. At this time, the data read to the bit line pair BL and bar BL (bit line BL and bar B
(Potential on L) is transferred to the sense line pair S and bar S. The sense amplifier 119 connected to the sense line pair S and the bar S of the sense amplifier row 117 including a plurality of sense amplifiers outputs the sense amplifier activation signal SAE (output from the row address storage circuit 105 to the first signal output line 133). The timing of the sense amplifier activation signal SAE is slightly behind the signal for controlling the switch SW1 described above, and therefore, although not shown in Fig. 1, several stages of gates are provided on the first signal output line 133. Activated by
The potential on the sense line pair S and the bar S is amplified.

On the other hand, the output of the address multiplexer 103 based on the column address is sent to the column decoder 121. The column decoder 121 outputs the selection signal CLS, and the selected bit line pair D and / D receives the output (amplified information) of the sense amplifier 119.
When the row address is latched from the external address to the internal latch circuit via the address buffer 101, the address multiplexer 103 does not need to input the row address from outside. Also, at the start of the memory operation, it is not necessary to input a column address. Therefore, the number of external terminals is halved by shifting the timing of the row address and the column address from the same external terminal. The row address storage circuit 105 has a function of latching a previously input row address signal in a continuously input row address and comparing the latched row address signal with a subsequently input row address.

The bit line pair BL and / BL are equalized to an intermediate level HVCC between the power supply voltage and the ground level by the equalizing signal EQB. The sense line pair is also equalized to the intermediate level HVCC by a signal SAE obtained by inverting the sense amplifier activation signal SAE output from the row address storage circuit 105 by the inverter 123. In the first embodiment, as a characteristic configuration, the shadow cache unit 115 is connected to at least one of the sense line pair S and the bar S. The shadow cache means 115 includes a shadow cache SC1 and a shadow switch SSW1. The shadow cache SC1 stores data on the sense line pair S and the bar S.

FIG. 2 is a circuit diagram showing an example of the shadow cache means 115. In this example, the shadow cache means includes an NMOS transistor N1 as a shadow switch having one electrode connected to one of the sense line pair S and bar S, and a capacitor C1 connected to the other electrode of the NMOS transistor N1. It is configured. The shadow cache control signal SSW1 is applied to the gate of the NMOS transistor N1, and the capacitor C1
, Which is not connected to the NMOS transistor N1, is supplied with a potential 1/2 VCC which is half of the power supply potential. In the case of a shadow cache composed of one transistor and one storage capacitor as shown in FIG. 2, it is better to provide a transistor having a larger size and a larger storage capacitor than the transistors of the memory cells included in the memory array.

FIG. 3 is a circuit diagram showing another example of the shadow cache means 115. In this example, in the shadow cache means, a capacitor C2 is connected between a pair of sense lines S and S via NMOS transistors N2 and N3 as shadow switches. The shadow cache control signal SSW1 is commonly applied to the gates of the NMOS transistors N2 and N3. Since the shadow cache shown in FIG. 3 is composed of two transistors and one storage capacitor, the voltage for reading information is higher than the memory cells included in the memory array, and the reading operation time is shorter.

Next, the shadow cache control signal SSW1
Will be described. The signal output from the row address storage circuit 105 to the second signal output line 131 and the signal obtained by inverting the refresh cycle detection signal REF by the inverter 125 are input to the NAND gate 127. NAN
The output of D gate 127 is inverted by inverter 129 and sent to shadow switch SSW1 as shadow cache control signal SSW1.

FIG. 6 shows a DRAM according to a first embodiment of the present invention.
It is a time chart. Hereinafter, the operation of the DRAM of the first embodiment will be described with reference to FIGS. First, a sense amplifier cache load cycle in which information is read into the sense amplifier is performed. A word is selected based on the row address RA0, and the word line WL0 included in the memory array is driven. Then, the bit line pair BL and bar BL are connected to the sense amplifier 119 by the switch SW1. Thereafter, the sense amplifier 119 is activated by the sense amplifier activation signal SAE, and the potential difference appearing on the pair of bit lines BL and / BL is amplified.
Then, the column addresses CA00, CA01, CA02
D of bit line pair BL and bar BL selected based on
00, D01 and D02 are transferred to the data line pair D and bar D for external output. At this time, the shadow cache control signal SSW1 is always at the L level.

Subsequently, when the same row address RA0 is input, a sense amplifier cache hit cycle is entered.
The same word line WL0 is maintained at the H level, and the bit line pair BL, / BL and the sense lines S, / S are output by the output signal to the first output signal line 133 of the row address storage circuit 105.
While the row address storage circuit 105 is in the connected state.
, The sense amplifier activation signal SAE, which is an output signal to the first output signal line 133, is held at the H level, and the previous amplification result is stored in the sense amplifier 119 of the sense amplifier array 117. Then, the information D03, D04, and D0 of the bit line pair selected based on the column addresses CA03, CA04, and CA05 are provided without waiting for the timing at which the word line WL1 is read out again and the amplification operation is completed.
5 is transferred to the data line pair D and D at high speed. In addition,
Even in this cycle, the shadow cache control signal S
SW1 is always at the L level.

The operation of a sense amplifier cache miss cycle having a sense amplifier cache miss shadow cache hit cycle and a sense amplifier cache miss shadow cache miss cycle will now be described. When a row address RA1 different from the row address RA0 in the sense amplifier cache hit cycle is input, a sense amplifier cache miss cycle starts. Here, it is assumed that the information of the memory cell corresponding to the word line WL1 based on the row address RA1 is held in the shadow cache SC1. This state is called a sense amplifier cache miss shadow cache hit cycle, and its operation will be described below. Row address storage circuit 105
The switch SW1 is turned off by the output signal to the first output signal line 133, and the bit line pair BL, / BL and the sense lines S, / S are disconnected. Further, the inverted sense amplifier activating signal / SAE, which is an output signal to the first output signal line 133 of the row address storage circuit 105,
To the H level, the sense line pair S and bar S are set to the intermediate level H.
Equalize to VCC.

Thereafter, the shadow switch SSW1 is turned on (shadow cache control signal SSW1 is set to H level).
Level) and the sense amplifier activation signal SAE
Is set to the H level again, and the information held in the shadow cache SC1 is read out to the sense line pair S and the bar S. In other words, the rise of the word line WL0 having a large wiring load, the precharge time for equalizing the bit line pair BL and the bar BL, and the subsequent rise of the word line WL1 and waiting for the timing at which the reading and amplification operations are completed. Without the column address CA10. . .
Of the bit line pair selected based on the data D10. . . To the data line pair D and bar D.

After reading the information held in the shadow cache SC1, that is, after the completion of the amplification operation of the sense amplifier, the switch SW1 is turned on at a predetermined timing (the first output of the row address storage circuit 105). The output signal SW1 to the signal line 133 is set to H level), and the information held in the shadow cache SC1 stored in the sense amplifier is written to the memory cell corresponding to the word line WL1. This operation allows external DRAM
Is written to the shadow cache SC
1 and the information of the memory cell corresponding to the word line WL1 are both updated. After that, the shadow cache control signal SSW1 is set to L level, and the information of the shadow cache SC1 is held as it is.

Following the row address RA1 in the sense amplifier cache miss shadow cache hit cycle,
When a different row address RA2 is input, a sense amplifier cache miss enters a shadow cache miss cycle. The operation of this sense amplifier cache miss shadow cache miss cycle will be described below. When the row address RA2 is input, the shadow cache SC1
Does not hold the information of the memory cell corresponding to the word line WL2, the word line WL1 falls,
After waiting for the precharge time for equalizing the bit line pair BL and the bar BL, and the subsequent timing of raising the word line WL2 (to H level), reading, and completing the amplification operation, the column address CA20,
Bit line pair B selected based on CA21 and CA22
The information D20, D21 and D22 of L and bar BL are transferred to the data line pair D and bar D. At this time, since the shadow cache control signal SSW1 is at the H level, the information held in the shadow cache SC1 is rewritten with the information of the memory cell corresponding to the word line WL2.
That is, the information held in the shadow cache SC1 is rewritten in the sense amplifier cache miss shadow cache miss cycle.

Thereafter, the refresh address RAr
When 0 is input, a refresh cycle starts, all the word lines are deselected, and the equalize signal EQB goes to H level, and the bit line pair BL, / BL
Are equalized to the intermediate level HVCC. The output signal SW1 of the row address storage circuit 105 to the first output signal line 133 and the shadow cache control signal SS
Since both W1 are at L level, the shadow cache S
The information held in C1 is held as it is, and the sense line pair S and bar S are also equalized to the intermediate level HVCC.

Note that the sense amplifier may operate due to the refresh operation unique to the DRAM. Also at this time, the refresh cycle detection signal REF is input to the inverter 125, and the shadow cache control signal SSW
Since 1 becomes L level, the shadow cache S
The information held in C1 is held as it is.

As described above, the DRA of the first embodiment
According to M, since a shadow cache is connected to a bit line via a switch, it is possible to store information of memory cells corresponding to a plurality of word lines. Further, even in the cache miss operation, the precharge time and the time of waiting for the completion of the read amplification operation for the word line and the bit line pair having a large wiring load can be reduced, so that high speed can be achieved. Further, since the switch is turned off at the time of the refresh operation, it is possible to store information of the memory cells corresponding to a plurality of word lines, and even if the sense amplifier is operated for the refresh operation, Information can be stored in the shadow cache.

FIG. 4 shows a DRAM according to a second embodiment of the present invention.
FIG. It should be noted that in FIG.
The same parts as those in the figure are denoted by the same reference numerals, and the description thereof is omitted. In the DRAM of the second embodiment, in addition to the shadow cache SC1 of the first embodiment (shown as a second shadow cache SC3 in FIG. 2), a shadow cache SC2 (the first shadow cache SC2 in FIG. 2). Is shown). The first shadow cache SC2 is a first shadow switch SSW2.
Is connected to at least one of the data line pair S and the bar S via The first shadow switch SSW2 is on / off controlled by a first shadow cache control signal SSW2. First shadow cache control signal SSW2
The switch control signal SW1 for controlling the switch SW1 of the switch means 113 and the inverted refresh signal obtained by inverting the refresh cycle detection signal REF by the inverter 125 are input to the NAND gate 227, and the N
The output of the AND gate 227 is a signal inverted by the inverter 229.

The row address storage circuit 20 shown in FIG.
5, the NAND gate 237, the inverter 239, the second shadow cache SC3, and the second shadow switch SSW2 are respectively connected to the row address storage circuit 10 of FIG.
5, the operation is the same as that of the NAND gate 127, the inverter 129, the shadow cache SC1, and the shadow switch SSW1, and the description thereof is omitted.

FIG. 7 shows a DRAM according to a second embodiment of the present invention.
It is a time chart. Hereinafter, the operation of the DRAM of the second embodiment will be described with reference to FIGS. First, in the sense amplifier cache load cycle and the sense amplifier cache hit cycle, the information D00 to D05 amplified by the sense amplifier are transferred to the data line pair D and / D as in the first embodiment. At this time, since the first shadow cache control signal SSW2 is at the H level (the first shadow switch SSW2 is in the ON state), the information D00 to D05 amplified by the sense amplifier in the first shadow cache SC2. Is held. This information D00 to D05 corresponds to the DRA of the first embodiment.
In M, after the data is transferred to the data line pair D and / D, if the sense amplifier activation signal SAE goes to L level, the data line pair S and / S are equalized and disappear. However, in the DRAM of the second embodiment, the amplification information D00 to D05 of the sense amplifier can be saved in the first shadow cache SC2 in advance.

Similarly, in the sense amplifier cache miss shadow cache miss cycle, the word line WL
(2) Waiting for the timing of completion of the read-out and amplification operations (starting up at H level again), and then information D20, D21, D22 of the bit line pair BL and bar BL selected based on the column addresses CA20, CA21, CA22. Is transferred to the data line pair D and bar D. At this time, since the first shadow cache control signal SSW2 is at the H level (the first shadow switch SSW2 is on), the information D20 and D21 amplified by the sense amplifier in the first shadow cache SC2. , D22 are held. Further, even if the refresh cycle is entered, the amplification information of the sense amplifier immediately before the refresh cycle indicates that the first shadow cache control signal SSW2 becomes L level by the refresh cycle detection signal REF.
Is retained in the shadow cache SC2.

As described above, in the DRAM of the second embodiment,
In addition to the effects of the DRAM of the first embodiment, the amplification information of the sense amplifier, which disappears when the sense amplifier activation signal SAE goes low, is saved (saved) in the shadow cache.
It is possible to do.

FIG. 5 shows a DRAM according to a third embodiment of the present invention.
FIG. In the DRAM of the third embodiment, memory cells capable of storing information are composed of first and second memory arrays 511 and 527 connected to a word line and a bit line pair. Information can be written to or read from the memory cells by selecting a word line based on a row address and selecting a bit line pair based on a column address.

A sense amplifier array 519 including a plurality of sense amplifiers 521 is arranged between the first memory array 511 and the second memory array 527. Each sense amplifier 5
Reference numeral 21 has a function of amplifying the potential difference between the bit line pair BL1, the bar BL1 or BL2, and the bar BL2 generated by the accumulated information due to the charge of the memory cell 513.

Between the first memory array 511 and the sense amplifier array 519, a first switch means SW1 for connecting both is arranged. Similarly, between the second memory array 527 and the sense amplifier array 519, a second switch means SW2 for connecting both is arranged. The bit line pair BL1, bars BL1 and BL2, and bar BL2 included in the first memory array 511 and the second memory array 527 are connected to the first and second switch means SW, respectively.
1, connected to and shared by a single sense amplifier 521 via SW2. The bit line pair BL1 and bar BL1 are equalized to the intermediate potential HVCC by the first equalizing signal EQB1, and the bit line pair BL2 and bar B
L2 is set to the intermediate potential HV by the second equalizing signal EQB2.
Equalized to CC.

The first and second shadow caches SC1 and SC2 are arranged between the sense amplifier 521 and the first switch means SW1, and the first and second shadow caches SC1 and SC2 are connected to the first shadow cache SC1 and the sense line. Shadow switch SSW1 and second shadow cache SC
2nd shadow switch SS which connects 2 and the sense line
W2. Similarly, third and fourth shadow caches SC3 and SC4 are arranged between the sense amplifier 521 and the second switch means SW2, and a third shadow switch connecting the third shadow cache SC3 and the sense line is provided. SSW3 and a fourth shadow switch SSW4 for connecting the fourth shadow cache SC4 to the sense line.

Each of the shadow caches SC1 to SC4 has
The first to fourth row address storage circuits 505, 5
09, 531 and 529. Further, the first to fourth row address storage circuits 505, 509, 53
1 and 529 have a function of holding the row address of the held data and comparing the row address with a subsequently input row address signal.

Since the operation of the third embodiment of the present invention is the same as that of the second embodiment, a detailed description thereof will be omitted. By employing the configuration of the third embodiment, the plurality of shadow caches SC1 to SC4 can store the word lines WL11, WL12 (or WL21, WL2) included in the first memory array 511 (or the second memory array 527).
Holding only the information of the memory cell corresponding to 2) may be achieved by changing the word lines WL11, WL12, WL21, WL2 included in the first and second memory arrays 511, 527.
It is also possible to hold all the information of the memory cells corresponding to No. 2 and the degree of freedom of the range of the memory cells that the shadow cache can handle can be increased. Furthermore, since one sense amplifier is arranged for two memory arrays,
The area occupied by the sense amplifier in the DRAM is small.

[0033]

As explained above, according to the present invention,
Since the shadow cache is connected to the bit lines via the switches, it is possible to store information of memory cells corresponding to a plurality of word lines. Further, even in the cache miss operation, it is possible to reduce the number of times of waiting for the completion of the read amplification operation for the word line and the bit line pair having a large wiring load, thereby achieving high speed. Further, since the switch is turned off at the time of the refresh operation, it is possible to store information of the memory cells corresponding to a plurality of word lines, and even if the sense amplifier is operated for the refresh operation, Information can be stored in the shadow cache.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a DRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a shadow cache unit according to the first embodiment;

FIG. 3 is a circuit diagram showing another example of the shadow cache unit of the first embodiment.

FIG. 4 is a block diagram showing a DRAM according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing a DRAM according to a third embodiment of the present invention.

FIG. 6 is a time chart showing the operation of the DRAM of the first embodiment.

FIG. 7 is a time chart illustrating the operation of the DRAM of the second embodiment.

[Explanation of symbols]

105, 205, 505, 509, 531, 533
Row address storage circuit 107, 509, 529 Row decoder 109, 511, 527 Memory array BL, bar BL, BL1, bar BL1, BL2, bar B
L2 Bit line SW1, SW2 Switch means SC1 to SC6 Shadow cache SSW1 to SSW6 Shadow switch means 119, 521 Sense amplifier D, bar D Data line pair

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-1-159891 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/40-11/409

Claims (12)

(57) [Claims] A selection signal responsive to a row address signal;
A row address storage circuit that outputs a switch control signal, a storage element control signal, and a sense amplifier activation signal; a row decoder that selects a word line in response to the selection signal; and a memory at an intersection of the word line and the bit line A memory cell array having cells; a sense amplifier array having a plurality of sense amplifiers for amplifying a potential difference between a set of sense lines in response to the sense amplifier activation signal; a set of the bit lines and a set of sense lines Switch means for connecting one set of the bit lines and one set of sense lines in response to the switch control signal; and a first terminal connected to at least one of the set of sense lines. A storage element switch means connected and turned on / off in response to the storage element control signal and the refresh cycle detection signal; Is connected to the second terminal of the switch means,
A storage element for storing a potential appearing on the sense line. 2. The semiconductor memory circuit according to claim 1, wherein said memory element is a capacitor. 3. The semiconductor device according to claim 2, wherein a first terminal of said capacitance means is connected to said storage element switch means, and a second terminal of said capacitance means is connected to a predetermined potential source. Storage circuit. 4. A first terminal of said capacitance means is connected to said storage element switch means, and a second terminal of said capacitance means is connected to the other of said set of sense lines via another storage element switch means. 3. The semiconductor memory circuit according to claim 2, wherein the semiconductor memory circuit is connected. 5. A selection signal in response to a row address signal,
A row address storage circuit that outputs a switch control signal, a storage element control signal, and a sense amplifier activation signal; a row decoder that selects a word line in response to the selection signal; and a memory at an intersection of the word line and the bit line A memory cell array having cells; a sense amplifier array having a plurality of sense amplifiers for amplifying a potential difference between a set of sense lines in response to the sense amplifier activation signal; a set of the bit lines and a set of sense lines Switch means for connecting one set of the bit lines and one set of sense lines in response to the switch control signal; and a first terminal connected to at least one of the set of sense lines. A first storage element switch means connected and turned on / off in response to the storage element control signal and the refresh cycle detection signal; A first storage element connected to a second terminal of the storage element switch means for storing a potential appearing on the sense line, and a first terminal connected to at least one of the set of sense lines; A second storage element switch which is turned on / off in response to the control signal and the refresh cycle detection signal; and a second terminal of the second storage element switch which is connected to the sense line and appears on the sense line. And a second storage element for storing a potential. 6. The semiconductor memory circuit according to claim 5, wherein said first and second storage elements are capacitance means. 7. The semiconductor according to claim 6, wherein a first terminal of said capacitance means is connected to said storage element switch means, and a second terminal of said capacitance means is connected to a predetermined potential source. Storage circuit. 8. A first terminal of said capacitance means is connected to said storage element switch means, and a second terminal of said capacitance means is connected to the other of said set of sense lines via another storage element switch means. 7. The semiconductor memory circuit according to claim 6, wherein said semiconductor memory circuit is connected. 9. A first circuit for outputting a first selection signal, a first switch control signal, a first storage element control signal, and a first sense amplifier activation signal in response to a row address signal.
A second selection signal in response to the row address signal;
A second row address storage circuit that outputs a switch control signal, a second storage element control signal, and a second sense amplifier activation signal, a third selection signal, a third selection signal, and a third selection signal in response to the row address signal.
A third row address storage circuit that outputs a switch control signal, a third storage element control signal, and a third sense amplifier activation signal, a fourth selection signal, a fourth selection signal,
A fourth row address storage circuit that outputs a switch control signal, a fourth storage element control signal, and a fourth sense amplifier activation signal, and a first word in response to the first and second selection signals. A first row decoder for selecting a line, a second row decoder for selecting a second word line in response to the third and fourth selection signals, and the first word line and the first bit A first memory cell array having a memory cell at an intersection with a line; a second memory cell array having a memory cell at an intersection with the second word line and the second bit line; A sense amplifier array having a plurality of sense amplifiers for amplifying a potential difference between a pair of sense lines in response to a sense amplifier activation signal; and a pair of the first bit lines and one end of the pair of sense lines. Provided between First switch means for connecting one set of the first bit lines and one set of sense lines in response to the first or second switch control signal; and one set of the second bit lines. A second terminal connected between the other end of the pair of sense lines and connecting the pair of second bit lines to the pair of sense lines in response to the third or fourth switch control signal; And a first terminal connected to at least one of the pair of sense lines and performing an on / off operation in response to the first storage element control signal and the refresh cycle detection signal. A storage element switch, a first storage element connected to a second terminal of the first storage element switch, and storing a potential appearing on the sense line; Connected to at least one of the sense lines, A second storage element switch means that is turned on / off in response to the storage element control signal and the refresh cycle detection signal of the above, and connected to a second terminal of the second storage element switch means, A second storage element for storing a potential appearing on the line, a first terminal connected to at least one of the set of sense lines, and responsive to the third storage element control signal and the refresh cycle detection signal, A third storage element switch means that is turned on / off, a third storage element connected to a second terminal of the third storage element switch means and storing a potential appearing on the sense line; One terminal is connected to at least one of the pair of sense lines, and is turned on / off in response to the fourth storage element control signal and the refresh cycle detection signal. 4 storage element switch means, and a fourth storage element connected to the second terminal of the fourth storage element switch means and storing a potential appearing on the sense line. Semiconductor storage circuit. 10. The semiconductor memory circuit according to claim 9, wherein said first to fourth memory elements are capacitance means. 11. The capacitor according to claim 1, wherein a first terminal of the capacitor is connected to the switch for the storage element, and a second terminal of the capacitor is connected to a predetermined potential source.
0. A semiconductor memory circuit according to item 0. 12. A first terminal of said capacitance means is connected to said storage element switch means, and a second terminal of said capacitance means is connected to the other of said set of sense lines via another storage element switch means. 11. The semiconductor memory circuit according to claim 10, wherein the semiconductor memory circuit is connected.