JP3082684B2 - Cache memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to a cache memory.

[0001]

2. Description of the Related Art In a conventional information processing apparatus, two types of cache memories, namely, a set associative type cache memory and a full associative type cache memory are used to improve a hit ratio. In the set associative cache, one line is allocated to one index. Further, since a plurality of entries can be registered for the same index, it is possible to have a plurality of the above configurations. Therefore, the hit rate is increased by increasing the number of entries.
Although it can be improved to some extent, in order to increase the hit rate for all jobs, finally, only an increase in the capacity is the corresponding means.

However, in practice, it is necessary to provide the same capacity for an index having many misses and for an index having a relatively small access, so that it can be said that the investment effect of increasing the capacity is low. In the full associative cache memory, the entry is free irrespective of the index as compared to the set associative cache memory, so that the highest hit rate can be expected with the same capacity. However, in order to make a hit / miss hit determination, all entries must be compared, and the operation speed and the amount of hardware become problems.

[0003]

In recent years, the speed and performance of microprocessors have been remarkably improved. Ironically, however, the speed improvement of the memory is slow, and the performance of the information processing device is not as high as that of the microprocessor. In order to bridge this speed difference, cache memory was devised based on the concept of copying a part of memory having the same response speed as a microprocessor, and showed a dramatic improvement in performance. It is becoming a problem that the transfer speed of the memory to be seen at the time of a mishit significantly lowers the performance. That is, it can be said that improving the hit rate of the cache memory is a shortcut to improving the performance of the entire information processing apparatus.

[0004] However, the speed required for the cache memory is the same as that of a microprocessor, and it is ideal that the cache memory be provided in a chip in consideration of the access time. However, it is difficult to mount a large-capacity cache memory in the chip. Since the capacity is generally used, it is difficult to expect a high hit rate. For this reason, there is a need for a cache memory having a small amount of hardware, a small capacity, and a high hit rate.

It is an object of the present invention to increase or decrease the number of lines in which one index can be registered depending on the number of cache misses, while being able to be incorporated in a high-speed microprocessor and following the structure of a conventional set-associative cache memory. Another object of the present invention is to provide a cache memory capable of achieving a high hit ratio even with a small capacity by enabling a threshold value for the number of mishits to be set by software.

[0006]

According to the cache memory of the present invention, for an index in an address, the number of entries in which one index can be registered is determined by the number of cache memory misses and a threshold set by software. It can be changed based on.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, the embodiment of the present invention comprises a microprocessor 108 and an external memory 109. The microprocessor 108 includes an address register unit 101, a data register unit 102, a first address array unit 103, a second address array unit 104, a data array unit 105, and an in-way LRU.
A (Least Recently Used) logic unit 106 and an inter-way LRU logic unit 107 are provided.

The first address array section 103 has offset signals for the number of indexes and hidden bits as lower bits of the index for the number of lines. The second address array unit 104 holds a tag as in a conventional cache memory. The data array unit 105 stores data on a memory corresponding to each address array. Inter-way LRU logic unit 107 when the number of ways is plural
Determines which way is updated when a cache miss occurs, and the in-way LRU logic unit 106
7 within the way determined by the address array unit 103.
Decide if you want to increase registrations in.

The operation of this embodiment will be described for each of a load instruction and a store instruction. First, in the case of a load instruction, an address is given to the register unit 101. The address array unit 103 is searched by the index part in the address. At that time, first, a line whose registration is fixed is searched to obtain an offset value. From this offset value, it is possible to know in which line the input index portion is registered.

FIG. 2 shows an example of the contents of the array units 103 and 104. The array unit 104 has an index “0”,
"1" and "2" are assigned so that they can be used in a fixed manner every other line, and a line between them can be used with an index sandwiching the line. The right side of the array unit 103 holds hidden bits of each line, and the left side holds an offset value indicating which line is registered for each index. For example, when the maximum number of three lines is used, “111” is set. When only one line is used, “010” is set.
Either “110” or “011” can be distinguished depending on the position of 1 at either the top or bottom of the line. In the figure, initial values are set.

According to the offset signal, the hidden bit of the line used by the index is read and compared with the address of the register 101. The interval at which fixed lines are allocated to the index and the bit width of the offset have an important causal relationship, and they are invariant in software and involve the amount of hardware.

In addition, the number of lines that can use one index is determined by the above setting. In this case,
Since up to three lines can be used for one index, three comparators are required. Further, the array unit 104 is searched from the offset signal in the same manner as the hidden bit,
The tags are compared, and if any one of the number candidates is the same as the tag and the hidden bit, it is determined to be a hit, and if both are different, it is determined to be a mishit. Actually, the entry of the cache memory is updated only at the time of a cache miss, so that there can be at most one identical tag having the same hidden bit.

Regarding the array section 104, the array section 103
Similarly, three comparators for the maximum number are required. In the case of a hit, data is retrieved from the data array unit 105, output from the signal line 110, and the logic unit 107 is updated. In the case of a mishit, as in the conventional cache memory, the logic unit 107 determines a way to be updated, and the logic unit 106 determines whether to increase the number of entries (lines) of the missed index. After receiving the block data of the address section and updating the data of the line section output by the logic section 106,
The data is transmitted to the signal line 110.

The operation of the logic unit 106 at the time of a mishit will be described with reference to FIG. The cache-missed index 301 is received by the way to be updated output from the logic unit 107, and the counter 302 corresponding to the index is incremented by one. As a result, the threshold value is compared with a threshold value set in advance by software, and if the threshold value is exceeded, the number of entries in the missed index is increased. If the number has been reached, all three entries are invalidated, updated to the initial state, and updated.

In the case of a store instruction, it is the same as a conventional cache memory. The difference from the load instruction is that the address and data are sent from the control unit, hit / miss hit determination similar to that of the load instruction is performed, an update is performed when a hit occurs, and update information is sent to the memory 109. If a mistake is made, the update information is sent only to the memory 109 and the LRU
Does not update the logic section. Accordingly, the logic unit 106 does not count the number of misses even in the case of a miss.

As described above, the cache memory of the present invention has a certain degree of flexibility in the entry method with respect to the conventional set associative cache memory. In other words, following the set associative structure in order to maintain high speed, instead of allocating the index to all the lines, the index is discretely allocated by the high-order bit of the index, and the index that is not allocated to the line not allocated between It is configured to be used with.

Also, since which index is used is determined in real time by the number of cache misses, only one line is allocated to an index with a low access frequency, but an index with a high access frequency is allocated. The number of entries can be increased, and the use efficiency of the memory area of the cache memory is higher than that of the conventional set associative type.

Also, the number of comparators may be the maximum number of entries that can be registered for a certain index, so that the amount of hardware may be smaller than that of a full associative cache memory. Further, although the number of entries in the index increases or decreases depending on the number of mishits, the threshold value can be set by software, so that the hit rate can be more flexibly improved.

[0020]

The first effect is that the line capacitance is variable depending on the number of misses. As a result, an improvement in the hit rate can be expected for a job whose hit rate depends on the line capacity.

The reason is that a plurality of tags can be registered with the same index and the same tag, and the line capacity corresponding to the hidden bit width can be maximized.

The second effect is that the frequency of increase and decrease of entries can be adjusted according to the job to be executed, and the hit ratio can be adjusted for the same job.

The reason is that the threshold value for determining the increase or decrease of entries can be set by software.

A third effect is that the number of comparators automatically determined when a conventional set associative type or full associative type is selected is reduced in both the hit ratio and the area (the number of comparators) in the present invention. Adjustments are possible.

The reason is that the required number is determined by the maximum number of registrations for one index, the number of comparators being set in advance by hardware, and it is possible to adjust both the flexibility for the entry and the amount of hardware. It is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of first and second address arrays.

FIG. 3 is a diagram showing an in-way LRU logic unit for increasing or decreasing the number of entries according to the number of misses.

[Explanation of symbols]

 Reference Signs List 101 address register section 102 data register section 103 first address array section 104 second address array section 105 data array section 106 in-way LRU logic section 107 inter-way LRU logic section

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/08-12/12

Claims (3)

(57) [Claims] (1)Set associative cash
In Mori, Set of high-order bits of consecutive indexes in the address
For each of the combinations, each said set of upper bits is
A logic unit for allocating a data storage area to be managed, Each of the upper bit sets of the index is
To manage whether data storage areas are allocated
An address array; Said data to which each of said set of upper bits is assigned
Data management in the storage area before the index
The second is managed by the lower bits excluding the upper bits.
An address array, The logic section is fixed for each of the upper bit sets.
The data storage area is divided and
Assigned to any management area of the set of upper bits.
Undefined data storage areas that have not been allocated
The number of cache access mistakes and the threshold set by software
By the above, the data adjacent to the indefinite data storage area
Any of the above set of higher-order bits whose storage area is a management area
Dynamically allocated as a management area Characterized by
Cache memory. 2. The logic unit according to claim 1, wherein the logic unit includes a set of the upper bits.
Memory access to the management area managed by either
The number of misses exceeds the threshold set by the software
In this case, the above-mentioned bit adjacent to the fixed management area
The constant data storage area is allocated to the management area of the upper bit set.
2. The cache memory according to claim 1, wherein the cache memory is used. 3. The logic unit according to claim 2 , wherein:
Is a fixed management area and the adjacent
When the entire data storage area is used as the management area,
The number of mishits for the management area of the
If the threshold value set by software is exceeded,
The cache memory of claim 2, wherein to disable all set management area, wherein the this <br/> updating the initial state.