JP3077891B2 - Semiconductor device memory cell and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell and a method of manufacturing the same, and more particularly, to a structure of a stack type charge storage capacitor of a dynamic random access memory (DRAM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 12 is a schematic sectional view of a memory cell portion of a conventional semiconductor device.

A so-called MOS type DR in which a memory cell is constituted by one MOS transistor and one capacitor
AM continues to be highly integrated. As the degree of integration increases, the area of a capacitor for storing information decreases, and thus the amount of stored charge decreases. As a result, there is a problem that the contents of the memory are destroyed.

In order to solve such a problem, a storage electrode is required.
There has been proposed a structure in which a plate electrode is provided so as to sandwich it.
I have. Manufacturing proposed in Japanese Patent Application Laid-Open No. 2-2005069
The method will be described with reference to FIG. FIG. 12
1 is a p-type silicon (p-Si) substrate, 2 is a cell region
Field oxide silicon film that separates
Silicon oxide film, 4 from polycrystalline silicon (poly Si)
Gate electrode and word line 5 and n^ー Type diffusion layer saw
Area, 6 is n^ー Drain region of type diffusion layer, 7 is dioxide
Silicon (SiO_Two ) It is composed of a film and covers the gate electrode.
The edge film 8 is a lower first plate electrode made of poly-Si.
The pole 9 is made of poly-Si and n^ー Type diffusion layer saw
The storage electrode connected to the storage region 5 is made of silicon dioxide.
(SiO _Two ) Lower first plate electrode made of a film or the like
A capacitor insulating film forming a capacitor between the storage electrode 8 and the storage electrode 9;
Reference numeral 1 denotes an upper second plate electrode made of a poly-Si film;
2 is silicon nitride (Si_ThreeN_Four) Film or SiO_Two Membrane S
i_ThreeN_FourThe upper second plate electrode 11
A capacitance insulating film for forming a capacitance between the electrode and the product electrode 9;
An interlayer insulating film such as silicate glass (PSG);
Bit line of aluminum (Al) or the like. As described above,
According to the above description, above the gate electrode 4 and above the field insulating film.
In the one region, the storage electrode 9 is provided above and below the capacitor insulating film 10,
The first plate electrode 8 and the second plate electrode 8
A charge storage capacitor portion is formed with both of the poles 11. for that reason
In addition, the cell occupation area can be significantly reduced without reducing the amount of stored charge.
Less is possible.

[0005]

However, in the conventional method, a step of patterning the first plate electrode 8 is newly required, which is time-consuming and expensive. An object of the present invention is to solve such a problem.
An object of the present invention is to provide a structure of a stack type charge storage capacitor portion capable of greatly reducing the cell occupation area without reducing the amount of stored charge in a small number of steps, and a method of manufacturing the same.

[0006]

According to the present invention, in order to solve the above-mentioned problems, a first plate electrode located below a storage electrode via a capacitor insulating film is formed in the same shape as a gate electrode or a bit electrode. By patterning in the same shape as the line, the step of patterning the first plate electrode can be omitted, and both the first and second plate electrodes of the storage electrode and the charge storage capacitor can be interposed via the capacitor insulating film. Provided is a structure of a stack-type charge storage capacitor section which can form an electric section and store sufficient charges, and a method of manufacturing the same.

When the structure of the present invention is used, the first plate electrode can be patterned in the same step as the gate electrode or the bit line.
It is possible to form both the second plate electrode and the storage electrode forming the capacitor. As a result, the area of the storage electrode increases, and sufficient charge can be stored, so that the width of the cell occupation surface can be significantly reduced, and a highly reliable product can be provided at low cost.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1A to 1H are schematic views of a memory cell portion showing a method of manufacturing an embodiment of a semiconductor memory cell according to the present invention in the order of steps, taken along line AA ′ of FIG. 3B. Sectional view,
FIG. 2 shows a line A of FIG. 3B of the memory cell part product of this example.
FIG. 3A is a schematic cross-sectional view, and FIGS. 3A and 3B are schematic plan views of the memory cell portion of the present example, and FIGS. 4A, 4B, and 4C.
FIG. 3 is a schematic cross-sectional view of a contact between a gate electrode and a wiring layer of a peripheral circuit portion of the semiconductor device of the present example.

First, as in the conventional example, as shown in FIG. 1A, the upper surface side of a p-type semiconductor substrate 1 made of silicon is separated by an element isolation insulating film 2 made of a thermal silicon dioxide film.

Next, as shown in FIG. 1B, a gate insulating film 3 made of a thermal silicon dioxide film having a thickness of about 120.degree.
A gate electrode material 4 made of polycrystalline silicon of about 00 ° by reduced pressure vapor deposition (CVD), an insulating film 15 of about 4000 ° in thickness, for example, a silicon dioxide film by normal pressure CVD, and a normal pressure CVD of about 3000 ° in thickness. A first plate electrode material 16 made of polycrystalline silicon is sequentially deposited, and a photoresist (not shown) is patterned into a predetermined shape. Using this photoresist as a mask, gate electrode material 4, insulating film 15, first plate electrode material 1
6 is anisotropically etched. This anisotropic etching
For example, by reactive ion etching, first, the first plate electrode material 16 is etched with an etching gas Cl ₂ flow rate of 200 scc.
m, HBr flow rate 200sccm, pressure 300mTorr
r, etching under the condition of RF power 200W,
An insulating film 15 is formed by etching gas CF _{4 at a} flow rate of 40 sccm,
CHF ₃ flow rate 400sccm, Ar flow rate 800scc
m, pressure 800 mTorr, RF power 800 W, and further, the gate electrode material 4 is etched with an etching gas Cl ₂ flow rate of 200 sccm and an HBr flow rate of 200 sc
Etching is performed under the conditions of cm, pressure 300 mTorr, and RF power 200 W. Further, the present invention is not limited to this example.
Is a BPSG (Boron Phospho Sili)
(Cate Glass) film or PSG film. Similarly, the first plate electrode material 16 may be a conductor film such as tungsten silicide. Phosphorous or arsenic that becomes n-type in the p-type silicon substrate 1 is converted to an energy of 30 keV.
In injected about 1El3cm ^-2, n ^- source region of the diffusion layer 5 and n ^- drain regions 6 of the diffusion layer.

Next, as shown in FIG. 1 (c), the gate electrode 4 and the first plate electrode 16 are laid at a normal pressure of about 3000.degree.
It is covered with an insulating film 7 made of a VD silicon dioxide film.

Next, as shown in FIG. 1D, the upper surface of the first plate electrode 16 is exposed by anisotropic etching.
The side wall insulating film 7 of the gate electrode 4 is formed.

Next, as shown in FIG. 1 (e), after the natural silicon dioxide film on the surface of the first plate electrode 16 is removed by hydrofluoric acid or the like, a silicon nitride film of about 80.degree. Then, steam oxidation is performed at about 800 ° C. to form a capacitive insulating film 10 of about 50 ° in terms of silicon dioxide film pressure.

Next, as shown in FIG. 1F, a part of the source region 5 of the n ⁻ -type diffusion layer is exposed by anisotropic etching using a photoresist (not shown) as a mask, and a film thickness of 300 nm is formed.
A storage electrode material 9 made of polycrystalline silicon is deposited by atmospheric pressure CVD of about 0 °, and anisotropic etching (for example, etching gas Cl ₂ flow rate of 200 sccm by reactive ion etching using a photoresist (not shown) as a mask) is used.
HBr flow rate 100sccm, pressure 500mTorr, R
The storage electrode 9 is formed so as to face the first plate electrode 16 via the capacitor insulating film 10 under the condition of F power of 250 W).

Next, as shown in FIG. 1 (g), after removing the natural silicon dioxide film on the surface of the storage electrode 9 with hydrofluoric acid or the like, a silicon nitride film is formed on the entire surface by a reduced pressure CVD with a thickness of about 80 °, The capacity insulating film 12 is formed by performing steam oxidation at about 800 ° C.

Next, as shown in FIG.
A second plate electrode made of polycrystalline silicon having a thickness of about 3000 ° is formed thereon. As shown in FIG.
An interlayer insulating film 13 made of a BPSG film having a thickness of about
^- a photoresist (not shown) a portion of the drain region 6 of the diffusion layer is exposed by anisotropic etching using the mask, the bit contact 19 is formed, the composite of tungsten silicide or tungsten silicide and tungsten having a thickness of about 2000Å Bit line 14 made of film
To form

FIGS. 3A and 3B show the present embodiment.
When the present invention is applied to a memory cell having such a shape, the storage electrode area of the storage capacitor portion increased by the first plate electrode 16 is a portion 22 where the first plate electrode 16 and the storage electrode 9 overlap, and 3 (a) and 3 (b) are increased by about 20% compared to the case where one plate electrode 16 is not provided. Since the capacity that can be stored is increased in this manner, the width of the cell occupation surface can be significantly reduced, and a highly reliable product can be provided at low cost.

Furthermore, in the present invention, the step of patterning the first plate electrode can be performed simultaneously with the formation of the gate electrode, so that the application of photoresist for patterning, alignment, fog light, Development, etching and photoresist removal steps can be reduced,
Productivity is improved.

By the way, in the case of the present invention, since the first plate electrode 16 is provided on the word line 4, to connect a contact to the word line 4, FIGS.
(C). Anisotropic etching is performed until a part of the word line 4 is exposed from above the interlayer insulating film 13, and a film thickness of 20
An insulating film 17 made of, for example, a silicon dioxide film by normal pressure CVD of about 00 ° is deposited. Next, the insulating film 17 is etched back by anisotropic etching to form the contact 18.
Then, an insulating layer is formed on the side wall of the substrate to expose a part of the word line 4 to form a wiring layer phase 21.

Further, the first plate electrode 16 and the second plate electrode 11 can be set to the same potential by being electrically connected in the peripheral circuit section.

Next, a second embodiment will be described.

FIGS. 5A to 5H show the manufacturing method of the second embodiment in the order of the steps in the memory cell portion shown in FIG.
3 is a schematic sectional view corresponding to line AA ′ of FIG.

As shown in FIG. 5A, steps up to the deposition of the insulating film 15 are performed in the same manner as in the first embodiment. Next, a first plate electrode material 16 made of polycrystalline silicon is deposited by atmospheric pressure CVD with a film thickness of about 6000 °. The film thickness of the first plate electrode material 16 is
Step h between the gate insulating film 3 and the gate insulating film 3 (see FIG. 5A). Next, a photoresist (not shown) is patterned into a predetermined shape. Using this photoresist as a mask, the gate electrode material 4, the insulating film 15, and the first plate electrode material 16 are anisotropically etched. This anisotropic etching is performed, for example, by reactive ion etching with an etching gas Cl ₂ flow rate of 200 sccm and an HBr flow rate of 200 sc
cm, pressure 300 mTorr, and RF power 200 W. Further, the insulating film 15 is not limited to this example.
An insulating film such as a G film or a PSG film may be used. Similarly, the first plate electrode material 16 may be a conductor film such as tungsten silicide. Phosphorous or arsenic that becomes n-type is implanted in the p-type silicon substrate 1 at an energy of 30 keV and about 1 El3 cm ⁻² to form a source region 5 of the n − type diffusion layer and a drain region 6 of the n − type diffusion layer.

Next, as shown in FIG. 5B, the gate electrode 4 and the first plate electrode 16 are made of inorganic S
It is covered with an insulating film 23 having good flatness such as OG.

Next, as shown in FIG. 5C, the CMP (Che
mechanical MechanicalPolish
By g), the upper surface of the first plate electrode 16 is exposed. At this time, the first plate electrode 1 on the gate insulating film 3
6b and the first plate electrode 16a on the element isolation insulating film 2.
Are exposed together, that is, "the thickness of the insulating film 23 on the first plate electrode 16a", "the step between the element isolation insulating film 2 and the gate insulating film 3", and "the polishing margin". Is polished by the total film thickness.

Next, as shown in FIG. 5D, after removing the white silicon dioxide film on the surface of the first plate electrode 16 by washing or the like, a silicon nitride film of about 80 ° in thickness is formed on the entire surface by low pressure CVD. Then, steam oxidation is performed at about 800 ° C. to form a capacitance insulating film 10 of about 50 ° in terms of silicon dioxide film thickness.

Next, as shown in FIG. 5E, a photoresist (not shown) is patterned into a predetermined shape. Using this photoresist as a mask, anisotropic etching is performed to form a capacity contact 20.

After that, as shown in FIGS. 5F, 5G, and 5H, as in the first embodiment.

According to the second embodiment, since the capacitance insulating film 10 made of a silicon nitride film or the like does not directly touch the semiconductor substrate 1, there is no fear that the leakage current on the surface of the semiconductor substrate 1 increases. We can provide highly reliable products.

Next, a third embodiment will be described.

FIGS. 6A to 6E show the manufacturing method of the third embodiment in the order of steps in the memory cell portion of FIG.
3 is a schematic sectional view corresponding to line AA ′ of FIG.

The steps up to FIG. 1C are performed in the same manner as in the first embodiment. However, the insulating film 7 is the element isolation insulating film 2
The thickness is set to be at least half the interval between the upper word lines 4.

Next, as shown in FIG. 6A, the upper surface of the first plate electrode 16 is exposed by anisotropic etching of the insulating film 7, and a part of the side surface of the first plate electrode 16 is further removed. Or expose all. This anisotropic etching may be performed about the thickness of the first plate electrode 16 after the upper surface of the first plate electrode 16 is exposed. Since the film thickness of the insulating film 7 between the word lines 4 on the element isolation insulating film 2 is sufficiently large, the element isolation insulating film 2 immediately thereunder is not etched by this anisotropic etching.

The subsequent steps are performed in the same manner as in the first embodiment. [FIGS. 6B to 6E] According to the third embodiment, as shown in FIG. 6E, not only the upper surface but also the side surface of the first plate electrode 16 has the capacitance insulating film 1.
Since it is opposed to the storage electrode 9 via 0, a capacitance portion capable of storing a larger charge than in the first embodiment is formed. The increase is determined by the side area of the first plate electrode 16, that is, the thickness of the plate electrode material. A capacitance portion capable of storing an electric charge approximately 30% larger than that of the first embodiment is formed. Therefore, a highly reliable product can be provided.

Next, a fourth embodiment will be described.

FIGS. 7A to 7F are sectional views of the memory cell portion showing the manufacturing method of the fourth embodiment in the order of steps.
3 is a schematic sectional view corresponding to line AA ′ of FIG.

The steps up to FIG. 1C are performed in the same manner as in the first embodiment.

Next, as shown in FIG. 7A, an insulator 23 having good flatness such as inorganic SOG is deposited on the surface.

Next, a part or all of the side surface of the first plate electrode 16 is exposed by anisotropic etching similar to that of the third embodiment.

The subsequent steps are performed in the same manner as in the second embodiment. [FIGS. 7 (c) to 7 (e)] According to the fourth embodiment, since the capacitance insulating film 10 made of a silicon nitride film or the like does not directly touch the semiconductor substrate 1, the leakage current on the surface of the semiconductor substrate l There is no concern about the increase of the first plate electrode 1 as shown in FIG.
Since not only the upper surface but also the side surface of the capacitor 6 is opposed to the storage electrode 9 via the capacitance film 10, it is possible to provide a product with higher reliability than the third embodiment.

Next, a fifth embodiment will be described.

FIGS. 8A to 8F are views of the memory cell section showing the manufacturing method of the fifth embodiment in the order of steps, and FIGS.
3 is a schematic sectional view corresponding to line AA ′ of FIG.

The steps up to FIG. 5C are performed in the same manner as in the second embodiment.

Next, as shown in FIG. 8A, an insulator 23 having good flatness, such as inorganic SOG, is deposited on the surface.

Next, as shown in FIG.
The upper surface of the first plate electrode 16 is exposed. At this time,
The film thickness such that the first plate electrode 16b on the gate insulating film 3 and the first plate electrode 16a on the element isolation insulating film 2 are both exposed, that is, "the thickness of the insulating film 23 on the first plate electrode 16a. Polishing is performed by a total film thickness of "film thickness", "step between element isolation insulating film 2 and gate insulating film 3", and "polishing margin".

Next, as shown in FIG. 8C, the insulator 23 is etched by anisotropic etching to a thickness of the remaining portion of the first plate electrode 16a on the element isolation insulating film 2.

The subsequent steps are performed in the same manner as in the third embodiment. [FIGS. 8 (d) to 8 (f)] According to the fifth embodiment, since the capacitor insulating film 10 made of a silicon nitride film or the like does not directly touch the semiconductor substrate 1, the leakage current on the surface of the semiconductor substrate 1 There is no concern about increase of the first plate electrode 1 as shown in FIG.
Since not only the upper surface but also the side surface of the capacitor 6 faces the storage electrode 9 via the capacitance film 10, a product with higher reliability than the third embodiment can be provided.

Next, a sixth embodiment will be described.

FIGS. 9A and 9B are schematic plan views of the memory cell portion of the sixth embodiment, and FIGS. 10A to 10F and FIGS. FIG. 10B is a schematic cross-sectional view of the memory cell section showing the manufacturing method of this example in the order of steps, taken along line BB ′ and line CC ′ in FIG. 9B.

First, as in the conventional example, as shown in FIG. 1A, the upper surface of a p-type semiconductor substrate 1 made of silicon is separated by an element isolation insulating film 2 made of a thermal silicon dioxide film.

First, similarly to the conventional example, as shown in FIG.
The upper surface of a p-type semiconductor substrate 1 made of silicon is separated by an element isolation film 2 made of a thermal silicon dioxide film.

Next, in the memory cell, through a gate insulating film 3 made of a thermal silicon dioxide film having a thickness of about 120.degree. A gate electrode material 4 made of polycrystalline silicon is deposited, and a photoresist (not shown) is patterned into a predetermined shape. The gate electrode material 4 is anisotropically etched using the photoresist as a mask. p
Phosphorus or arsenic, which becomes n-type, is implanted in the silicon substrate 1 at an energy of 30 keV to about 1 El3 cm ⁻² to form a source region 6 of an n − type diffusion layer and a drain region 5 of an n − type diffusion layer (not shown). Next, the gate electrode 4 is formed to a thickness of 300.
It is covered with an insulating film 7 made of a normal pressure CVD silicon dioxide film of about 0 °. Next, the side wall insulating film 7 of the gate electrode 4 is formed by anisotropic etching.

Next, as shown in FIG.
Depositing an interlayer insulating film 13 of about Å BPSG film;
A bit contact 19 is formed by exposing a part of the n − type diffusion layer 6 by anisotropic etching using a photoresist (not shown) as a mask. Next, as shown in FIG.
Conductor film 14 made of tungsten silicide or a composite film of tungsten silicide and tungsten having a thickness of 2000 .ANG.
Film 24 made of silicon dioxide film with a thickness of 30
A first plate electrode material 25 made of a polycrystalline silicon film is sequentially deposited by atmospheric pressure CVD of about 00 °, and the conductor film 14, the insulating film 24, the anisotropically etched first plate electrode are formed using a photoresist (not shown) as a mask. The material 25 is anisotropically etched. This anisotropic etching is performed, for example, by reactive ion etching. First, the first plate electrode material 25 is etched with an etching gas Cl ₂ flow rate of 200 sccm.
HBr flow rate 200sccm, pressure 300mTorr, R
Etching is performed under the condition of F power of 200 W, and then the insulating film 24 is etched with a switching gas CF ₄ flow rate of 40 sccm and CHF
₃ Etching is performed under the conditions of a flow rate of 400 sccm, an Ar flow rate of 800 sccm, a pressure of 800 mTorr, and an RF power of 800 W. Further, the conductive film 14 is further etched with an etching gas Cl ₂ flow rate of 200 sccm, an HBr flow rate of 200 sccm, and a pressure of 3.
Etching is performed under the conditions of 00 mTorr and RF power of 200 W. Further, the insulating film 24 is not limited to this example,
(Boron Phospho Silicate G
(insulation film) such as a glass film or a PSG film. Similarly, the first plate electrode material 25 may be a conductor film such as tungsten silicide.

Next, as shown in FIG. 10F, an insulating film 27 made of a BPSG film having a thickness of about 1 μm is deposited.

Next, as shown in FIG. 10G, the upper surface of the first plate electrode material 25 is exposed by CMP. Alternatively, an insulator having good flatness such as inorganic SOG is deposited instead of the insulating film 27, and anisotropic etching (for example, reactive etching ions, etching gas CF ₄ flow rate 40 s)
ccm, CHF ₃ flow rate 400 sccm, Ar flow rate 800
sccm, pressure 800mTorr, RF power 800W
May be performed to expose the upper surface of the first plate electrode material 25. Next, after removing the natural silicon dioxide film on the upper surface of the first plate electrode 25 with hydrofluoric acid or the like, a silicon nitride film is formed on the entire surface by low pressure CVD with a thickness of about 80 °, and steam oxidation is performed at about 800 ° C. A capacitance insulating film 26 having a thickness of about 50 ° in terms of silicon dioxide thickness is formed.

Next, as shown in FIG. 10H, a part of the source region 5 of the n − -type diffusion layer is exposed by anisotropic etching using a photoresist (not shown) as a mask to form a capacitor contact 20. . Next, a storage electrode material 9 made of polycrystalline silicon having a film thickness of about 3000.degree.
And anisotropic etching using a photoresist (not shown) as a mask (for example, reactive ion etching using an etching gas Cl ₂ flow rate of 200 sccm, an HBr flow rate of 1)
00sccm, pressure 500mTorr, RF power 25
Under the condition of 0 W), the storage electrode 9 is formed so as to face the first plate electrode 25 with the capacitance insulating film 26 interposed therebetween.
FIG. 10 is a cross-sectional view in the vertical direction of the gate line in the steps up to here.
(D). Next, after removing the natural silicon dioxide film on the surface of the storage electrode 9 with hydrofluoric acid or the like, a silicon nitride film is formed on the entire surface by low pressure CVD at about 80 ° C., and steam oxidation is performed at about 80 ° C. to form the capacitance insulating film 12. Form. Next, a second plate electrode 11 made of polycrystalline silicon having a thickness of about 3000 ° is formed on the capacitance insulating film 12.
FIG. 10 is a cross-sectional view in the vertical direction of the gate line in the steps up to here.
(E).

When this embodiment is applied to the cell shape as shown in FIGS. 9A and 9B, the first plate electrode 25
The storage electrode area of the storage capacitor portion increased by the first plate electrode 25 and the storage electrode 9 overlaps with the portion 2
8, which is about 15% more than in the case where the first plate electrode 25 is not provided. Since the capacity that can be stored is increased in this manner, the cell occupation area can be significantly reduced, and a highly reliable product can be provided at low cost.

Further, in the present invention, the first plate electrode 2
5 can be performed at the same time as the formation of the bit line 14, so that the application of photoresist for p-turning, alignment, exposure, development,
The steps of etching and photoresist removal can be reduced, and the productivity is improved.

By the way, in the case of the present embodiment, since the first plate electrode 25 is provided on the bit line 14, it is necessary to connect the contact to the bit line 14 from above by using the word of the first embodiment. What is necessary is just to make the method similar to the method of connecting a contact on a line.

The first plate electrode 25 and the second plate electrode 11 can be set to the same potential by being electrically connected in the peripheral circuit section.

Next, a seventh embodiment will be described.

FIGS. 11A to 11D are cross-sectional views of the memory cell portion showing the manufacturing method of the seventh embodiment in the order of steps.
It is a schematic cross section equivalent to line BB 'of (b).

As in the sixth embodiment, as shown in FIG. 11A, the bit line 14, the insulating film 24, and the first plate electrode 25 are patterned into a predetermined shape. Next, after removing the natural silicon dioxide film on the surface of the first plate electrode 25 using hydrofluoric acid or the like, the entire surface is subjected to low pressure CVD with a thickness of about 80 °.
To form a capacitor insulating film 26 by performing steam oxidation at a temperature of about 800 ° C.

Next, as shown in FIG. 11B, a part of the source region 5 of the n − -type diffusion layer is exposed by anisotropic etching using a photoresist (not shown) as a mask to form a capacitor contact 20. . Next, a storage electrode material 9 made of polycrystalline silicon having a film thickness of about 3000.degree.
And anisotropic etching using a photoresist (not shown) as a mask (for example, reactive ion etching using an etching gas Cl ₂ flow rate of 200 sccm, an HBr flow rate of 1)
00sccm, pressure 500mTorr, RF power 25
Under the condition of 0 W), the storage electrode 9 is formed so as to face the first plate electrode 25 with the capacitance insulating film 26 interposed therebetween.
FIG. 10 is a cross-sectional view in the vertical direction of the gate line in the steps up to here.
(D). Next, after removing the natural silicon dioxide film on the surface of the storage electrode 9 with hydrofluoric acid or the like, a silicon nitride film is formed on the entire surface by low pressure CVD at about 80 ° C., and steam oxidation is performed at about 80 ° C. to form the capacitance insulating film 12. Form.

Next, as shown in FIG.
A second plate electrode 11 made of a polycrystalline silicon film having a thickness of about 3000.degree.

According to the present embodiment, as shown in FIG. 11D, not only the upper surface but also the side surface of the first plate electrode 25 is opposed to the storage electrode 9 via the capacitor insulating film 26.
It is possible to provide a product with higher reliability than the embodiment.

The embodiment described above is an example to which the present invention is applied, and the present invention is not limited to the above-described embodiment, but is effective as long as it meets the gist of the present invention.

[0069]

As described above, according to the present invention, since the first plate electrode can be patterned in the same step as the gate electrode or the bit line, the first and second plate electrodes can be formed with a small number of steps. It is possible to form a storage electrode that forms a capacitance with both, so that the storage capacitance area can be increased by about 20 to 50% as compared with the case where the first plate electrode is not provided, and a sufficient charge can be stored. Thus, there is an effect that it is possible to provide an inexpensive and highly reliable semiconductor device which can reduce the cell occupation area.

[Brief description of the drawings]

FIGS. 1A to 1H are schematic cross-sectional views of a memory cell portion of a semiconductor device memory cell according to an embodiment of the present invention, taken along line AA ′ of FIG. FIG.

FIG. 2 is a line A in FIG. 3B of the memory cell part product of the present example.
FIG. 4 is a schematic cross-sectional view taken along line −A ′.

FIGS. 3A and 3B are schematic plan views of a memory cell section of the present example.

FIGS. 4A, 4B, and 4C are schematic cross-sectional views of a contact between a gate electrode and a wiring layer of a peripheral circuit portion of the semiconductor device of the present embodiment.

FIGS. 5A to 5H are views showing a manufacturing method according to the second embodiment in the order of steps, and show a line A- in FIG.
FIG. 3 is a schematic sectional view corresponding to A ′.

FIGS. 6A to 6E are views showing a manufacturing method of the third embodiment in the order of steps, and show a line A- in FIG.
FIG. 3 is a schematic sectional view corresponding to A ′.

FIGS. 7 (a) to 7 (f) show a manufacturing method according to a fourth embodiment in the order of steps in a memory cell portion along a line A- in FIG. 3 (b).
FIG. 3 is a schematic sectional view corresponding to A ′.

FIGS. 8A to 8F are cross-sectional views of a memory cell section showing a manufacturing method according to a fifth embodiment in the order of steps, taken along line A-A of FIG.
FIG. 3 is a schematic sectional view corresponding to A ′.

FIGS. 9A and 9B are schematic plan views of a memory cell unit according to a sixth embodiment.

10 (a) to (f) and (g) to (h) respectively show a manufacturing method of the present embodiment in the order of steps of a memory cell portion.
FIG. 10B is a schematic cross-sectional view taken along line BB ′ and line CC ′ in FIG.

FIGS. 11A to 11D are diagrams illustrating a manufacturing method according to a seventh embodiment in the order of steps in a memory cell portion, taken along line B in FIG. 9B;
FIG. 4 is a schematic cross-sectional view corresponding to −B ′.

FIG. 12 is a schematic sectional view of a memory cell portion of a conventional semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type semiconductor substrate 2 element isolation insulating film 3 gate insulating film 4 gate electrode and word line 5 source region of n-type diffusion layer 6 drain region of n-type diffusion layer 7, 15, 17, 23, 24, 27 insulation Film 8 First plate electrode (conventional example) 9 Storage electrode 10, 12, 26 Capacitive insulating film 11 Second plate electrode 13 Interlayer insulating film 14 Bit line 16 First plate electrode (first to fifth embodiments) 18 Contact (on the gate in the peripheral circuit section) 19 Bit contact 20 Capacitance contact 21 Wiring layer 22 Charge storage capacitor section (formed of 16 and 9) 25 First plate electrode (Sixth and seventh embodiments) (Of the embodiment) 28 charge storage capacitors (formed of 25 and 9)

Claims (6)

(57) [Claims] In a semiconductor device memory cell comprising a charge storage capacitor and a switching transistor, a first pattern having the same pattern as a bit line with an insulating film interposed on a bit line connected to a drain side of the switching transistor.
And a charge storage capacitor portion including an upper surface of the first plate electrode and a storage electrode via a capacitor insulating film, and a second electrode via the upper surface and side surfaces of the storage electrode and the capacitor insulating film. A memory cell for a semiconductor device, comprising: a charge storage capacitor portion including a plate electrode. 2. A further semiconductor device memory cells according to claim 1, further comprising a charge storage capacitor comprising a storage electrode through the upper and side surfaces and the capacitance insulating film of the first plate electrode. 3. A method of manufacturing a semiconductor device memory cell comprising a charge storage capacitor portion and a switching transistor, comprising: a) depositing a second conductive layer on a first conductive layer via a first insulating film; b) patterning the first conductive layer and the second conductive layer at the same time, forming the first conductive layer as a gate electrode of a switching transistor, and forming the second conductive layer as a first plate electrode; C) connecting the gate electrode and the first plate electrode to a second
D) exposing an upper surface of the first plate electrode; and e) forming a charge storage capacitor portion including the upper surface of the first plate electrode and a storage electrode with a first capacitor insulating film interposed therebetween. F) forming a charge storage capacitor portion comprising an upper surface of the storage electrode and a second plate electrode with a second capacitor insulating film interposed therebetween; And wherein instead of the step d, the upper surface of the first plate electrode, a portion of the side surface or to expose a whole, in place of the step e, the upper surface of the first plate electrode
4. The method according to claim 3 , further comprising forming a charge storage capacitor portion including a part of or all of the side surface and a storage electrode via the first capacitor insulating film. 5. A method of manufacturing a semiconductor device memory cell comprising a charge storage capacitor portion and a switching transistor, comprising: a) a first insulating film on a first conductive layer connected to a drain side of the switching transistor; Depositing a second conductive layer by b) depositing a first capacitive insulating film on the second conductive layer; c) patterning the first conductive layer and the second conductive layer simultaneously D) forming a storage electrode on the first capacitance insulating film; e) depositing a second capacitance insulating film on the upper surface and side surfaces of the storage electrode; A method for manufacturing a memory cell of a semiconductor device, comprising forming a third conductive layer thereon. 6. A method for manufacturing a memory cell of a semiconductor device comprising a charge storage capacitor and a switching transistor, comprising: a) a first insulating film interposed on a first conductive layer connected to a drain side of the switching transistor. B) simultaneously patterning said first conductive layer and said second conductive layer; c) a first capacitive insulating film on the top and side surfaces of said second conductive layer D) forming a storage electrode on the first capacitive insulating film; e) depositing a second capacitive insulating film on the top and side surfaces of the storage electrode; f) the second capacitive insulating film A method for manufacturing a memory cell of a semiconductor device, comprising forming a third conductive layer on a film.