JP3073402B2 - Output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit with noise suppression.

[0002]

2. Description of the Related Art Conventionally, an output buffer circuit used for an output circuit or the like of a semiconductor memory device uses an output transistor having a large current driving capability. Changes, and noise is generated in an inductive load or the like. When the power supply voltage increases due to the voltage fluctuation, the noise also increases, which may cause a malfunction of the semiconductor device. Further, even when the temperature is low or the threshold voltage of the FET is low, the influence of this noise becomes relatively large, and a malfunction may occur.

Therefore, in order to prevent malfunctions due to such noises, output buffer circuits which take noise countermeasures as shown in FIGS. 11 and 12 have been conventionally proposed.

The output buffer circuit shown in FIG. 11 is composed of two P-channel output transistors Q101 and Q102 and two N-channel output transistors Q103 and Q104 in which output transistors are parallelized, and these are used for signal transmission time. (See Japanese Patent Application Laid-Open No. 3-147418). One P-channel and N-channel output transistors Q101 and Q103 are connected to the other output transistor Q10.
2. It is formed so that the driving ability is lower than that of Q104. The driving circuit 21 for driving one of the output transistors Q101 and Q103 is connected to the other output transistor Q102 and Q102.
The signal transmission time is configured to be shorter than that of the drive circuit 22 for driving the Q104. Therefore, this output buffer circuit is provided with an output transistor Q10 having a high driving capability.
2. By switching the output transistors Q101 and Q103 having a low driving capability before the switching of the transistor Q104, a sudden change in the current can be reduced, thereby suppressing the generation of noise.

The output buffer circuit shown in FIG.
The P-channel and N-channel output transistors Q111 and Q112 are respectively driven by using control circuits 31 and 32 in which the P-channel transistors constituting the CMOS inverter circuit are parallelized and have different driving capabilities. JP-A-4-2055791). In the control circuit 31, the input signal is directly input to the gate terminal of the parallelized P-channel transistor Q113 of the lower driving ability, and the input signal is delayed by the delay circuit 31a before the P driving of the higher driving ability is performed.
The input is made to the gate terminal of the channel transistor Q114. Therefore, the output transistor Q111
Is interrupted, the voltage of the power supply VCC is first supplied by the transistor Q113 having a low driving capability,
After the elapse of the delay time, the voltage of the power supply VCC is also supplied from the transistor Q114 having a high driving capability. The control circuit 32
In this case, the input signal is directly input to the gate terminal of the P-channel transistor Q115 having the lower driving capability, and the input signal is delayed by the delay circuit 32a.
Input to the gate terminal. Therefore, when the output transistor Q112 conducts, the voltage of the power supply VCC is supplied first by the transistor Q115 having a low driving capability, and the voltage of the power supply VCC is also supplied from the transistor Q116 having a high driving capability after a delay time. Is done. Therefore, also in this output buffer circuit, when the voltage of the power supply VCC is supplied to the gate terminals of the output transistors Q111 and Q112 to cut off or conduct, a sudden current change at the time of switching can be reduced. Generation of noise is suppressed.

However, the output buffer circuits shown in FIG. 11 and FIG. 12 reduce noise by uniformly slowing down the switching of the output transistor. When the threshold voltage is high, the signal output is delayed even though the influence of noise is small, which is against the demand for speeding up the output buffer circuit.

For this reason, conventionally, FIGS.
An output buffer circuit as shown in FIG. 16 has also been proposed.

The output buffer circuit shown in FIG.
A power supply voltage adjusting circuit 41 is inserted between a source terminal of a P-channel output transistor Q121 constituting an S inverter circuit and a power supply VCC (Japanese Patent Laid-Open No. 3-354).
No. 97). When the chip select signal CS goes low, the power supply voltage adjusting circuit 41 turns on the transistor Q122 to supply the voltage of the power supply VCC. The upper limit of the voltage supplied to the output transistor Q121 is regulated by the threshold voltage of the transistor Q123. Therefore, even if the voltage of power supply VCC exceeds the threshold voltage of transistor Q123, the voltage supplied to output transistor Q121 is limited to this threshold voltage.
When the voltage of CC is low, it is possible to obtain the effect of reducing noise by limiting the voltage only when the voltage of the power supply VCC is high without impairing the high speed operation of the output transistor Q121.

[0009] The output buffer circuit shown in FIG.
1 and 52, a P-channel output transistor Q13
The gates of the 1 and N-channel output transistors Q132 are input to the gate terminals. These control circuits 5
Reference numerals 1 and 52 allow the output transistors Q131 and Q132 to be turned on only when the output enable signals OE and OE are at H level and L level, respectively. Only when the input signal is at the L level, the control circuit 51 grounds the gate terminal of the output transistor Q131 through the parallel circuit of the N-channel control transistors Q133 and Q134. Only in the case of the level, the gate terminal of the output transistor Q132 is connected to the power supply VCC through a parallel circuit of P-channel control transistors Q135 and Q136. Each control circuit 5
1 and 52, one of the control transistors Q133 and Q135
Has a lower driving capability than the other control transistors Q134 and Q136, and has a gate terminal connected to the power supply VCC or grounded to be always in a conductive state. The gate terminals of the other control transistors Q134 and Q136 have power supply voltage control signals VCCH and VCCH, respectively.
A bar has been entered.

The power supply voltage control signals VCCH and VCCH bar are signals generated by the power supply voltage control signal generation circuit 53 shown in FIG. The power supply voltage control signal generating circuit 53 supplies power to the circuit only when the chip enable signal CE is at L level. The power supply voltage control signal VCCH is connected to the diodes D101 to D101.
The voltage of the power supply Vcc is detected by connecting a series circuit of D104 and an N-channel transistor Q141 to Q143 whose gate terminal is connected to the power supply Vcc to the power supply ground, and this detection output is output to four P-channel transistors. Q144 ~
This signal is generated by outputting the signal through the inverter circuit 53a having Q147 and the three inverter circuits 53b to 53d. Therefore, the power supply voltage control signal VCCH
As shown in FIG. 16, when the voltage of the power supply Vcc is equal to or higher than the set voltage of 5 V, the voltage becomes the same as this power supply Vcc. Becomes The power supply voltage control signal VCCH bar detects the voltage of the power supply VCC by connecting a series circuit of P-channel transistors Q148 to Q151 and diodes D105 to D108 whose gate terminals are grounded between the power supply ground. This is a signal generated by outputting a detection output through an inverter circuit 53e having two N-channel transistors Q152 and Q153 and three inverter circuits 53f to 53h. Therefore, as shown in FIG. 16, the power supply voltage control signal VCCH bar becomes the same voltage as the power supply VCC when the voltage of the power supply VCC is less than 5 V, and sharply when the voltage of the power supply VCC exceeds about 5 V. To a voltage of 0V.

Therefore, in this output buffer circuit, when the voltage of power supply VCC becomes higher than 5 V, power supply voltage control signals VCCH and VCCH bar go to H level and L level, respectively. Only the low control transistors Q133 and Q135 become conductive, and the switching of the output transistors Q131 and Q132 can be slowed to reduce noise. In addition, when the voltage of the power supply VCC is lower than 5 V, the power supply voltage control signal VCC
Since H and VCCH bars go to L level and H level, respectively, the control transistors Q134 and Q136 having high driving capability in the control circuits 51 and 52 conduct, and the output transistor Q
Switching of 131 and Q132 can be performed quickly so that high-speed operation is not impaired.

[0012]

However, in the conventional output buffer circuit shown in FIG. 13, the voltage supplied by the power supply voltage adjusting circuit 41 is slightly lower than the power supply VCC even when the voltage of the power supply VCC is low. There is a problem that the output signal cannot be fully swung because of the voltage.

In each of the output buffer circuits shown in FIG. 13 and FIGS. 14 to 16, the level of the voltage of the power supply VCC is determined depending on the threshold voltage of the transistor. If the threshold voltage fluctuates in the range of about ± 0.2 V due to the variation, the switching of the output transistor may be made slow or quick regardless of the magnitude of the effect of the actual noise.
There is a problem that the control becomes inappropriate. Moreover, the effect of the actual noise fluctuates due to changes in temperature,
Similarly, there is a problem that the control may become inappropriate depending on the temperature. Further, since these output buffer circuits switch control in two stages depending on whether the voltage of the power supply VCC is higher or lower than a predetermined value, it is necessary to finely perform optimal control for each state according to the degree of influence of noise. There was also a problem that it was not possible.

The present invention solves the above-mentioned conventional problems, and continuously controls the switching of the output transistor according to the level of the power supply voltage, and also considers the influence of noise due to temperature and the threshold value of the FET. It is an object of the present invention to provide an output buffer circuit that can perform optimal and accurate noise suppression by performing control.

[0015]

According to the output buffer circuit of the present invention, two control transistors having different driving capacities are inserted in parallel on a circuit in which the control terminal of the output transistor is connected to a power supply or grounded. A drive capacity adjusting circuit is provided which continuously changes in accordance with the level of the power supply voltage and generates control signals complementary to each other, and supplies these complementary control signals to the control terminals of the control transistor. This achieves the above object.

In the output buffer circuit of the present invention, an output transistor comprising a P-channel and an N-channel FET is connected in series between a power supply and a ground, and the gate terminals of these output transistors are connected to a power supply in accordance with an input signal. An output buffer circuit provided with a control circuit connected to or grounded to a control transistor comprising two N-channel FETs having different driving capacities on a circuit in which a gate terminal of a P-channel output transistor is grounded via a control circuit. Are inserted in parallel, and a control transistor composed of two P-channel FETs having different driving capabilities is inserted in parallel on a circuit connecting the gate terminal of the N-channel output transistor to the power supply via the control circuit. It changes continuously according to the level of the power supply voltage,
And control signals for generating the complementary control signals and increasing the higher the power supply voltage, the control transistors of the N-channel having a lower driving capability and the P-channels having a higher driving capability. The other control signal, which is supplied to the gate terminal of the transistor and becomes higher as the power supply voltage becomes lower, is supplied to the N-channel control transistor having a higher driving capability and the P-channel control transistor having a lower driving capability. A driving capability adjusting circuit for supplying the driving voltage to the gate terminal is provided, thereby achieving the above object.

Further, the output buffer circuit of the present invention has a P
A first control circuit for connecting a first output transistor comprising a channel and an N-channel FET in series between a power supply ground and connecting or grounding the gate terminals of these first output transistors to a power supply according to an input signal, respectively , A P-channel and an N-channel, each having a higher driving capability than the first output transistor.
A second control circuit for connecting a second output transistor comprising a channel FET in series between the power supply ground and connecting or grounding the gate terminal of each of the second output transistors to a power supply according to an input signal; A second output buffer circuit, and a delay circuit for delaying an input signal supplied to the first output buffer circuit and supplying the delayed output signal to the second output buffer circuit. Two N-channel FEs having different driving capacities are provided on a circuit in which the gate terminals of the two output transistors are grounded via the first control circuit and the second control circuit, respectively.
A circuit in which control transistors each including T are inserted in parallel, and gate terminals of the first output transistor and the second output transistor of the N channel are connected to a power supply via the first control circuit and the second control circuit, respectively. A control transistor composed of two P-channel FETs having different driving capabilities is inserted in parallel on the way, and continuously changes according to the level of the power supply voltage, and generates control signals complementary to each other. The control signal of the N-channel control transistor having a higher driving capability and the gate terminal of the P-channel control transistor having a lower driving capability in the first output buffer circuit; The N-channel control transistor having a lower driving capability and the N-channel control transistor having a higher driving capability in the second output buffer circuit. The other control signal, which is supplied to the gate terminal of the control transistor of the channel and becomes higher as the power supply voltage becomes lower, is supplied to the control transistor of the N-channel having the lower drive capability in the first output buffer circuit. A gate terminal of the higher P-channel control transistor, a gate terminal of the N-channel control transistor having a higher driving capability in the second output buffer circuit, and a gate terminal of the P-channel control transistor having a lower driving capability. A drive capacity adjusting circuit for supplying the power is provided, whereby the object is achieved.

Further, preferably, the delay circuit in the output buffer circuit of the present invention is capable of adjusting a delay time, and the one control signal which becomes higher as the power supply voltage in the drive capability adjusting circuit becomes higher becomes higher. The delay time of the input signal becomes longer as the voltage becomes higher.

Still preferably, in a drive capacity adjusting circuit in the output buffer circuit according to the present invention, the one control signal, which becomes higher as the power supply voltage becomes higher, is set to a higher voltage as the temperature becomes lower, and / or And the other control signal, which becomes higher as the power supply voltage becomes lower, becomes higher as the temperature becomes higher, and / or the threshold voltage of the FET becomes higher. The higher the voltage, the higher the voltage.

Still preferably, in a drive capacity adjusting circuit of the output buffer circuit according to the present invention, the first input voltage which becomes higher as the power supply voltage becomes higher, the first input voltage becomes higher as the temperature becomes higher, and / or the operation of the FET becomes higher. A second input voltage which becomes a higher voltage as the threshold voltage becomes higher, is inputted to a differential amplifier circuit, and complementary differential outputs of the differential amplifier circuit are outputted as control signals via respective current mirror circuits. It is.

Still preferably, in the output buffer circuit according to the present invention, the first bipolar transistor connected in the saturation region connected between the power supply grounds and the first bipolar transistor connected in the saturation region connected between the power supply grounds The transistor is composed of a series circuit of a second bipolar transistor having a different emitter area and a first passive element, and a series circuit of an FET shorted between a drain and a gate terminal connected between a power supply ground and a second passive element. They are connected to each other via a current mirror circuit, and supply the terminal voltage of a series circuit of the FET and the second passive element to the differential amplifier circuit as the second input voltage.

Still preferably, in the output buffer circuit according to the present invention, the FE having a short circuit between the drain and gate terminals is provided.
T is a series circuit or a parallel circuit of an N-channel FET and a P-channel FET in which the drain and gate terminals are short-circuited.

[0023]

The power supply and the ground in the present invention mean the power supply on the high voltage side and the power supply on the low voltage side supplied to the output buffer circuit, respectively, and the power supply voltage indicates the potential difference between these power supply grounds.

According to the first aspect of the present invention, the voltages at the control terminals of the two control transistors having different driving capacities are complementarily changed in accordance with the level of the power supply voltage. The power supply is gradually connected or gradually grounded to the control terminal of the output transistor by a low control transistor, and when the power supply voltage is low, the power supply is rapidly connected to the control terminal of the output transistor by a control transistor having a high driving capability or Can be grounded. Therefore, at the time of the high voltage of the power supply where the influence of the noise is large, the switching of the output transistor is slowed down to reduce this noise. It is possible to prevent the output of the circuit from increasing in speed. In addition, since the control signal of the drive capability adjusting circuit changes continuously, not stepwise, according to the level of the power supply voltage, optimal control can be performed according to the degree of the influence of noise.

The invention according to claim 2 shows a case where an output buffer circuit is constituted by an inverter circuit using an output transistor composed of an FET. The pair of output transistors is usually constituted by a CMOS FET. The driving capability of the transistor indicates the switching speed and the current driving capability. In the case of an FET, the driving capability increases as the mutual conductance gm increases. In the case of a MOS-FET, the mutual conductance g
Since m increases as the channel width W increases, the driving capability increases as the size of the transistor increases.

Also in this case, the higher the power supply voltage is, the more the conduction of the control transistor having a low driving ability is promoted and the conduction of the control transistor having a high driving ability is suppressed, so that the switching of the output transistor becomes slow. Further, as the power supply voltage is lower, the conduction of the control transistor having a higher driving ability is promoted, and the conduction of the control transistor having a lower driving ability is suppressed, so that the switching of the output transistor is quicker. Therefore, when the power supply voltage is high, noise can be reduced, and when the power supply voltage is low, the speed of the output buffer circuit can be increased.

The invention of claim 3 shows a case where an output buffer circuit is constituted by a first output buffer circuit and a second output buffer circuit having different driving capabilities of output transistors. In this case, the first output buffer circuit having the lower driving capability, as opposed to the output buffer circuit according to the second aspect, allows the first output transistor to be quickly switched at the time of the high power supply voltage and at the time of the low power supply voltage. The switching of the first output transistor is performed slowly. Further, the second output buffer circuit having the higher driving capability causes the switching of the second output transistor to be performed slowly at the time of the high power supply voltage and the second output buffer circuit at the time of the low power supply voltage, similarly to the output buffer circuit of the second aspect.
The switching of the output transistor is performed at high speed. In addition, the input signal to the second output buffer circuit having the higher driving capability is delayed by the delay circuit.

Therefore, in this case, the first output buffer circuit having a lower driving capability operates predominantly at a high power supply voltage, and the second output buffer circuit having a higher driving capability operates at a low power supply voltage. Therefore, the noise reduction effect of the output buffer circuit according to the second aspect can be further ensured.

The invention of claim 4 shows a case where the delay circuit of claim 3 shortens the delay time as the power supply voltage becomes lower. Therefore, in the case of the output buffer circuit according to the third aspect, even when the second output buffer circuit having the higher driving capability operates dominantly at the time of the low power supply voltage, the input signal is uniformly delayed by the delay circuit. However, in this case, the high-speed operation can be ensured by shortening the delay time of the delay circuit.

According to a fifth aspect of the present invention, the driving capability adjusting circuit comprises:
The case where the voltage of the control signal is changed in consideration of not only the level of the power supply voltage but also the level of the temperature and the threshold voltage of the FET will be described. When the operating environment or the temperature of the element is lowered, or when the threshold voltage of the FET is lowered due to a variation in the manufacturing process, the influence of noise increases as in the case where the power supply voltage becomes relatively high. Therefore, even when the power supply voltage does not change, when the temperature is lowered or the threshold voltage is low, the same control signal as when the power supply voltage is increased is output. Therefore, in this case, more accurate noise reduction and high-speed operation control can be performed in consideration of the temperature and the threshold voltage.

A sixth aspect of the present invention is directed to a case where the driving capability adjusting circuit according to the fifth aspect is constituted by a differential amplifier circuit and a current mirror circuit. In this case, the temperature is detected by the bandgap voltage of the bipolar transistor in this case. further,
Claim 8 sets the threshold voltage of the FET to N-channel F
The case where the threshold voltage is set to the lower threshold voltage of either or both of the ET and P-channel FETs will be described.

[0032]

Embodiments of the present invention will be described below.

1 to 7 show a first embodiment of the present invention. FIG. 1 is a circuit diagram of an output buffer circuit, and FIG. 2 is a diagram of a differential amplifier circuit for generating a control signal and its peripheral circuits. 3 is a circuit diagram of a reference voltage generating circuit, FIG. 4 is a circuit diagram of a threshold voltage circuit, FIG. 5 is a circuit diagram of another threshold voltage circuit, and FIG. FIG. 7 is a graph illustrating the relationship with the output reference voltage, and FIG. 7 is a graph illustrating the operation of the differential amplifier circuit. In the present embodiment, as shown in FIG.
An output buffer circuit using P-channel and N-channel output transistors Q1 and Q2 constituting a CMOS FET inverter circuit will be described. The P-channel output transistor Q1 has a source terminal connected to the power supply VCC, a drain terminal connected to the output terminal 1 of the output buffer circuit, and an N-channel output transistor Q2 having a source terminal grounded and a drain terminal connected to the output terminal. The terminals are connected to the same output terminal 1. The input signal is input to the gate terminal of the P-channel output transistor Q1 via the first control circuit 2, and is input to the N-channel output transistor Q2 via the second control circuit 3.
Input to the gate terminal.

The first control circuit 2 includes a transistor Q2
1 and a CMOS inverter circuit composed of Q22. However, N-channel transistor Q22
Is grounded via a parallel circuit of two N-channel control transistors Q23 and Q24. Further, the second control circuit 3 is constituted by a CMOS inverter circuit including transistors Q31 and Q32. However, the source terminal of the P-channel transistor Q31 is connected to two P-channel control transistors Q33 and Q34.
Are connected to a power supply VCC through a parallel circuit of These control transistors Q23, Q24, Q33, Q34 are formed such that one of the control transistors Q23, Q33 has a higher driving capability. For example, if only the channel width W of one of the control transistors Q23 and Q33 is made larger than the other control transistors Q24 and Q34 and the size is made larger under the same other conditions, the mutual conductance gm becomes larger. The driving capability of the transistors Q23 and Q33 can be increased. Further, the gate terminals of the control transistors Q23 and Q33 having the higher driving capability are connected to
The control signal B bar and the control signal A bar are input, respectively, and the control transistors Q24,
The control signal B and the control signal A, which are complementary to each other, are input to the gate terminal of Q34.

The control signals A and A and the control signals B and B
The bars indicate the differential outputs of the differential amplifier circuit 4 shown in FIG. 2 via the current mirror circuits. The differential amplifier circuit 4 includes N-channel transistors Q41 and Q41.
This is a DC amplifier circuit composed of a P.42 transistor, P-channel transistors Q43 and Q44, and a constant current circuit 4a. The amplifier amplifies the difference between the input voltages of the gate terminals of the N-channel transistors Q41 and Q42, and Output as control signals A and A which are complementary to each other. Note that the constant current circuit 4a may be constituted by, for example, a current mirror circuit or a circuit utilizing the constant current characteristics of the FET, or may be simply replaced by a high resistance.

A circuit in which a P-channel transistor Q45 and an N-channel transistor Q46 are connected in series between the power supply grounds, a P-channel transistor Q47 and an N-channel transistor Q48 and a circuit in series between the power supply ground. The drain terminal of the transistor Q41 that forms one output of the differential amplifier circuit 4 is connected to the gate terminal of the transistor Q43 and the gate terminal of the transistor Q45, and the transistor Q42 that forms the other output of the differential amplifier circuit 4 Is connected to the gate terminal of the transistor Q44 and the gate terminal of the transistor Q47. Therefore, transistor Q43 and transistor Q
45 and the transistor Q34 of the second control circuit 3 shown in FIG. 1 constitute a current mirror circuit, and the transistor Q44, the transistor Q47 and the transistor Q33 of the second control circuit 3 constitute a current mirror circuit. . The transistor Q46 has the drain-gate terminal short-circuited and outputs the control signal B therefrom. The transistor Q48 also has the drain-gate terminal short-circuited and outputs the control signal B bar therefrom. Therefore, the transistor Q46 and the transistor Q24 of the first control circuit 2 shown in FIG. 1 constitute a current mirror circuit, and the transistor Q48 and the first control circuit 2
Transistor Q23 forms a current mirror circuit.

The divided voltage Vo obtained by dividing the voltage of the power supply VCC by the resistors R1 and R2 is input to the gate terminal of the transistor Q41, which is one input of the differential amplifier circuit 4. Further, the reference voltage Vref from the reference voltage generation circuit 5 is input to the gate terminal of the transistor Q42, which is the other input of the differential amplifier circuit 4. The reference voltage generation circuit 5 is a circuit that outputs a reference voltage Vref that becomes higher as the temperature is higher and becomes higher as the threshold voltage Vth of the FET is higher.

As shown in FIG. 3, the reference voltage generating circuit 5 includes a P-channel transistor and an N-channel transistor Q5.
3, Q54 and a pnp type bipolar transistor Q51 are connected in series between the power supply ground and the P channel and N
Channel transistors Q55 and Q56, resistor R3 and pn
A p-type bipolar transistor Q52 is connected in series between the power supply grounds, and a P-channel transistor Q57, a resistor R4 and a threshold voltage circuit 6 are connected in series between the power supply grounds. The bases of the bipolar transistors Q51 and Q52 are short-circuited to the collectors and grounded. The gate terminal of the transistor Q54 is short-circuited to the drain terminal and connected to the gate terminal of the transistor Q56 to form a current mirror circuit. Further, the gate terminal of the transistor Q55 is short-circuited to the drain terminal and connected to the gate terminals of the transistor Q53 and the transistor Q57 to form a current mirror circuit.

As shown in FIG. 4, the threshold voltage circuit 6 includes N-channel and P-channel transistors Q61,
Q62 are connected in series by short-circuiting between the drain and gate terminals. Therefore, the transistors Q61 and Q61 are connected between the terminals of the threshold voltage circuit 6.
A voltage Vthn + Vthp of the sum of the threshold voltage Vthn and the threshold voltage Vthp of 62 is added. Although the threshold voltage of the FET varies depending on the manufacturing process even if the FET has the same design, if the voltage between the terminals of the threshold voltage circuit 6 is detected, other FETs manufactured by the same process Can be inferred.

The bipolar transistor Q52 in the reference voltage generating circuit 5 is formed so that only the emitter area is A times that of the bipolar transistor Q51 under the same other conditions. Here, assuming that a value determined by the carrier density or the like is K, the bandgap voltage VQ52 of the bipolar transistor Q52 can be expressed by the following equation (1).

[0041]

(Equation 1)

Then, the current mirror circuit shown in FIG.
And that the current I1 and the current I2 are equal to each other and that the emitter area of the bipolar transistor Q51 is 1 / A.
Since the carrier density is increased by the narrower, the band gap voltage V of the bipolar transistor Q51 is
Q51 can be represented by the following equation (2).

[0043]

(Equation 2)

Therefore, the terminal voltage ΔV of the resistor R3 becomes
The difference between these band gap voltages VQ51 and VQ52 is expressed by the following equation (3).

[0045]

(Equation 3)

Then, the current I2 becomes the following equation (4).

[0047]

(Equation 4)

Since the current I2 and the current I3 are also equal by the current mirror circuit, if the terminal voltage of the threshold voltage circuit 6 is Vthn + Vthp as described above, the reference voltage Vre
f is represented by the following equation (5).

[0049]

(Equation 5)

To have a positive temperature characteristic in which the reference voltage Vref becomes higher as the temperature becomes higher as described above, the value obtained by differentiating the reference with respect to the temperature should be positive. Then, when the reference voltage Vref of Expression 5 is differentiated by the absolute temperature T, the following Expression 6 is obtained.

[0051]

(Equation 6)

The threshold voltage of the FET has a negative temperature characteristic in which the higher the temperature, the lower the voltage. The value obtained by differentiating the threshold voltage with respect to the absolute temperature T is expressed by the following equation (7). So you can

[0053]

(Equation 7)

Equation (6) is rewritten as shown in the following equation (8), and if this is larger than zero, the reference voltage Vref has a positive temperature characteristic.

[0055]

(Equation 8)

As a result, the reference voltage Vref output from the reference voltage generation circuit 5 can be adjusted by appropriately adjusting the ratio A of the emitter areas of the resistors R3 and R4 and the bipolar transistors Q51 and Q52 as shown in Expression 8. As shown in FIG. 6, it can be set so as to have a positive temperature characteristic in which the higher the absolute temperature T, the higher the voltage. Moreover, the reference voltage Vref itself is equal to the terminal voltage Vthn + of the threshold voltage circuit 6 indicating the threshold voltage of the FET, as shown in Expression 5.
It also depends on Vthp, and the higher the threshold voltage, the higher the voltage.

In this embodiment, the threshold voltage circuit 6
Is constituted by a series circuit of transistors Q61 and Q62 as shown in FIG. 4, and the sum of these threshold voltages is output as a terminal voltage Vthn + Vthp. However, the threshold voltage circuit 6 can be configured by connecting these transistors Q61 and Q62 in parallel as shown in FIG. 5, for example. In this case, since the transistors Q61 and Q62 with the higher threshold voltage are cut off, only the lower one of the threshold voltages Vthn and Vthp becomes the terminal voltage of the threshold voltage circuit 6. In this case, the condition for the reference voltage Vref of the reference voltage generating circuit 5 to have a positive temperature characteristic is as shown in the following equation (9).

[0058]

(Equation 9)

The operation of the output buffer circuit having the above configuration will be described.

In the differential amplifier circuit 4 shown in FIG. 2, the constant current flowing through the constant current circuit 4a is I0, and the transistors Q41 and Q4
Assuming that currents flowing through 2 are I4 and I5, respectively, a relationship of I0 = I4 + I5 is established. Assuming that the reference voltage Vref of the reference voltage generation circuit 5 is constant, when the divided voltage Vo obtained by dividing the voltage of the power supply VCC by the resistors R1 and R2 changes around the reference voltage Vref,
As shown by the thick solid line in FIG. 7, the currents I4 and I5 change complementarily from zero to the magnitude of the current I0.

Therefore, for example, when the voltage of the power supply VCC becomes higher and the divided voltage Vo becomes higher than the reference voltage Vref, the current I4 increases, and accordingly, the current of the transistor Q45 connected by the current mirror circuit is increased. I6 is also increased. Then, the control signal A, which is the gate voltage, becomes low and the control signal B becomes high, so that the control transistors Q24 and Q34 of the control circuits 2 and 3 shown in FIG. Promoted. At this time, the current I5 of the differential amplifier circuit 4 decreases, and accordingly, the current I7 of the transistor Q47 connected by the current mirror circuit also decreases. Then, the control signal A bar, which is the gate voltage, becomes high voltage and the control signal B bar becomes low voltage, and the conduction of the control transistors Q23 and Q33 having higher driving capability in the control circuits 2 and 3 is suppressed. .

Conversely, when the voltage of the power supply VCC decreases and the divided voltage Vo becomes lower than the reference voltage Vref, the current I4
And the current I6 decreases, the control signal A becomes high voltage and the control signal B becomes low voltage, and the conduction of the control transistors Q24 and Q34 of the control circuits 2 and 3, which have lower driving ability, is suppressed. Also, at this time, the current I5 and the current I7 of the differential amplifier circuit 4 increase, so that the control signal A bar becomes low voltage and the control signal B bar becomes high voltage. The higher control transistor Q
23, Q33 conduction is promoted.

As a result, as the voltage of the power supply VCC increases, the control circuits 2 and 3 slow down the switching of the output transistors Q1 and Q2 by the control transistors Q24 and Q34 having a low driving ability. Noise can be reduced. Conversely, when the voltage of the power supply VCC decreases, the control circuits 2 and 3 cause the control transistors Q23 and Q33 having a high driving capability to quickly switch the output transistors Q1 and Q2. Therefore, in the output buffer circuit of this embodiment, when the voltage of the power supply VCC increases and the influence of noise increases, the noise at the time of switching of the output transistors Q1 and Q2 decreases, and the voltage of the power supply VCC decreases and the influence of the noise decreases. Is smaller, the output transistors Q1 and Q2 can be switched at high speed. Moreover, this output transistor Q
1, Q2 are continuously controlled according to the fluctuation of the voltage of the power supply VCC.

Further, when the temperature decreases or the threshold voltage of the FET decreases, the influence of noise increases. When the temperature decreases or the threshold voltage of the FET decreases, the reference voltage Vref output from the reference voltage generating circuit 5 also decreases.
4. The curve of I5 changes in the direction of arrow A. That is, when the reference voltage Vref decreases in this way, the current I4 increases and the current I5 decreases, as in the case where the voltage of the power supply VCC becomes high, even if the divided voltage Vo is constant. . Conversely, when the temperature or the threshold voltage rises, the reference voltage Vref also rises, so that the curves of the currents I4 and I5 shift in the direction of arrow B, and even if the divided voltage Vo is constant, the power supply VC becomes constant.
As in the case where the voltage of C becomes low, the current I4 decreases and the current I5 increases.

Therefore, the output buffer circuit according to the present embodiment is designed such that, for example, even if the voltage of the power supply VCC is as specified, if the influence of noise increases due to an increase in temperature or threshold voltage, the output transistor Q1 , Q2 at the time of switching can be reduced. Further, for example, even when the voltage of the power supply VCC is somewhat high, if the influence of noise is small because the temperature and the threshold voltage are low, the output transistors Q1 and Q2 can be switched at high speed.

8 to 10 show a second embodiment of the present invention. FIG. 8 is a circuit diagram of an output buffer circuit, FIG. 9 is a circuit diagram of one delay circuit, and FIG. It is a circuit diagram of a circuit. Components having the same functions as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

In this embodiment, as shown in FIG. 8, a case where the CMOS inverter circuit forming the output buffer circuit is divided into two will be described. The output transistors Q1 and Q2 constituting one CMOS inverter circuit, and the first control circuit 2 and the second control circuit 3 have the same configuration as in the first embodiment. Also, the control signals A and A and the control signals B and B are generated by the same circuit as in the first embodiment. However, the input signal is input to the first control circuit 2 via the inverter circuit 11 and the delay circuit 9 and is input to the second control circuit 3 via the inverter circuit 12 and the delay circuit 10. I have.

The P-channel output transistor Q3 constituting the other CMOS inverter circuit has a source terminal connected to the power supply VCC, a drain terminal connected to the output terminal 1 of the output buffer circuit, and an N-channel output transistor Q4. Has a source terminal grounded and a drain terminal connected to the same output terminal 1.
The output transistors Q3 and Q4 are formed so that their driving capabilities are lower than those of the output transistors Q1 and Q2 of one CMOS inverter circuit.
The input signal is input to the gate terminal of the output transistor Q3 via the inverter circuit 11 and the third control circuit 7, and is input to the gate terminal of the output transistor Q4 via the inverter circuit 12 and the fourth control circuit 8. It has become. The third control circuit 7 includes a transistor Q
It comprises a CMOS inverter circuit consisting of 71 and Q72, and a parallel circuit of two N-channel control transistors Q73 and Q74 connected to the source terminal of the N-channel transistor Q72. The driving capability of the control transistor Q73 is controlled by the control transistor Q74. It is the same as the first control circuit 2 in that it is formed higher than the first control circuit 2. Further, the fourth control circuit 8 includes:
A CMOS inverter circuit including transistors Q81 and Q82, and two P-channel control transistors Q8 connected to the source terminals of P-channel transistor Q81.
3, a parallel circuit of Q84 and a control transistor Q83
This is the same as the second control circuit 3 in that the drive capability of the second control circuit 3 is made higher than that of the control transistor Q84. However,
Contrary to these control circuits 2 and 3, the control signals B and A are input to the gate terminals of the control transistors Q73 and Q83 having the higher driving capability, respectively, and the control terminals having the lower driving capability are controlled. The control signals B and A are input to the gate terminals of the transistors Q74 and Q84, respectively.

As shown in FIG. 9, the delay circuit 9 has a CMOS inverter circuit 9 having the same configuration as that of the second control circuit 3.
a, 9c and a CMOS inverter circuit 9b having the same configuration as the first control circuit 2 are connected in series. Also,
The delay circuit 10, as shown in FIG.
CMOS inverter circuits 10a and 10c having the same configuration as the above and CMOS inverter circuit 1 having the same configuration as the second control circuit 3
0b are connected in series. Therefore, these delay circuits 9 and 10 are connected to CMOS inverter circuits 9a to 9c or CMOS inverter circuit 1 connected in three stages.
The input signal is delayed and output by integrating the respective delay times of 0a to 10c. The delay time can be continuously expanded and contracted by the control signals A and A and the control signals B and B. Note that each delay circuit 9,
10, the number of connection stages of the CMOS inverter circuits 9a to 9c or the CMOS inverter circuits 10a to 10c is as follows.
It can be changed appropriately according to a desired delay time.

The output transistors Q1 and Q2 constituting one of the CMOS inverter circuits in the output buffer circuit of the present embodiment having the above configuration, and the first control circuit 2 and the second control circuit 3 thereof are the output transistors of the first embodiment. Performs the same operation as the buffer circuit. That is, as the control signal B becomes higher in voltage and the control signal A becomes lower in voltage, the output transistors Q1,
As the switching of Q2 becomes slower and the control signal B becomes higher and the control signal A becomes lower, the switching of the output transistors Q1 and Q2 becomes faster. Also,
The output transistors Q3 and Q4 constituting the other CMOS inverter circuit and the third and fourth control circuits 7 and 8 have the opposite inputs of the control signals A and A and the control signals B and B. An operation reverse to that of the output buffer circuit of the first embodiment is performed. That is, as the control signal B becomes higher and the control signal A becomes lower, the switching of the output transistors Q1 and Q2 becomes faster, and as the control signal B becomes higher and the control signal A becomes lower, the output transistors Q1 and Q2 become lower. Switching becomes slow.

The delay circuits 9 and 10 are composed of CMOS inverter circuits 9a to 9c having the same configuration as the control circuits 2 and 3, and CMOS
As the control signal B becomes high voltage and the control signal A becomes low voltage, the delay time becomes longer. Since the control signal B becomes high voltage and the control signal A becomes low voltage, the delay time becomes longer. Be shorter.

As a result, in the output buffer circuit of the present embodiment, as the voltage of the power supply VCC increases, and / or
As the temperature decreases and the threshold voltage of the FET decreases, the control signal B becomes higher and the control signal A becomes lower. Therefore, the switching of the output transistors Q1 and Q2 constituting one of the CMOS inverter circuits is performed slowly. At the same time, the switching of the output transistors Q3 and Q4 constituting the other CMOS inverter circuit is performed quickly, and the delay time of the delay circuits 9 and 10 is lengthened. Therefore, the output buffer circuit, when the condition of the influence of the noise becomes large, firstly, the output transistors Q3,
Since the transistor Q4 operates quickly and the output transistors Q1 and Q2 having high driving capability operate slowly after the long delay time of the delay circuits 9 and 10, the noise generated at the time of this switching can be surely reduced. . Conversely, as the voltage of the power supply VCC decreases and / or as the temperature increases and the threshold voltage of the FET increases, the control signal B becomes higher and the control signal A becomes lower. The switching of the output transistors Q1 and Q2 constituting one CMOS inverter circuit is quickly performed, and the switching of the output transistors Q3 and Q4 constituting the other CMOS inverter circuit is slowed down. Shorten. Therefore, when the effect of noise is reduced, the output buffer circuit quickly operates after the short delay time of the delay circuits 9 and 10 because the output transistors Q1 and Q2 having high driving capability operate quickly. No damage is done.

[0073]

As described above, according to the present invention, the switching of the output transistor is slowed down at the time of a high power supply voltage at which the influence of noise is large, and this noise is reduced. Sometimes, the high-speed operation of the output transistor can be prevented. In addition, since the control of the output transistor is continuously changed according to the level of the power supply voltage, optimal control can be performed according to the degree of the influence of noise. Further, since the output transistor can be controlled in consideration of the temperature and the threshold voltage of the FET as well as the level of the power supply voltage, it is possible to perform accurate control in accordance with the degree of the influence of actual noise. .

[Brief description of the drawings]

FIG. 1, showing a first embodiment of the present invention, is a circuit diagram of an output buffer circuit.

FIG. 2, showing a first embodiment of the present invention, is a circuit diagram of a differential amplifier circuit for generating a control signal and peripheral circuits thereof.

FIG. 3, showing the first embodiment of the present invention, is a circuit diagram of a reference voltage generating circuit.

FIG. 4 shows a first embodiment of the present invention and is a circuit diagram of a threshold voltage circuit.

FIG. 5 is a circuit diagram of another threshold voltage circuit according to the first embodiment of the present invention.

FIG. 6 is a graph showing a first embodiment of the present invention and showing a relationship between a temperature and a reference voltage output from a reference voltage generation circuit.

FIG. 7 is a graph illustrating the operation of the differential amplifier circuit according to the first embodiment of the present invention.

FIG. 8 illustrates a second embodiment of the present invention, and is a circuit diagram of an output buffer circuit.

FIG. 9 shows a second embodiment of the present invention, and is a circuit diagram of one delay circuit.

FIG. 10 shows a second embodiment of the present invention, and is a circuit diagram of another delay circuit.

FIG. 11 shows a first conventional example, and is a circuit diagram of an output buffer circuit.

FIG. 12 shows a second conventional example and is a circuit diagram of an output buffer circuit.

FIG. 13 shows a third conventional example, and is a circuit diagram of an output buffer circuit.

FIG. 14 shows a fourth conventional example, and is a circuit diagram of an output buffer circuit.

FIG. 15 shows a fourth conventional example and is a circuit diagram of a power supply voltage control signal generation circuit.

FIG. 16 is a graph showing a fourth conventional example and showing a relationship between a power supply voltage and a power supply voltage control signal.

[Explanation of symbols]

 2 First control circuit 3 Second control circuit 4 Differential amplifier circuit 5 Reference voltage generation circuit 6 Threshold voltage circuit 7 Third control circuit 8 Fourth control circuit 9 Delay circuit 10 Delay circuit Q1 output transistor Q2 output transistor Q3 output Transistor Q4 Output transistor Q23 Control transistor Q24 Control transistor Q33 Control transistor Q34 Control transistor Q51 Bipolar transistor Q52 Bipolar transistor Q61 transistor Q62 transistor

Claims (8)

(57) [Claims] 1. A circuit in which a control terminal of an output transistor is connected to a power supply or grounded, two control transistors having different driving capacities are inserted in parallel, and the control transistors change continuously according to the level of a power supply voltage. And an output buffer circuit provided with a drivability adjusting circuit for generating mutually complementary control signals and supplying these complementary control signals to the control terminals of the control transistor. 2. A control circuit for connecting output transistors comprising P-channel and N-channel FETs in series between a power supply ground and connecting or grounding the gate terminals of these output transistors to a power supply in accordance with an input signal. In the output buffer circuit comprising: a control transistor consisting of two N-channel FETs having different driving capacities is inserted in parallel on a circuit in which the gate terminal of the P-channel output transistor is grounded via the control circuit; A control transistor composed of two P-channel FETs having different driving capacities is inserted in parallel on the circuit connecting the gate terminal of the N-channel output transistor to the power supply through the control circuit, and is continuously connected according to the level of the power supply voltage. And control signals that are complementary to each other. The one control signal, which becomes a very high voltage, is supplied to the gate terminals of the N-channel control transistor having the lower driving capability and the P-channel control transistor having the higher driving capability, and the lower the power supply voltage is, An output provided with a drive capacity adjustment circuit for supplying the other control signal of a high voltage to the gate terminals of the N-channel control transistor having a higher drive capacity and the P-channel control transistor having a lower drive capacity; Buffer circuit. 3. A first output transistor comprising P-channel and N-channel FETs is connected in series between a power supply ground and a gate terminal of each of the first output transistors is connected to a power supply according to an input signal. A first output buffer circuit having a first control circuit to be grounded, and a second output transistor comprising a P-channel and an N-channel FET each having a higher driving capability than the first output transistor are connected in series between the power supply ground. With
A second terminal connected to a power source or grounded in accordance with an input signal is connected to a gate terminal of each of the second output transistors.
A second output buffer circuit having a control circuit; and a delay circuit for delaying an input signal supplied to the first output buffer circuit and supplying the delayed input signal to the second output buffer circuit. The gate terminals of the output transistor and the second output transistor are connected to the first control circuit and the second
A control transistor consisting of two N-channel FETs having different driving capacities is inserted in parallel on a circuit grounded through the control circuit, and gate terminals of the first output transistor and the second output transistor of the N-channel. Respectively with the first control circuit and the second control circuit.
A control transistor composed of two P-channel FETs having different driving capabilities is inserted in parallel on the circuit connected to the power supply via the control circuit, and changes continuously according to the level of the power supply voltage and complements each other. One of the N-channel control transistors having the higher driving capability in the first output buffer circuit and the N-channel control transistor having the lower driving capability in the first output buffer circuit. Supplying the gate terminal of a P-channel control transistor, the gate terminal of the N-channel control transistor having a lower driving capability in the second output buffer circuit and the gate terminal of the P-channel control transistor having a higher driving capability, The other control signal, which becomes higher in voltage as the power supply voltage becomes lower, is supplied to the N of the first output buffer circuit having the lower drive capability. A gate terminal of the P-channel control transistor having a higher driving capability and the P-channel control transistor having a higher driving capability in the second output buffer circuit; An output buffer circuit provided with a drive capacity adjusting circuit for supplying a gate terminal of a channel control transistor. 4. The delay circuit is capable of adjusting a delay time, and the higher the power supply voltage in the drive capability adjustment circuit is, the higher the voltage is. The higher the one control signal is, the higher the delay of the input signal is. 4. The output buffer circuit according to claim 3, wherein the time becomes longer. 5. The driving capability adjusting circuit according to claim 1, wherein the one of the control signals, which has a higher voltage as the power supply voltage is higher, has a higher voltage as the temperature is lower, and / or has a lower threshold voltage of the FET. The other control signal having a higher voltage and a higher voltage as the power supply voltage is lower is generated as a higher voltage as the temperature is higher and / or as a higher voltage as the threshold voltage of the FET is higher. Item 5. The output buffer circuit according to any one of Items 1 to 4. 6. The driving capability adjusting circuit according to claim 1, wherein the first input voltage becomes higher as the power supply voltage becomes higher, and the first input voltage becomes higher as the temperature becomes higher, and / or becomes higher as the threshold voltage of the FET becomes higher. 6. The output buffer circuit according to claim 5, wherein the second input voltage is input to a differential amplifier circuit, and complementary differential outputs of the differential amplifier circuit are output as control signals via current mirror circuits. 7. A first bipolar transistor which is conductive in a saturation region connected between power supply grounds, and a second bipolar transistor which is conductive in a saturation region connected between power supply grounds and has an emitter area different from that of the first bipolar transistor. And a series circuit of a first passive element and a series circuit of an FET connected between a power supply ground and a short-circuited drain-gate terminal and a second passive element via a current mirror circuit. 7. The output buffer circuit according to claim 6, wherein a terminal voltage of a series circuit of said FET and a second passive element is supplied to said differential amplifier circuit as said second input voltage. 8. The output buffer circuit according to claim 7, wherein the FET having a short-circuit between the drain and gate terminals is a series circuit or a parallel circuit of an N-channel FET and a P-channel FET having a short-circuit between the drain and gate terminals. .