JP3072435B2 - Digital convergence device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence apparatus for correcting a color shift of a multi-scan type projection display.

[0002]

2. Description of the Related Art Conventionally, an input synchronizing signal frequency range is set in a memory in advance, and if an input signal is within the set range, correction data is read from the memory to perform convergence correction. FIG. 6 shows a block diagram of a conventional digital convergence device for correcting a color shift of a projection display. In FIG.
31 is a control device (CPU), 32 is a read-only memory (ROM) for storing programs, 33 is a temporary memory (RAM), and 34 is a correction data memory, the contents of which are retained even when the power is turned off. A data changeable memory, 35 is a part for converting a synchronization signal for distinguishing an input signal, an aspect ratio, etc. into parallel data so that it can be processed by software, and a coefficient ROM and a pattern ROM according to the synchronization signal.
Is an interface (I / F) having a portion for generating an address for reading out the data. 36 is an interpolation operation unit,
Since the correction data memory 34 has only data of a specific point, an interpolation operation is performed using the correction data and coefficients. 37 is the coefficient RO
M and 38 are pattern ROMs, and 39 is a D / A converter. FIG. 7 shows a flow of processing of the above-mentioned conventional example. Next, the operation of the above conventional example will be described. In FIG. 6, it is determined by the program in the ROM 32 whether or not the synchronization signal frequency of the input signal input to the I / F 35 is within a preset range ( _S61 ). As a result, the correction data corresponding to the determination range is read from the correction data memory 34, and the coefficient data corresponding to the synchronization signal frequency is simultaneously stored in the coefficient RO.
From M37, the pattern data is read from the pattern ROM 38, and the pattern data is output ( _S62 ). The correction data read from the correction data memory 34 and the coefficient ROM 37
The coefficient data read from the
( _S63 ), the result of the interpolation calculation is output as corrected data after conversion by the D / A converter 39 ( _S64 ). If not in the range where the input signal is preset by the signal determination (S _61), as long as shift convergence, it performed again adjusted by interactively remake the correction data correction data memory 34
Perform a rewrite of (S ₇₁ ~S _74).

[0003]

However, in the above conventional example, when a signal input outside the range set by the program is present, there is a problem that the signal is outside the determination range and cannot be corrected. As shown in FIG. 8A, when there are a plurality of signal inputs (A, B, and C in FIG. 8) in one determination range, the correction data 2 corresponding to the synchronization signal frequency A is stored in the determination range 2. When the synchronization signal frequency B and the synchronization signal frequency C are newly input, the correction data 2 of the synchronization signal frequency A is read and the convergence correction is performed. However, signal A,
If the synchronization signal frequencies and amplitudes of B and C are different, if the correction of the signal C is performed using the correction data of the signal A, there is a problem that a convergence shift occurs as shown in FIG. The data that needs convergence correction is the raster data on the CRT screen.
It is determined by the spatial positional relationship of (R, G, B). For this reason, a difference in the synchronization signal frequency or amplitude results in a difference in the correction position, causing a convergence deviation. SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a digital convergence apparatus for providing an optimum convergence correction state.

[0004]

In order to achieve the above object of the present invention, if the type of the signal or the type of the discrimination signal is changed without setting the type of the signal or the determination range in advance by a program,
The convergence correction is performed by calculating a correction signal by calculation each time.

[0005]

According to the invention thus, when the installation adjustment, signal type with correction data (synchronization signal frequency, aspect ratio, etc.), stores the storage head address or the like of the correction data, during operation, the input signal In addition, the storage of the type of the signal in the memory is checked, a determination range is provided in consideration of the signal variation, and correction data within the range is read. Corresponding to the input signal
If the data does not exist in the memory, the coefficient data and pattern data corresponding to the input signal are obtained by calculation from the synchronization signal frequency and the number of scanning lines, and are sequentially changed each time the type of the input signal changes. In this way, convergence correction is performed digitally on an arbitrary input signal.

[0006]

FIG. 1 is a block diagram showing a digital convergence apparatus according to first and second embodiments of the present invention. In FIG. 1, reference numeral 1 denotes a control device (CP
U), 2 is a ROM for storing programs, 3 is a RAM,
Reference numeral 4 denotes a correction data memory, which comprises a signal type and correction data, and the signal type comprises a synchronization signal frequency, an aspect ratio, and a correction data storage start address. Reference numeral 5 denotes an interface (I / F), 6 denotes an interpolation operation unit for performing an interpolation operation using correction data and coefficients, 7 denotes a coefficient memory, 8 denotes a pattern memory, and 9 denotes a pattern memory.
Is a D / A converter. FIG. 2 shows a processing flow of the first embodiment of the present invention. Next, the operation of the first embodiment will be described. The CPU 1 determines whether or not the input signal from the interface 5 is stored in the signal type on the correction data memory 4 within a range in which the fluctuation of the signal is considered (S ₁ ). As a result, if I is stored in the correction data memory 4, and outputs the correction data corresponding to the signal selected from the correction data memory 4 to the interpolation operation unit 6 (S _2). At the same time, coefficient data and pattern data corresponding to the signal are calculated by the CPU 1 and stored in the coefficient memory 7 and the pattern memory 8. Further, the data of the coefficient memory 7 and the data of the pattern memory 8 are output in synchronization with the input signal, and the output of the coefficient memory 7 and the output of the correction data memory 4 are subjected to an interpolation operation by the interpolation operation unit 6 (S ₄ ). The result is converted by the D / A converter 9 to output a correction signal. If there is no data corresponding to the input signal in the correction data memory (in the adjustment mode) (S ₁₁ ), the CPU 1 calculates coefficient data and pattern data according to the input signal, and calculates the coefficient memory 7 and the pattern memory 8. (S
₁₂ ). Also, make the correction data of the adjusting points interactively for convergence adjustment (S _13), to store the signal type and the correction data in the correction data memory _{4 (S 14, S 15)} , on that, the correction data, coefficient An interpolation operation is performed by the data and interpolation operation unit 6, and a correction signal is output from the D / A converter 9.

Next, a second embodiment of the present invention will be described. Although the block configuration of the digital convergence device in the second embodiment is the same as that of FIG. 1, the coefficient memory 7 and the pattern memory 8 are electrically stored in the data storage mode even when the power is turned off, similarly to the correction data memory 4. Erasable memory (eg, E ² PROM, NVRA
M, battery backup RAM). FIG. 3 shows a flow of processing according to the second embodiment of the present invention.
Next, the operation of the second embodiment will be described. CP
U1 is interface 5 based on the program in ROM2.
More of the signal input, with reference to the signal type from the correction data memory (S _21), from the correction data memory 4 a correction data corresponding thereto, also from the coefficient memory 7 the coefficient data further reads the pattern data from the pattern memory
(S _22), performs interpolation calculation of the correction data and the coefficient data by the interpolation operation unit 6 (S _23), after converting the interpolation operation results in D / A converter 9, and outputs the corrected data. The result of reading from the pattern memory 8 is output as pattern data. When there is no data in the correction data memory 4 when the input signal is determined (S ₂₁ ), if there is an input signal, the operation starts to generate correction data. That is, in the adjustment mode (S ₃₁ ), the CPU
1 calculates and outputs correction data and coefficient data according to the input signal ( _S32 ), and stores the signal type, correction data, coefficient data, and pattern data in the correction data memory 4 ( _S33 ,
_S34 , _S35 ).

Next, a third embodiment of the present invention will be described. FIG. 4 is a block diagram showing a digital convergence apparatus according to a third embodiment of the present invention. In FIG. 4, 11 is a control device (CPU), 12 is a ROM for storing a program, 13 is a RAM, 14 is a correction data memory, 15 is an interface (I / F), and 16 is a frame memory, The contents of this memory are used for the operation of. 17 is a pattern memory, and 18 is a D / A converter. FIG. 5 shows a flow of processing in the third embodiment of the present invention. Next, the operation of the third embodiment will be described. When all the information of the display is operated using the frame memory 16, the interpolation calculation unit and the coefficient memory are not required to store all the information. CPU1 is RO
According to the program of M2, the correction data memory 14 is read by the input signal of the interface 5 to determine the signal.
( _S41 ) If there is data in the correction data memory 14, pattern data corresponding to the input signal is output from the pattern memory 17 ( _S42 ), and correction data corresponding to the input signal is output from the frame memory 16. and (S _43), after converting the output of the frame memory 16 by the D / a converter 18, the correction signal, and outputs the pattern data (S _44). If there is no data in the correction data memory 14 at the time of signal discrimination, an adjustment mode process ( _S51 ) is performed, and
The pattern data corresponding to the input signal is output from the pattern memory 17 ( _S52 ), and the coefficient data corresponding to the input signal is output to the CPU.
Determined by calculation in 1 (S _53), and a correction data of a pattern intersection (adjustment point) at convergence adjustment interactive,
Interpolation operation is performed on the correction data and coefficient data, and the frame memory 16
The output of the frame memory 16 is converted by the D / A converter and output ( _S54 ), and the signal type and all data of the frame memory 16 are stored in the correction data memory ( _S55 ,
_S56 ).

[0009]

The present invention exhibits As apparent from the above examples, during installation adjustment, signal type with correction data (synchronization signal frequency, aspect ratio, etc.), are stored and storing the start address of the correction data, in operation Examines the location where the type of signal is stored in correspondence with the input signal, sets a determination range in consideration of signal fluctuation, and reads out correction data within the range. Also,
If there is no data corresponding to the input signal in the memory,
The coefficient data and pattern data corresponding to the signal are obtained by calculation from the synchronization signal frequency and the number of scanning lines, and are sequentially changed each time the type of input signal changes. As above,
There is an effect that convergence correction can be digitally performed on an arbitrary input signal.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital convergence device according to first and second embodiments of the present invention.

FIG. 2 is a processing flowchart of the first embodiment of the present invention.

FIG. 3 is a processing flowchart of a second embodiment of the present invention.

FIG. 4 is a block diagram of a digital convergence device according to a third embodiment of the present invention.

FIG. 5 is a processing flowchart of a third embodiment of the present invention.

FIG. 6 is a block diagram of a conventional digital convergence device.

FIG. 7 is a processing flowchart of a conventional example.

FIG. 8 is a diagram illustrating a problem in a conventional example.

[Explanation of symbols]

1, 11, 31 ... CPU, 2, 12, 32 ... ROM, 3, 1
3,33… RAM, 4,14,34… Correction data memory,
5, 15, 35 ... I / F, 6, 36 ... interpolation operation unit, 7 ... coefficient memory, 8, 17 ... pattern memory, 9, 18, 39 ...
D / A converter, 16 ... frame memory, 37 ... coefficient ROM, 38 ... pattern ROM.

Claims (6)

(57) [Claims] 1. Spatial position and input of raster on CRT screen
The relationship set by the signal synchronization signal frequency and the number of scanning lines
Change the input signal type for numerical data and pattern data
The spatial position of the raster on the CRT screen
A control unit having a determining function in accordance with the <br/> Rutotomoni program to set the coefficient data and the pattern data corresponding to the operation to input <br/> force signal by the synchronizing signal frequency and the number of scanning lines of the force signal, A pattern data memory for storing pattern data according to the input signal, and a coefficient data memory for storing coefficient data according to a synchronization signal of the input signal,
A correction data memory in which a signal type and correction data are stored, and the control unit determines whether the input signal is included in the signal type stored in the correction data memory in a range in which signal fluctuation is considered. Program means for interpolating coefficient data output from the coefficient data memory and correction data output from the correction data memory to output a correction signal. When the control unit calculates a correction signal corresponding to the input signal without setting the determination range or the determination range, and the control unit determines that the data corresponding to the input signal is not stored in the correction data memory. In the above, coefficient data and pattern data corresponding to the input signal are calculated by the control means, and the coefficient data memory and the pattern data are calculated. Stores the data memory, said by the coefficient data and the pattern data by the interpolation calculation means
Correction data between adjustment points stored in the correction data memory
Digital convergence apparatus characterized by realizing an optimum convergence correction state by the interpolation calculation and outputs a correction signal. 2. The method according to claim 1, wherein the data of the signal type is stored in the correction data memory.
Synchronization signal frequency, aspect ratio, stores the number of scanning lines and notes <br/> Li storage starting address, the correction data at the time of signal input
Of the signal type stored in the data memory and the input signal
And the input signal is stored in the correction data memory.
Digital convergence apparatus according to claim 1, wherein the determining whether included in the signal type that is. 3. The correction data memory stores signal type data.
The synchronization signal frequency, aspect ratio, number of scanning lines and notes
Stores the re storage head address, considering the signal variation of the time signal input, the synchronization signal frequency, provides certain identification range to the aspect ratio, the signal type of the synchronization signals stored in said correction data memory within that range checks whether the frequency and aspect ratio is on, the digital convergence apparatus according to claim 1, wherein the allocating the correction data memory than the correction data long as within the range. In the case where 4. A co Nbajen scan tone obtained from interpolation calculation from the correction data of adjustment points correction data convergence adjustment of each scan line between Seiten, for each scan line between adjustment points for the interpolation operation the number of scanning lines which is obtained from the input sync signal frequency interpolation coefficients using vertical adjustment points, the digital convergence apparatus according to claim 1, wherein the determination by calculating interpolation coefficients corresponding to the input signal. 5. The optimum adjustment point position information against the input signal (pattern data), the synchronization signal frequency of the input signal and
Digital convergence apparatus according to claim 1, wherein the determination by calculation based on the aspect ratio. 6. The digital claim 1, wherein the storing setting compensation data in the memory and the signal type stored with another signal type to clear the compensation correction data into the correction data memory Convergence device.