JP3071515B2 - Field effect transistor and method of operating the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method for operating the same.

[0002]

2. Description of the Related Art A field effect transistor is widely used as a single unit or as an individual semiconductor element for forming a semiconductor integrated circuit.

The most common type of such a field-effect transistor is described in, for example, a document (“Ultra-high-speed MOS device”).
Baifukan (Showa 61) pp. 6 to 12). Hereinafter, the structure and operation of the conventional MOSFET will be described with reference to FIG. Here, FIG. 6 is a cross-sectional view schematically showing a conventional MOSFET cut along the channel length direction.

[0004] This MOSFET has a silicon substrate 11
A field oxide film 13 for element isolation formed on a predetermined portion of the substrate 11, an active region 15 surrounded by the field oxide film 13, and a gate insulating film formed on a predetermined portion of the active region 15. Membrane 17
And the gate electrode 1 formed on the gate insulating film 17.
9 and diffusion layers 21 serving as source / drain regions respectively formed in active region portions on both sides of the gate electrode 19.
It is configured to include: And the gate electrode 1
9, an intermediate insulating film 2 on a substrate 11 having a diffusion layer 21 and the like.
3 is provided, and for example, an aluminum wiring 27 is connected to the diffusion layer 21 through a contact hole 25 provided in a portion of the intermediate insulating film 23 corresponding to the diffusion layer 21.

In this MOSFET, when the MOSFET is of an N-channel type, one diffusion layer 21 (diffusion layer serving as a source region) is set to a ground level potential and the other diffusion layer 21 (drain region) is set to a ground level. Diffusion layer)
Is electrically connected to a high-level potential, and when the potential of the gate electrode 19 is set to a potential equal to or higher than the threshold voltage _Vth , a channel is formed on the surface of the substrate portion under the gate electrode 19, and the current flows. It flows from the drain region to the source region.

In order to achieve high integration and miniaturization of a semiconductor integrated circuit, miniaturization of a field effect transistor is very important.

[0007]

However, when the size of a field effect transistor is reduced, the gate length is shortened according to the principle of the proportional reduction rule, so that the electric field in the gate length direction becomes strong. There was a problem that occurs.

Further, when the gate length is shortened, the driving capability of the field effect transistor increases, but there is a problem that a so-called short channel effect occurs in which a leak current increases when the potential of the gate electrode is lower than a threshold value. there were.

[0009] The present application has been made in view of the above points, and it is therefore an object of the present application to provide a field effect transistor in which the above-mentioned problems associated with miniaturization are less likely to occur than in the past, and an operation for effectively using the field effect transistor. And to provide a method.

[0010]

According to a first aspect of the present invention, there is provided a field effect transistor having a window for exposing a substrate portion corresponding to an active region of a transistor. The first insulating film,
And a groove whose longitudinal direction is substantially perpendicular to the channel length direction of the field effect transistor and whose length is substantially the same as the channel width of the field effect transistor. A plurality of grooves are provided side by side along the above-described channel length direction, and a second insulating film is provided on each of the inner walls of the plurality of grooves and the surface of the substrate portion corresponding to the active region. A first gate electrode is provided in each of the plurality of trenches, a third insulating film is provided on the first gate electrode, and a second insulating film is formed on a substrate portion corresponding to the active region. A second gate electrode made of the same material or a different material as the first gate electrode is provided on a predetermined portion of the film, and the plurality of grooves in the substrate portion corresponding to the active region are provided. Formed part Wherein the portion other than beauty second portion where the gate electrode is formed of is provided with a diffusion layer serving as source and drain regions.

In the first aspect of the present invention, the case where the length direction of the groove is substantially perpendicular to the direction of the channel length is, of course, included. In addition, it is needless to say that the case where the length of the groove is substantially the same as the channel width also includes the case where it is truly the same.

In the first embodiment of the present invention, the depth of the plurality of grooves may be different for all the grooves or for some of the grooves. This is because the length of the current path can be changed more variously than when the depth of all the grooves is the same. At this time,
It is preferable that the depth of the groove provided at the position closest to the drain region diffusion layer among the plurality of grooves is greater than the depths of the other grooves. This is because the channel near the drain region is formed in a deep part of the substrate, so that the penetration of hot carriers into the insulating film is reduced and the driving capability is further increased as compared with the case where the channel is not formed.

According to the second invention of this application, when operating the field effect transistor of the first invention, a signal of a constant voltage is applied to one of the first gate electrode and the second gate electrode. Applied or the first
A signal whose potential fluctuates is applied to each of the gate electrode and the second gate electrode. Here, as an example of applying a constant voltage signal to one of the gate electrodes, for example, a fixed voltage is applied to one of the first and second gate electrodes, and a normal single gate type MOSFET is applied to the other. An example in which a signal is applied to the gate electrode is applied. As an example of applying a signal whose potential fluctuates to both gate electrodes, a signal applied to each of the first and second gate electrodes, for example, a gate electrode of a normal dual gate type MOSFET is applied. An example of application is given.

[0014]

According to the structure of the present invention, a conventional FET having the same gate length and a planar structure is provided for a plurality of grooves.
(For example, the FET of FIG. 6; hereinafter, referred to as “conventional FET”), the effective channel length is longer. And
When the potential of the gate electrode (hereinafter, also referred to as “gate potential”) is equal to or lower than the threshold voltage of the FET, the leak current flows through the substrate along this groove, so that the leak current is smaller than that of the conventional FET.

Further, the constituent materials of the first gate electrode and the constituent material of the second gate electrode can be arbitrarily selected. Further, signals applied to these gate electrodes can be set arbitrarily. Thus, it is possible to cause a difference in how the inversion layer is formed in the substrate portion facing each gate electrode. Also in this respect, it is possible to reduce the leak current and the influence of hot carriers. Further, the switching speed can be increased by utilizing the difference in the formation of the inversion layer.

Further, according to the second invention of this application, it is possible to make a difference in how the inversion layer is formed in the substrate portion facing the first and second gate electrodes. Can be used effectively.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, an embodiment of a field effect transistor (hereinafter, may be abbreviated as "FET") of the first invention and an embodiment of an operation method of the FET of the second invention will be described below. I do. However, the drawings used in the following description schematically show the dimensions, shapes, and arrangements of the components so that the present invention can be understood.
Further, in each of the drawings used for the description, the same components are denoted by the same reference numerals, and overlapping description is omitted.

1. 1. Description of Embodiment of First Invention (FET) 1-1. Structure Description FIG. 1 is a view for explaining the structure of an FET according to an embodiment of the present invention, and is a cross-sectional view of the FET cut along the channel length direction.

In the FET of this embodiment, a first insulating film 35 having a window 35a exposing a substrate portion 33 corresponding to an active region of a transistor is provided on, for example, a silicon substrate 31 as a semiconductor substrate. This first insulating film 35 becomes a field oxide film for element isolation.

Further, in the FET of this embodiment, the longitudinal direction of the substrate portion 33 corresponding to the active region corresponds to the channel length direction of the field effect transistor (in this case, X in FIG. 1).
A plurality of grooves 37 each having a rectangular shape which is substantially perpendicular to (i.e., the direction denoted by) and whose length is substantially the same as the channel width of the field effect transistor and whose cross-sectional shape is rectangular along the channel length direction (illustrated example) 3) are provided side by side. The width W, depth D, pitch P (refer to FIG. 1) and the number of the grooves can be set to dimensions and numbers according to the design. Groove 3
Reference numeral 7 can be any suitable groove having a cross-sectional shape other than a rectangle depending on the design.

Further, in the FET of this embodiment, the gate insulating film 3 as the second insulating film is formed on each of the inner walls of the plurality of grooves 37 and the surface of the substrate portion 33 corresponding to the active region.
9 is provided, and a first gate electrode 41 is provided in each of the plurality of trenches 37.
In this case, a third insulating film 43 is provided on the gate electrode 41 such that the surface thereof is flush with the surface of the portion of the second insulating film 39 on the substrate.

Further, in the FET of this embodiment, a portion on the continuous surface composed of the second insulating film 39 and the third insulating film 43 (in this case, a portion other than a portion where the source / drain region of the FET is to be formed). ) A second gate electrode 45 made of the same material or a different material as the first gate electrode.
In addition, a diffusion that becomes a source / drain region in a portion of the substrate portion 33 corresponding to the active region other than the portion where the plurality of grooves 37 are formed and the portion where the second gate electrode 45 is formed is provided. A layer 47 is provided. An intermediate insulating film 49 is provided on the sample on which the second gate electrode 45 and the diffusion layer 47 have been formed.
A contact hole 51 is provided in a predetermined portion corresponding to the diffusion layer 47. A wiring 53 (for example, an aluminum wiring) is connected to the diffusion layer 47 through the contact hole 51.

Here, that the constituent materials of the first gate electrode 41 and the second gate electrode 45 are the same or different is, for example, a case as shown in Table 1 below. Of course, this is only an example.

[Table 1]

[0024]

1-2. Description of Manufacturing Method The FET of the embodiment described with reference to FIG. 1 can be manufactured by, for example, a method described below. FIG.
3 (A) to 3 (C) and FIGS. 3 (A) to 3 (C) are manufacturing process diagrams for explanation thereof. Both figures are cross-sectional views at positions corresponding to FIG.

First, a known LOCOS (Local oxidation of silicon) method is applied to the silicon substrate 31, for example.
Substrate portion 33 corresponding to active region of transistor
A first insulating film 35 having a window 35a for exposing is formed (FIG. 2A).

Next, a groove 3 of the substrate portion 33 is formed in the substrate portion 33 corresponding to the active area for forming the groove 37.
7 A resist pattern 5 for selectively exposing a region to be formed
5 (FIG. 2B).

Next, anisotropic etching is performed on the sample on which the resist pattern 55 has been formed by, for example, RIE (Reactive Ion Etching) to form a groove 37 (FIG. 2C).

Next, a second insulating film 39 is formed in each groove 37 and on the surface of the substrate portion 33 corresponding to the active region by, for example, a thermal oxidation method (FIG. 3A).

Next, a first gate electrode forming material such as polysilicon is deposited on the entire surface of the sample on which the second insulating film 39 has been formed in a thickness sufficient to fill the groove 37. A material capable of planarizing the surface such as a resist is deposited on the first gate electrode forming material, and thereafter, the etching rate of the resist (planarizing material) is equal to the etching rate of the first gate electrode forming material. Both are etched under appropriate etching conditions until the surface of the second insulating film 39 on the surface of the substrate 31 is exposed (etchback method is performed). Thus, the first gate electrode 41 can be formed in the groove (FIG. 3B).

Next, if the first gate electrode forming material is polysilicon, the third insulating film 43 is formed on the first gate electrode 41 by oxidizing the surface by, for example, a thermal oxidation method ( (FIG. 3 (C)). In addition, the third
When the insulating film 43 is formed, the second insulating film 39 formed on the substrate surface is first removed, and the second insulating film 39 is formed again by a thermal oxidation process for forming the third insulating film 43. Good to do. This is because the second insulating film functions as a gate insulating film and needs to have a predetermined thickness.

Next, a second gate electrode forming material is formed on the entire surface of the sample on which the third insulating film 43 has been formed by a known method, and thereafter, the second gate electrode forming material is formed by a known lithography technique and etching technique. The second gate electrode 45 is formed by patterning the forming material into a predetermined shape.
(A)).

Next, ions are implanted into the substrate using the second gate electrode 45 and the first insulating film 35 as a mask at the time of ion implantation, and a source / drain diffusion layer 47 is formed in a self-aligned manner. FIG. 4 (B)).

Thereafter, though not shown, by a known method,
The formation of the intermediate insulating film 49, the formation of the contact hole 51, and the formation of the wiring 53 are performed to obtain the FET of the embodiment shown in FIG.

[0035] 2. Description of Embodiment of Second Invention (Method of Operating FET) The above-described FET of the first embodiment of the present invention has a first gate electrode 4
By using different materials for the first and second gate electrodes 45 and / or different signals to be applied to these gate electrodes, the following use is possible. In each usage method, a unique effect is obtained.

2-1. Use Example 1 In the case where the FET of the embodiment of the first invention is used as a PMOS, the first gate electrode 41 is made of p ⁺ -type polysilicon, and the second gate electrode 43 is made of n ⁺ -type polysilicon. And the first gate electrode 41 is connected to the silicon substrate 31
Of the second gate electrode 4
When 5 is used as the gate electrode of a normal MOSFET, the following effects can be obtained.

In this usage example, as shown in FIG. 5A, even when the potential of the second gate electrode 45 is 0 V, the groove 3
The inversion layer 6 is provided on the portion of the substrate that contacts the groove 37 on the bottom and side surfaces of the substrate 7.
1 (channel) is always formed. Therefore, when the potential of the second gate electrode 45 becomes equal to or higher than the threshold, the surface portion 63 of the semiconductor substrate 31 (see FIG. 5A).
A drain current flows only by forming an inversion layer. Therefore, the switching time of the FET is shorter than in the case where this is not the case (when a new inversion layer is newly formed on the entire substrate along the groove 37). When the gate potential is lower than the threshold voltage, the leak current flows through the substrate along the groove 37, so that the leak current is smaller than that of the conventional FET. Also, when the gate potential is equal to or higher than the threshold voltage, the drain current flows through the substrate along the trench 37, so that the effective channel length becomes longer than that of the conventional FET. Is less likely to occur than before. Further, when the gate potential is equal to or higher than the threshold voltage and becomes a relatively large value, a depletion layer develops more in the depth direction of the groove 37 from the substrate surface in the substrate portion between the grooves as the voltage increases, so that the channel becomes It is considered that the driving capability of the FET gradually increases toward the groove bottom side, and as a result, the driving capability of the FET increases.

2-2. Use Example 2 In the case where the FET according to the embodiment of the first invention is used as a PMOS, the first gate electrode 41 and the second gate electrode 45 are used.
Are made of n ⁺ -type polysilicon, a constant voltage equal to or higher than the threshold value of the FET is applied to the first gate electrode 41, and the second gate electrode 45 is
Also when used as the gate electrode of the SFET, even when the potential of the second gate electrode 45 is 0 V, the inversion layer 61 ( Channel) will always be formed. For this reason, an effect that the switching speed is increased as in the first usage example is obtained. Further, other effects of the usage example 1 are obtained in a similar manner.

2-3. Usage Example 3 In the case where the FET of the embodiment of the first invention is used as an NMOS, the first gate electrode 41 and the second gate electrode 45 are used.
Are made of the same material, a constant voltage equal to or higher than the threshold value of the FET is applied to the first gate electrode 41, and the second gate electrode 45 is used as a gate electrode of a normal MOSFET. Also, similarly to the above-described usage example 1, even when the potential of the second gate electrode 45 is 0 V, the groove 3
The inversion layer 6 is provided on the portion of the substrate that contacts the groove 37 on the bottom and side surfaces of the substrate 7.
Since 1 (channel) is always formed, an effect of increasing the switching speed is obtained as in the first usage example. Further, other effects of the usage example 1 are obtained in a similar manner.

The first and second use examples are the first and second use examples.
In the example described above, a fixed signal having a constant potential is applied to the gate electrode 41 of FIG. Has the same effect.

2-4. Usage Example 4 In the FET according to the embodiment of the first invention, the first gate electrode 41 and the second gate electrode 45 are made of materials having different work functions, respectively, and the first gate electrode 41 and the second gate electrode 45 are made of different materials.
May be used as the gate electrodes of ordinary MOSFETs. As an example, the second gate electrode 45 is made of a material having a higher work function than the constituent material of the first gate electrode, and the first gate electrode 4
Each of the first and second gate electrodes 45 is a normal MOSF
The case of using as an ET gate electrode will be described.

In this usage example, the threshold value at the substrate portion facing the first gate electrode 41 is larger than the threshold value at the second gate electrode 45.
Is lower than the threshold value in the substrate portion opposite to. Therefore, the substrate portion in contact with the bottom and side surfaces of the groove 37 has the second
The inversion layer is formed at a gate potential lower than the substrate portion facing the gate 45 of FIG. Therefore, both gate electrodes 41, 4
5 is equal to or less than the threshold value of the first gate electrode 41,
Since the leak current flows through the substrate along the groove 37, the leak current is reduced as compared with the conventional case. Also, both gate electrodes 41,
When the potential of the gate electrode 45 becomes equal to or higher than the threshold value of the second gate electrode 45, an inversion layer is already formed on the substrate portion facing the first gate electrode 41. Is formed, a drain current flows. For this reason, the effect that the switching speed is faster than the conventional one can be obtained as in the conventional use examples. When the gate potential further increases, in this usage example 4, both gate electrodes 4
Since both 1 and 45 have a high potential, a depletion layer grows on the substrate portion between the grooves 37 from the substrate surface side and the groove side wall side. For this reason, it is considered that the substrate portion between the trenches 37 is more depleted than in the conventional example, and as a result, the drain current is reduced as shown by 65 in FIG. Then, it is considered that the fluid flows through the substrate portion corresponding to the groove bottom. Therefore, almost the same driving capability as that of the conventional FET can be obtained.

Although the second gate electrode 45 is provided on the second insulating film 39 and the third insulating film 43 in each of the above embodiments, the second gate electrode 45 is provided on the substrate 31.
9, the second gate electrode may be provided. However, in this case, the manufacturing process becomes complicated.

[0044]

As is apparent from the above description, according to the field effect transistor of the first invention of this application, the effective channel length is longer than that of the conventional FET by the provision of the plurality of grooves. . When the potential of the gate electrode is equal to or lower than the threshold voltage of the FET, the leak current flows through the substrate along the groove, so that the leak current is smaller than that of the conventional FET. Further, the constituent material of the first gate electrode and the constituent material of the second gate electrode can be variously selected, and an arbitrary signal can be applied to these gate electrodes. For this reason, the method of use as in the second invention becomes possible, and as a result, it is possible to cause a difference in how the inversion layer is formed in the substrate portion opposed to each gate electrode, which also causes a leakage current. And the effects of hot carriers can be reduced. In addition, the switching speed can be increased by making a difference in how the inversion layer is formed in the substrate portion facing each gate electrode.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing an FET according to an embodiment of the first invention.

FIGS. 2A to 2C are process diagrams showing an example of a method for manufacturing an FET according to an embodiment.

FIGS. 3A to 3C are process diagrams subsequent to FIG. 2, illustrating an example of a method of manufacturing an FET according to an embodiment.

FIGS. 4A and 4B are process diagrams subsequent to FIG. 3, illustrating an example of a method for manufacturing an FET according to an embodiment.

FIGS. 5A and 5B are views for explaining each embodiment of the second invention.

FIG. 6 is a diagram provided for explanation of a conventional technique.

[Explanation of symbols]

 31: semiconductor substrate 33: active region 35: first insulating film (field oxide film) 35a: window exposing the active region 37: groove 39: second insulating film (gate insulating film) 41: first gate electrode 43: Third insulating film 45: Second gate electrode 47: Diffusion layer 49: Intermediate insulating film 51: Contact hole 53: Wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (2)

(57) [Claims] A first insulating film having a window exposing a substrate portion corresponding to an active region of a transistor is provided on a semiconductor substrate, and a longitudinal direction of the substrate portion corresponding to the active region is set to the electric field. A plurality of grooves which are substantially perpendicular to the channel length direction of the effect transistor and whose length is substantially the same as the channel width of the field effect transistor, are provided side by side along the channel length direction; A second insulating film is provided on each of the inner walls of the groove and the surface of the substrate portion corresponding to the active region; a first gate electrode is provided in each of the plurality of grooves; A third insulating film is provided thereon, and a predetermined material of the second insulating film on a substrate portion corresponding to the active region is formed of the same material or a different material as the first gate electrode. Diffusion on the substrate portion corresponding to the active region except for the portion where the plurality of grooves are formed and the portion where the second gate electrode is formed. A field-effect transistor, comprising a layer. 2. When operating the field-effect transistor according to claim 1, a signal of a constant voltage is applied to one of the first gate electrode and the second gate electrode, or the first gate electrode is applied to the first gate electrode or the second gate electrode. A signal whose potential varies is applied to each of the gate electrode and the second gate electrode.