JP3068563B2 - Data transfer method and data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interleave data transfer device.

[0002]

2. Description of the Related Art In a situation where a data string of 2n bytes in width (n is an integer of 1 or more) is transferred from a data transmitting device to a data receiving device, if only one data transfer port having a width of n bytes is connected, Data width and transfer width are 2:
Since it is 1, it is necessary to transfer the data in two parts, the upper side and the lower side of the data string. Here, when the number of transfer ports becomes two or more, it is possible to transfer the data at one time by dividing the data into two and separately transferring the transfer ports. This is called interleaving.

As described above, conventionally, in a computer apparatus, an interleave apparatus has been used for the purpose of efficiently transferring data.

FIG. 12 is a block diagram showing an example of a conventional interleaved data transfer device. Data transmission device 9
1 of the 2n-byte data string read from the storage device 0, the upper-side data string 16 having a width n is transferred to the data receiving device 92 through the data transfer port 12, and the lower-order data n having a width n is transferred. The column 17 is transferred to the data receiving device 92 through the data transfer port 13. Similarly, of the data string of width 2n read from the storage device 2, the data string 20 of the upper width n is transferred to the data receiving device 92 through the data transfer port 14, and the data data of the lower width n is transferred. The column 21 is transferred to the data receiving device 92 through the data transfer port 15. The data strings 16 and 17 are combined by the data combiner 28 in the data alignment circuit 93 and stored in the storage device 4, and the data strings 20 and 21 are combined by the data combiner 30 in the data alignment circuit 93 and stored in the storage device 6. Is stored in In this example, a data transmitting device 91 and a data receiving device 92 are connected in four ports, and two 2-way interleaves using two ports are used. At the time of data transfer by this interleaving method, the storage device 1,
3, 5, 7 are not used.

[0005]

However, this prior art has the following problems.

[0006] The first problem is that when performing data transfer using interleaving, the storage devices 1, 3, 5, and 7 are not used, so that hardware resources are wasted. The reason is that the interleaving paths are fixed.

The second problem is that since data is stored in the storage device 4 and the storage device 6 in a concentrated manner, the storage device 4 is likely to be in a busy state, resulting in a decrease in throughput. The reason is that the data cannot be stored in a distributed manner because the path is fixed as in the first problem.

It is an object of the present invention to provide an interleave device that uses hardware resources without waste and that performs efficient data transfer without a decrease in throughput.

[0009]

According to the present invention, the first half and the second half of the data of the odd-numbered transmission-side storage device are transferred through different data transfer ports, then combined, and stored in the corresponding reception-side storage device. The odd interleaving and the first half and the second half of the data of the even-numbered transmission side storage device are transferred via different data transfer ports and then combined, and the even interleaving stored in the corresponding reception side storage device is switched.

By switching between the odd interleave and the even interleave in a round robin manner for each data transfer, the usage rates of the storage devices are almost the same.

[0011] Switching between odd interleave / even interleave is performed in response to an interleave switch request and a data storage status of each storage device on the receiving side, that is, a busy signal indicating whether or not data has been stored at a predetermined value or more. For example, when the odd interleave is selected and at least one of the odd-numbered storage devices on the receiving side stores data equal to or more than a predetermined value and activates the busy signal, at this time, the odd-numbered storage devices on the receiving side are activated. If none of them has activated the busy signal, it switches to even-numbered interleave and switches to data transfer between even-numbered storage devices. If the interleave switching signal is activated while the odd interleave is selected, the interleave is switched to the even interleave except when one of the even storage devices on the transmission side activates the busy signal.

Further, according to the present invention, if the receiving storage device having the largest number of currently stored data is a receiving storage device corresponding to the currently selected interleave,
Switching to the other interleave is performed regardless of whether or not the interleave switching request is present and whether or not the number of data stored in the receiving side storage device corresponding to the currently selected interleave does not exceed a predetermined value.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. (First Embodiment) Referring to FIG. 1, a data transfer device according to a first embodiment of the present invention includes interleave control devices 10 and 11.

The interleave control device 10 includes storage devices 0 to 3 capable of storing a plurality of data having a data width of 2n bytes (n is an integer of 1 or more) and a data transfer path for dividing a data to be transferred and selecting a port for transferring the data. The switching control circuit 8 is configured. The storage devices 0 to 3 are connected to the data transfer path switching control circuit 8 and the data transmission device 43. Further, the interleave control device 11 has the data width 2
Storage devices 4 to 7 capable of storing a plurality of n-byte data
And a data alignment circuit 9 for aligning the transferred data.
It is composed of The storage devices 4 to 7 are connected to the data alignment circuit 9 and the data receiving device 44. The interleave control device 10 and the interleave control device 11 are connected by four data transfer ports 12 to 15. The data transfer ports 12 to 15 are signal lines capable of transmitting data having a width of n bytes at a time. The data transfer path switching control circuit 8 includes selectors 24 to 27 and a control unit 36.

The data alignment circuit 9 includes data synthesizers 28 to 3
1. Width 2 read from storage device 0
The n-byte data string is divided into a data string 16 having a width of n bytes on the upper side and a data string 17 having a width of n bytes on the lower side. Similarly, the data string read from the storage device 1 is:
The data sequences read from the storage device 2 are stored in the data sequences 18 and 19, the data sequences 20 and 21 are stored in the data sequence 20, and the data sequences read out from the storage device 3 are stored in the data sequences 22 and 23. Each is divided. The selector 24 is a circuit that selects one of the data sequence 16 and the data sequence 23. The selector 25 has a data sequence 18 and a data sequence 17
Is a circuit for selecting one of the above. The selector 26 is a circuit for selecting either the data string 20 or the data string 19. The selector 27 has the data sequence 22 and the data sequence 2
1 is a circuit for selecting any one of them. Selector 24
27 are respectively connected to the data transfer ports 12-15. The data synthesizer 28 is connected to the data transfer port 12
And the lower data string 17 transferred from the data transfer port 13 are combined.
The data combiner 29 combines the upper data sequence 18 transferred from the data transfer port 13 and the lower data 19 transferred from the data transfer port 14.

The data combiner 30 has a data transfer port 1
4 and the lower data string 21 transferred from the data transfer port 15 are combined. The data combiner 31 combines the upper data string 22 transferred from the data transfer port 15 with the lower data string 23 transferred from the data transfer port 12. Outputs of the data synthesizers 28 to 31 are stored in the storage devices 4 to 7, respectively. The control information 32 to 35 are sent to the control unit 36, which controls the selectors 24 to 27 and the data combiner 28.
To 31 are controlled. Busy signal 37 of storage devices 4 to 7
Are activated when the storage devices 4 to 7 store a certain number or more of data, and are sent to the control unit 36. The control unit 36 includes selectors 24 to 27 and data synthesizers 28 to 3
1 and the control information 32-35 and the busy signal 37-
The selectors 24 to 24 are selected by a select signal 41 in which
27 and the data synthesizers 28 to 31 are controlled.

Next, a detailed configuration of the storage devices 4 to 7 will be described. Since the storage devices 4 to 7 have the same configuration, only the storage device 4 will be described.

FIG. 2 is a block diagram showing a configuration example of the storage device 4 in the present embodiment. The storage device 4 includes a write pointer 45, a read pointer 46, a subtractor 47, a busy occurrence set value register 48, a comparator 49, and a storage circuit 50. The storage circuit 50 is a circuit in which a plurality of flip-flops are grouped and stores data. The data string 28 includes a strobe line 85 and a data line 86. The data line 86 is connected to the storage circuit 50. The storage circuit 50 is connected to the data receiving device 44 via a data line 87. The strobe line 85 is asserted synchronously during data transfer. Light pointer 4
Numeral 5 is constituted by a counter of several bits, and is incremented by one while data is written to the storage circuit 50, that is, while the strobe line 85 is asserted. Therefore, the last written location in the memory circuit 50 is shown. Also, from the data receiving device 44,
The read request signal 88 is asserted. When the read request signal 88 is asserted, data is read from the storage circuit 50. The read pointer 46 is formed of a counter of several bits, and is incremented by one while the reading of the storage circuit 50 is performed, that is, while the read request signal 88 is asserted. Therefore, the last read location in the memory circuit 50 is shown. The subtractor 47 is a circuit that subtracts the value of the read pointer 46 from the value of the write pointer 45. The busy occurrence setting value register 48 is a register formed of a flip-flop of several bits and holding a predetermined value at which busy occurs. The comparator 49 is a circuit for comparing the value of the busy occurrence set value register 48 with the result of the subtractor 47. When the result of the subtractor 47 is equal to or larger than the value of the busy occurrence set value register 48, the output becomes "1". When the result of the subtractor 47 is smaller than the value of the busy occurrence set value register 48, the output becomes 0. The result of the comparator 49 becomes the busy signal 37. Similarly, in the storage devices 5 to 7, the results of the comparator 49 are respectively output from the busy signals 38.
~ 40.

FIG. 3 is a block diagram showing a configuration example of the control unit 36 in the present embodiment. The logical sum circuit 51 is a circuit that calculates the logical sum of all the control information 32 to 35. The logical sum circuit 52 is a circuit that calculates the logical sum of the busy signals 37 and 39. The logical sum circuit 53 is a circuit that calculates the logical sum of the busy signals 38 and 40. The logic circuit 54 is a circuit having four inputs of the result of the logical sum circuit 51, the result of the logical sum circuit 52, the result of the logical sum circuit 53, and the select signal 41 and a one-bit output. Table 1 shows a truth table of the logic circuit 54. The exclusive OR circuit 55 is a circuit that performs an exclusive OR operation on the result of the logic circuit 54 and the select signal 41. F
F56 is formed of a 1-bit flip-flop, holds the result of the exclusive OR circuit 55, and outputs the select signal 41.

[0020]

[Table 1] Next, the operation of the present embodiment will be described with reference to the drawings. On the transmission side, the data transmission device 43 selects one of the storage devices 0 to 3 and stores the data to be transmitted. On the other hand, on the receiving side, the data receiving device 44 reads data stored from any of the storage devices 4 to 7.

In FIG. 1, of the 2n-byte wide data string read from the storage device 0, the upper data string 1
6 is a and the lower data string 17 is b. Similarly, the upper data string 18 read from the storage device 1 is represented by c,
The lower data sequence 19 is d, the upper data sequence 20 read from the storage device 2 is e, the lower data sequence 21 is f, the upper data sequence 22 read from the storage device 3
Is g, and the lower data string 23 is h.

Referring to FIG. 4, at T0 to T6,
The select signal 41 is "0". At this time, the selector 24 selects the data string a, and the selector 25 selects the data string b. In addition, the selector 26 selects the data string e
And the selector 27 selects the data string f. Therefore, the data strings a and b are simultaneously transferred through the data transfer ports 12 and 13, and the data synthesizer 2
After being combined at 8, it is stored in the storage device 4. On the other hand, the data strings e and f are simultaneously transferred through the data transfer ports 14 and 15, combined at the data combiner 30, and stored in the storage device 6. That is, the data sequence of the storage device 0 and the data sequence of the storage device 2 are transferred,
They are stored in the storage device 4 and the storage device 6, respectively. During this time, the data in the storage devices 1 and 3 enters a wait state and the next data is not read. This state is referred to as odd interleaving for convenience in the present invention.

Referring to FIG. 4, at T5, the control information 32-35 changes from "0" to "1". The control information 32 to 35 is one bit in the data of each of the storage devices 0 to 3 and is sent to the control unit 36. In the control unit 36, the logical sum of all the control information 32 to 35 is obtained, and the result is "1", so that it is determined that the interleave switching request has been made. That is, the transfer port can be switched by providing an interleave method switching request bit in the data. The control unit 36 switches the select signal 41 from "0" to "1" at the next T6.

Referring to FIG. 4, during T6 to T11, the select signal 41 is "1". At this time, the selector 25 selects the data string c, and the selector 26 selects the data string d. The selector 27 selects the data string g, and the selector 24 selects the data string h. Therefore, the data strings c and d are transferred at the same time through the data transfer ports 13 and 14, combined in the data combiner 29, and stored in the storage device 5.

On the other hand, the data strings g and h are simultaneously transferred through the data transfer ports 15 and 12, are combined in the data combiner 31, and are stored in the storage device 7.
That is, the data sequence of the storage device 1 and the data sequence of the storage device 3 are transferred and stored in the storage device 5 and the storage device 7, respectively. During this time, the data in the storage devices 0 and 2 enters a wait state, and the next data is not read. In the present invention, this state is called even-number interleaving for convenience.

Referring to FIG. 4, at T10, control information 32-35 changes from "0" to "1". As in the case of T5, the control information 32 to 35 are sent to the control unit 36. Since the logical sum of all the control information 32 to 35 is "1" in the control unit 36, a request for switching the interleave method is issued. Judge that there was. The control unit 36 changes the select signal 41 from “1” to “0” at the next T11.
Switch to As a result, the switching from the even interleave to the odd interleave is performed at T11.

Referring to FIG. 4, at T15, the busy signal 37 changes from "0" to "1". The busy signal 37 is a signal indicating that the storage device 4 has stored a certain amount or more of data, and is sent to the control unit 36. Control unit 3
At 6, the select signal 41 is switched from "0" to "1" at the next T16 in order to change the interleave method from the odd interleave to the even interleave due to the rise of the busy signal 37. This allows T1
At 6, dynamic switching from odd interleaving to even interleaving is performed.

Referring to FIG. 4, at T19, the control information 32-35 changes from "0" to "1". As in the case of T5 and T10, the control information 32 to 35 are sent to the control unit 36, where the control information 32 to 35 is transmitted.
Since all the logical sums of 35 are "1", it is determined that a request to switch the interleave method has been made. However, at the same time, since the busy signal 37 is still “1”, the selection signal 41 is not switched here. The control unit 36 switches the select signal 41 from "1" to "0" at T23 when the busy signal 37 switches from "1" to "0". As a result, switching from even-numbered interleaving to odd-numbered interleaving is performed at T23.

Referring to FIG. 4, at T30, the busy signal 37 changes from "0" to "1". As in the case of T15, the busy signal 37 is sent to the control unit 36. The control unit 36 switches the select signal 41 from "0" to "1" at the next T31 in order to change the interleave method from the odd interleave to the even interleave when the busy signal 37 rises. This dynamically switches from odd interleaving to even interleaving at T31. At T32, the busy signal 38 changes from "0" to "1". The busy signal 38 is sent to the control unit 36. Normally, when the busy signal 38 rises in the control unit 36, the select signal 41 is switched to change the interleave method from even interleave to odd interleave.
In this case, the selection signal 41 is not switched, and reading of the storage devices 0 to 3 by interleave transfer is suppressed. The transfer without using the interleave method in a storage device that is not busy is not suppressed.

Referring to Table 1, which is a truth value, by fixing any of the control information 32-35 to "1",
The select signal 41 always switches. That is, odd / even interleaving can be alternately switched for each data transfer. As a result, the usage rates of the storage devices are almost the same, which is more efficient. (Second Embodiment) Referring to FIG. 5, the data transfer device of the present embodiment is provided with a new busy management unit 42. Further, in addition to the busy signals 37 to 40, busy level information 57 to 60 is output from the storage devices 4 to 7. The busy level information 57 to 60 is input to the busy management unit 42.

FIG. 6 is a configuration diagram of the storage device 4 in the present embodiment. In FIG. 6, the result of the subtractor 47 is the busy level information 57. That is, this is information on how many levels of data are stored in the storage circuit 50. Similarly, in the storage devices 5 to 7, the results of the subtractor 47 become busy level information 58 to 60, respectively.

FIG. 7 is a configuration diagram of the busy management unit 42 in the present embodiment. The subtracter 62A is a circuit that subtracts the busy level information 59 from the busy level information 57. The subtracter 62B is a circuit that subtracts the busy level information 60 from the busy level information 58. Comparator 63A
Is a circuit for comparing the result of the subtractor 62A with 0.
When the result of the subtractor 62A is 0 or more, the output is "1". When the result of the subtractor 62A is less than 0, the output is "0"
Becomes The comparator 63B is a circuit that compares the result of the subtractor 62B with 0. When the result of the subtractor 62B is 0 or more, the output is "1". When the result of the subtractor 62B is less than 0, the output is "0". Inverters 64A, 64
B inverts the output signals of the comparators 63A and 63B, respectively. The AND circuits 65A and 65B include the comparators 63A and 63
This is a circuit that takes the logical product of the result of 3B and the busy level information 59, 58. The AND circuits 66A and 66B are circuits that take the AND of the outputs of the inverters 64A and 64B and the busy level information 59 and 60. OR circuit 67A, 67B
Is a circuit for calculating the logical sum of the results of the AND circuits 65A and 66A and the results of the AND circuits 65B and 66B. The subtractor 68 is a circuit that subtracts the output of the OR circuit 67A and the output of 67B. The comparator 69 is a circuit that compares the result of the subtractor 68 with 0. When the result of the subtractor 68 is 0 or more, the output is “1”.
Becomes When the result of the subtractor 68 is less than 0, the output "0"
Becomes The result of the comparator 69 becomes the busy management information 61. In the busy management unit 42, the busy level information 57
Search for the largest of ~ 60. Busy management information 6
When 1 is "1", the largest one is the busy level information 57.
In the case of or 59, the even interleave is prioritized. When the busy management information 61 is "0", the largest one is the busy level information 58 or 60, and the odd interleave has priority. The busy management information 61 is sent to the control unit 63.

FIG. 8 is a configuration diagram of the control unit 63 in the present embodiment. The control unit 63 includes OR circuits 51, 52, 53
, A logic circuit 71, an exclusive OR circuit 55, and a flip-flop 56. The logic circuit 71 includes a result of the logical sum circuit 51, a result of the logical sum circuit 52, and a logical sum circuit 53.
As a result, the circuit takes the logic of five inputs of the select signal 41 and the busy management information 61. Table 2 shows a truth table of the logic circuit 71.

[0034]

[Table 2] This embodiment has a new effect that data is more efficiently stored in the storage device on the receiving side because the probability that the stored information is busy with a certain value or more is reduced. (Third Embodiment) FIG. 9 is a configuration diagram of a data transfer device according to a third embodiment of the present invention.

Referring to FIG. 9, the selector 24 is a circuit for selecting one of the data sequence 16 and the data sequence 19. The selector 25 is a circuit that selects one of the data sequence 18 and the data sequence 6. The selector 26 is a circuit that selects one of the data string 20 and the data string 23. The selector 27 is a circuit that selects one of the data sequence 22 and the data sequence 21. Selectors 24-27
Are connected to the data transfer ports 12 to 15, respectively. The data combiner 28 combines the upper data string 16 transferred from the data transfer port 12 with the lower data string 17 transferred from the data transfer port 13. The data combiner 29 combines the upper data string 18 transferred from the data transfer port 13 with the lower data string 19 transferred from the data transfer port 12. Data synthesizer 30
Connects the upper data string 20 transferred from the data transfer port 14 and the lower data string 21 transferred from the data transfer port 15. The data combiner 31 includes an upper data string 22 transferred from the data transfer port 15 and a lower data string 23 transferred from the data transfer port 14.
And

The control unit 72 is connected to the selectors 24 to 27 and the data synthesizers 28 to 31, and controls information 32 to 3
Select signal 73 taking into account 3 and busy signals 37-38
Controls the selectors 24 and 25 and the data combiners 28 and 29, and outputs control information 34 to 35 and busy signals 39 to 4
The selectors 26 and 2 are selected by the select signal 74 in which 0 is added.
7 and the data synthesizers 30 and 31 are controlled.

FIG. 10 shows a control unit 72 according to this embodiment.
The detailed configuration of is shown. The OR circuit 75 controls the control information 32
And a circuit for calculating the logical sum of. The OR circuit 76
This is a circuit for calculating the logical sum of the control information 34 and 35. The logic circuit 79 outputs the result of the select signal 73 and the OR circuit 75,
This is a circuit that takes the logic of four inputs of a busy signal 37 and a busy signal 38. The logic circuit 80 is a circuit that takes the logic of the four inputs of the busy signal 37 and the busy signal 38 as a result of the select signal 74 and the OR circuit 76. Table 3 shows a truth table of the logic circuit 79. Table 4 shows a truth table of the logic circuit 80.
Shown in

[0038]

[Table 3]

[0039]

[Table 4] The exclusive OR circuit 81 is a circuit that performs an exclusive OR operation on the result of the logic circuit 79 and the select signal 73. FF83
Is formed of a 1-bit flip-flop and holds the result of the exclusive OR circuit 81. The output of the FF 83 becomes the select signal 73. The exclusive OR circuit 82 is a circuit that performs an exclusive OR operation on the result of the logic circuit 80 and the select signal 74. The FF 84 is configured by a 1-bit flip-flop, and holds the result of the exclusive OR circuit 82.
The output of the FF 84 becomes the select signal 74.

Next, the operation of the circuit of FIG. 9 will be described with reference to the drawings.

Referring to FIG. 11, in T0 to T6, select signal 73 and select signal 74 are both "0". At this time, the selector 24 selects a, and the selector 25 selects b. The selector 26 selects e, and the selector 27 selects f. Therefore, the data strings a and b are simultaneously transferred through the data transfer ports 12 and 13, and the data synthesizer 2
After being combined at 8, it is stored in the storage device 4. On the other hand, the data strings e and f are simultaneously transferred through the data transfer ports 14 and 15, combined at the data combiner 30, and stored in the storage device 6. That is, the data sequence of the storage device 0 and the data sequence of the storage device 2 are transferred,
They are stored in the storage device 4 and the storage device 6, respectively. During this time, the data in the storage devices 1 and 3 enters a wait state and the next data is not read.

Referring to FIG. 11, at T5, the control information 32 to 33 change from "0" to "1". The control information 32 to 33 is one bit in the data of each of the storage devices 0 and 1 and is sent to the control unit 72. In the control unit 72, the logical sum of the control information 32 to 33 is calculated, and the result is “1”.
If so, it is determined that there has been a request to switch the interleave method. That is, the transfer port can be switched by providing the interleaving method switching request bit in the data. The control unit 72 switches the select signal 73 from "0" to "1" at the next T6.

Referring to FIG. 11, the select signal 73 is "1" in T6 to T11. At this time, the selector 25 selects c and the selector 24 selects d. Therefore, the data strings d and c are simultaneously transferred through the data transfer ports 12 and 13 and are combined in the data combiner 29 before being stored in the storage device 5. That is, the data string of the storage device 1 is transferred and stored in the storage device 5.

During this time, the data in the storage device 0 enters a wait state and the next data is not read.

Referring to FIG. 11, at T8, the control information 34 to 35 change from "0" to "1". The control information 34 to 35 is one bit in the data of each of the storage devices 2 and 3 and is sent to the control unit 72. The control unit 72 calculates the logical sum of the control information 34 to 35, and if the result is 1, determines that the interleave method has been switched. That is, the transfer port can be switched by providing an interleave method switching request bit in the data. The control unit 72 switches the select signal 74 from "0" to "1" at the next T6.

Referring to FIG. 11, the select signal 74 is "1" from T9 to T28. At this time, the selector 26 selects h and the selector 27 selects g. Therefore, the data strings h and g are simultaneously transferred through the data transfer ports 14 and 15, are combined in the data combiner 31, and are stored in the storage device 7. That is, the data sequence in the storage device 3 is transferred and stored in the storage device 7.

During this time, the data in the storage device 2 enters a wait state and the next data is not read.

Referring to FIG. 11, at T10, the control information 32-33 changes from "0" to "1". T5
The control information 32 to 33 are stored in the
The control unit 72 determines that the request for switching the interleave method has been issued since the logical sum of the control information 32 to 33 is “1”. The control unit 72 determines the next T
At 11, the select signal 73 is switched from "1" to "0". As a result, the data in the storage device 0 switches to valid interleave at T11.

Referring to FIG. 11, the busy signal 37 changes from "0" to "1" at T15. The busy signal 37 is a signal indicating that the storage device 4 has stored a certain amount of data or more, and is sent to the control unit 72. In the controller 72, the select signal 73 is changed from "0" to "1" at the next T16 due to the rise of the busy signal 37.
Switch to

As a result, the data in the storage device 1 is switched to valid interleave at T16.

Referring to FIG. 11, at T19, the control information 32-33 changes from "0" to "1". T5
Similarly to the case of T10 and T10, the control information 32 to 33 are sent to the control unit 72, and the control information
Since the logical sum of .about.33 is 1, it is determined that a request for switching the interleave method has been made. However, at the same time, since the busy signal 37 is still "1", the selection signal 73 is not switched here. Control unit 72
Is T when the busy signal 37 is switched from “1” to “0”.
At 23, the select signal 73 is switched from "1" to "0". Thereby, the data in the storage device 0 is switched to the valid interleave at T23.

Referring to FIG. 11, at T27, the control information 34 to 35 change from "0" to "1". T8
The control information 34 to 35 are stored in the control
The control unit 72 determines that the request for switching the interleave method has been issued since the logical sum of the control information 34 to 35 is “1”. The control unit 72 determines the next T
At 28, the select signal 74 is switched from "1" to "0".

Referring to FIG. 11, after T27, the control information 34 to 35 remain "1". This control information 34
35 are sent to the control unit 72, and the select signal 74 is alternately switched from "1" to "0" from "0" to "1". That is, data transfer is performed alternately for the storage devices 2 and 3. This further reduces the probability that the storage devices 6 and 7 will be busy.

In this embodiment, the connection configuration for data transfer is changed. This embodiment is more effective when the connection between the data transmitting device and the data receiving device is two ports.
In a two-port connection, data in storage device 0 is interleaved using data transfer ports 12 and 13, and data in storage device 1 is similarly interleaved using data transfer ports 13 and 12. Therefore, it is possible to switch between two interleaving methods, that is, interleaving in which data in the storage device 0 is valid and interleaving in which data in the storage device 1 is valid. As described above, the connection configuration of this embodiment has a new effect that the hardware use efficiency does not decrease even when two ports are connected.

Next, consider the case where a failure has occurred in the data transfer port. If a failure occurs in the data transfer port 14 or the data transfer port 15 or both and the transfer path becomes unavailable, the data transfer port 1
2 and the data transfer between the data transfer ports 13 can be interleaved, and the storage devices 0 and 1 can be used without waste. Similarly, data transfer port 1
Even when a failure occurs in the data transfer port 2, the data transfer port 13, or both of them, the data transfer between the data transfer port 14 and the data transfer port 15 can be interleaved, and the storage device 2 and the storage device 3 can be used without waste. . As described above, the present embodiment has a new effect that interleaved transfer can be performed even if a failure occurs in the transfer path.

In the above embodiment, the control information 32 to 3
5 is included in the data of the storage device, but may be given from outside the data.

[0057]

As described above, the present invention includes means for dynamically switching the port for transferring data, so that efficient data transfer can be performed without a decrease in throughput. Hardware resources can be used without waste.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transfer device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a storage device 4 in FIG.

FIG. 3 is a configuration diagram of a control unit 36 in FIG.

FIG. 4 is a timing chart showing the operation of the first embodiment.

FIG. 5 is a configuration diagram of a data transfer device according to a second embodiment of the present invention.

6 is a configuration diagram of a storage device 4 in FIG.

FIG. 7 is a configuration diagram of a busy management unit in FIG. 5;

8 is a configuration diagram of a control unit 70 in FIG.

FIG. 9 is a configuration diagram of a data transfer device according to a third embodiment of the present invention.

FIG. 10 is a configuration diagram of a control unit 72 in FIG. 10;

FIG. 11 is a timing chart showing the operation of the third embodiment.

FIG. 12 is a configuration diagram of a conventional example of a data transfer device.

[Explanation of symbols]

 0 to 7 storage device 8 data transfer bus switching control circuit 9 data alignment circuit 10, 11 interleave control device 12 to 15 transfer port 16 to 23 data sequence 24 to 27 selector 28 to 31 data synthesizer 32 to 35 control information 36 control unit 37-40 Busy signal 41 Select signal 42 Busy management unit 43 Data transmitting device 44 Data receiving device 45 Write pointer 46 Read pointer 47 Subtractor 48 Busy occurrence setting value register 49 Comparator 50 Storage circuit 51-53 OR circuit 54 Logic circuit 55 Exclusive OR circuit 56 FF 57-60 Busy level information 61 Busy management information 62A, 62B Subtractor 63A, 63B Comparator 64A, 64B Inverter 65A, 66A, 65B, 66B AND circuit 67A, 67B OR circuit 68 Subtraction Bowl 9 Comparator 70 Control unit 71 Logic circuit 72 Control unit 73, 74 Select signal 75, 76 OR circuit 79, 80 Logic circuit 81, 82 Exclusive OR circuit 83, 84 FF 85 Strobe line 86, 87 Data line 88 Read Request signal

Continuation of front page (56) References JP-A-2-140853 (JP, A) JP-A-58-114119 (JP, A) JP-A-2-146656 (JP, A) JP-A-1-290048 (JP) JP-A-59-49639 (JP, A) JP-A-4-340635 (JP, A) JP-A-4-211880 (JP, A) JP-A-59-84643 (JP, U) (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/06 G06F 12/04 G06F 3/00 G06F 13/16 G06F 13/36

Claims (14)

(57) [Claims] The data stored in m (m is an even number of 2 or more) transmission-side storage devices capable of storing a plurality of data having a data width of 2n bytes (n is an integer of 1 or more) is represented by a data width of Is a data transfer method for transferring data to corresponding storage devices of m receiving storage devices capable of storing a plurality of 2n-byte data through m data transfer ports having a data width of n bytes. The first half and the second half of the data of the transmission side storage device are transferred via different data transfer ports and then combined and stored in the corresponding reception side storage device, and the first half of the data of the even number transmission side storage device is stored. Interleave switching required to transfer the second half through separate data transfer ports and then combine and switch the even interleaving stored in the corresponding receiving storage device and switch the interleaving If There inputted, and / or if the data of at least one a specified value or more of the number of the receiving-side storage device corresponding to the interleaving that is currently selected is stored, the received corresponding to the interleaving that is not currently selected A data transfer method for switching interleaving when data equal to or less than a specified value is stored in any of the side storage devices. 2. If the receiving storage device having the largest number of data currently stored is the receiving storage device corresponding to the currently selected interleave, the presence or absence of the interleave switching request and the currently unselected interleave switching request are not present. The method according to claim 1, wherein the switching to the other interleave is performed regardless of whether the number of data stored in the receiving storage device corresponding to the interleave exceeds a prescribed value. 3. First, second,..., Which can store a plurality of data having a data width of 2n bytes (n is an integer of 1 or more).
The m-th (m is an even number equal to or greater than 2) transmission-side storage device and the first, second,..., M-th transmission-side storage device, respectively. 1
, As the first input, and the second half of the data as the second input from the m-th, first, second,... The first selector selects the first and second inputs according to the first and second logic levels of the select signal, and the even selector selects the first and second inputs of the select signal.
, M-th selector for selecting and outputting the second and first inputs, respectively, according to the logical level of the first, second,..., M-th selectors. The first, second,..., M-th data transfer ports to which the outputs of the selectors are output, and the first and second, second and third,.
Are combined when the select signal is at the first logic level if it is an odd-numbered data combiner, and if the select signal is at the second logical combiner if it is an even-numbered data combiner. .., M-th data synthesized from the first, second,..., M-th transmission-side storage devices and assembled into data having a data width of 2n, respectively. A plurality of data synthesized by the data synthesizer and the first, second,..., M-th data synthesizers are stored, and a busy signal is output when the number of currently stored data exceeds a set value. , M-th receiving-side storage device, and the select signal, the interleave switching signal, and the busy signal are input, and the select signal is at a first logical level, and Interleave switching signal In but inactive,
When the busy signal from at least one odd-numbered receiving storage device is active and all even-numbered receiving storage devices are inactive, and when the select signal is at the first logic level and the interleave If the switching signal is active and the busy signals of all even-numbered receiving storage devices are inactive, the select signal is switched to a second logical level, and the select signal is switched to the second logical level, and the interleave switching is performed. The signal is inactive, all odd-numbered receiving storage busy signals are inactive, and at least one even-numbered receiving storage busy signal is active;
A control unit that switches the select signal to the first logical level when the select signal is at the second logical level, the interleave switching signal is active, and the busy signals of all odd-numbered receiving storage devices are inactive; A data transfer device having: 4. A storage circuit for storing the data, a write pointer that is incremented by one each time one data is written to the storage circuit, and one data from the storage circuit. Is read every time
A read pointer that is incremented by one, a subtractor that subtracts the value of the read pointer from the value of the write pointer, a busy occurrence setting value register that holds a default value at which a busy occurs, and an output of the subtractor that is busy. 4. The apparatus according to claim 3, further comprising a comparator for comparing with a predetermined value of an occurrence setting value register and activating the busy signal when the predetermined value is exceeded. 5. A first OR circuit for calculating a logical sum of a busy signal of an odd-numbered storage device of the receiving-side storage device, and a busy-state of an even-numbered storage device of the receiving-side storage device. A second OR circuit for calculating a logical sum of signals, a flip-flop for holding the select signal, an output of the first logical circuit, an output of the second logical circuit, an interleave switching signal, and an output of the flip-flop. The output of the flip-flop is at a first logic level, the interleave switching signal is inactive,
An output of the first OR circuit indicates that a busy signal of at least one odd-numbered receiving storage device is active, and an output of the second OR circuit indicates that all even-numbered receiving devices are active. When the busy signal of the storage device indicates inactive, the output of the flip-flop is at the first logic level, the interleave switching signal is active, and the output of the second OR circuit is all even numbers. If the busy signal of the second receiving storage device indicates inactive, the output is switched to a second logical level, the output of the flip-flop is at the second logical level, and the interleave switching signal is inactive. Active, the output of the first OR circuit indicates that the busy signals of all odd-numbered receiving storage devices are inactive, and When the output of the OR circuit indicates that the busy signal of at least one even-numbered receiving storage device is active, the output of the flip-flop is at the second logical level, and the interleave switching signal is When active, the output of the first OR circuit indicates that the busy signals of all odd-numbered receiving storage devices are inactive,
A logic circuit that outputs the same logic level as the output of the flip-flop except for the above, and an exclusive-OR circuit that performs an exclusive-OR operation on the output of the logic circuit and the output of the flip-flop , Claim 3
Or the apparatus according to 4. 6. The data processing apparatus according to claim 3, wherein the interleave switching signal is included as 1-bit data in data output from each of the transmission-side storage devices, and the interleave switching signal is a logical sum of the data. The apparatus according to claim 1. 7. A first, second,..., Which can store a plurality of data having a data width of 2n bytes (n is an integer of 1 or more).
The m-th (m is an integer equal to or greater than 2) transmission-side storage device and the first, second,..., And m-th transmission-side storage devices, respectively. 1
, As the first input, and the second half of the data as the second input from the m-th, first, second,... The first selector selects the first and second inputs according to the first and second logic levels of the select signal, and the even selector selects the first and second inputs of the select signal.
, M-th selector for selecting and outputting the second and first inputs, respectively, according to the logical level of the first, second,..., M-th selectors. The first, second,..., M-th data transfer ports to which the outputs of the selectors are output, and the first and second, second and third,.
,..., And assemble them into data having a data width of 2n output from the first, second,. .., The m-th data combiner, and a plurality of data combined by the first, second,..., M-th data combiners are stored, and the number of data currently stored is determined by a busy level. .., M-th receiving side storage device for activating a busy signal when the number exceeds a set value, and inputting the busy level information, A busy management unit that outputs first and second logical level busy management information when the storage device with the largest level information is an odd-numbered storage device and an even-numbered storage device; Interleave switching Signal, the busy signal, and the busy management information, the select signal is at the first logic level, the interleave switching signal is inactive, and the busy signals of all odd-numbered and even-numbered receiving storage devices are Inactive,
When the busy management information is at the first logic level, when the select signal is at the first logic level, the interleave switching signal is inactive, and the level signal of at least one odd-numbered receiving storage device is active. When the level signals of all the even-numbered receiving storage devices are inactive, when the select signal is at the first logical level, and when the interleave switching signal is inactive,
The busy signal of at least one odd-numbered receiving storage device is active, the busy signal of at least one receiving storage device is active, and the busy management information is the first.
And the case where the select signal is the first logical level, the interleave switching signal is active, and the busy signals of all the odd-numbered and even-numbered receiving storage devices are inactive, The select signal is at the first logic level, the interleave switching signal is active, the busy signals of at least one odd-numbered receiving storage device are active, and the busy signals of all even-numbered receiving storage devices are inactive. And the select signal is at a first logic level, the interleave switching signal is active, the busy signal of at least one odd-numbered receiving storage device is active, and at least one even-numbered receiving storage device is active. When the busy signal is active, the select signal is switched to the second logic level, The select signal is at the second logic level, the interleave switching signal is inactive, the busy signals of all odd-numbered receiving storage devices are inactive, and the busy signals of all even-numbered receiving storage devices are Inactive, when the busy management information is at the first logical level, and when the select signal is at the second logical level, the interleave switching signal is inactive, and at least one of the odd-numbered receiving side storage devices is busy. When the signal is active and the busy signals of all even-numbered receiving storage devices are inactive, and when the select signal is at the second logic level and the interleave switching signal is inactive and at least one odd-numbered The busy signal of the receiving storage device is active,
When the busy signal of at least one even-numbered receiving storage device is active and the busy management information is at the first logical level, and when the select signal is at the second logical level and the interleave switching signal is active. When the busy signals of at least one odd-numbered receiving storage device are active and the busy signals of all even-numbered receiving storage devices are inactive, and when the select signal is switched to the first logical level. A data transfer device having a unit. 8. A storage circuit for storing the data, a write pointer that is incremented by one each time data is written to the storage circuit, and a data read from the storage circuit. A read pointer that is incremented by one, a subtractor that subtracts the value of the read pointer from the value of the write pointer and outputs a result as the busy level information, and a busy generator that holds a default value at which a busy occurs. The apparatus according to claim 7, further comprising a setting value register, and a comparator for comparing an output of the subtractor with a setting value of the busy generation setting value register, and activating the busy signal if the value exceeds the predetermined value. . 9. A circuit for inputting the busy level information of the odd-numbered receiving side storage device and outputting the maximum busy level information, and the busy level information of the even-numbered receiving side storage device. Then, the circuit that outputs the maximum busy level information is compared with the maximum busy level information of the odd-numbered receiving storage devices and the busy level information of the even-numbered receiving storage devices. 8. A circuit for outputting the level management information of a second logical level when the first logical level is larger than the latter.
Or the apparatus according to 8. 10. A control circuit, comprising: a first logical sum circuit for calculating a logical sum of an odd-numbered busy signal of the receiving side storage device; and a logical sum of a busy signal of an even-numbered receiving side storage device. A second OR circuit, a flip-flop holding the select signal, an output of the flip-flop, the interleave switching signal, an output of the first OR circuit, an output of the second OR circuit, Busy management information is input, the output of the flip-flop is at a first logic level, the interleave switching signal is inactive, and the output of the first OR circuit is the output of all odd-numbered receiving-side storage devices. Indicating that the busy signal is inactive, the case where the busy management information is at the first logic level, and the case where the output signal of the flip-flop is at the first logic level, The interleave switching signal is inactive, the output of the first OR circuit indicates that the level signal of at least one odd-numbered receiving storage device is active, and the output of the second OR circuit is When the level signals of all even-numbered receiving storage devices indicate inactive, the output of the flip-flop is at a first logic level, the interleave switching signal is inactive, and the The output of one OR circuit is at least one
The busy signals of the odd-numbered receiving storage devices are active, the output of the second OR circuit is active, the busy signal of at least one receiving storage device is active, and the busy management information is at the first logical level. And the output of the flip-flop is at the first logic level, the interleave switching signal is active, and the output of the first OR circuit is set to the busy signal of all odd-numbered receiving-side storage devices. Active, the output of the second OR circuit indicates that the busy signals of all even-numbered receiving-side storage devices are inactive, and the output of the flip-flop indicates the active state. At a logical level of 1, the interleave switching signal is active, and the output of the first OR circuit outputs at least one of the odd-numbered receiving-side storage devices. And the output of the second OR circuit indicates that the busy signals of all even-numbered receiving storage devices are inactive, and The output is at a first logic level, the interleave switch signal is active, the output of the first OR circuit indicates that a busy signal of at least one odd-numbered receiving storage device is active, If the output of the second OR circuit indicates that the busy signal of at least one even-numbered receiving storage device is active,
The select signal is switched to a second logical level, the output of the flip-flop is at a second logical level, the interleave switching signal is inactive, and the output of the first OR circuit is all odd-numbered. The busy signal of the receiving storage device is inactive, and the output of the second OR circuit indicates that the busy signals of all even-numbered receiving storage devices are inactive;
When the busy management information is at the first logic level, when the output of the flip-flop is at the second logic level, the interleave switching signal is inactive, and the output of the first OR circuit is at least one Indicates that the busy signals of the odd-numbered receiving storage devices are active, and that the output of the second OR circuit indicates that the busy signals of all the even-numbered receiving storage devices are inactive. The output of the flip-flop is at a second logic level, the interleave switching signal is inactive, and the output of the first OR circuit is a busy signal of at least one odd-numbered receiving storage device. Is active, and the output of the second OR circuit is activated by the busy signal of at least one even-numbered receiving storage device. And when the busy management information is at the first logical level, the output of the flip-flop is at the second logical level, the interleave switching signal is active, and the first OR circuit is activated. Indicates that the busy level signal of at least one odd-numbered receiving storage device is active, and the output of the second OR circuit indicates that the busy signals of all even-numbered receiving storage devices are A logic circuit for switching the select signal to a first logic level when the signal indicates inactive; an exclusive OR of an output of the flip-flop and an output of the logic circuit; 10. The method according to claim 7, further comprising an OR circuit.
Item. 11. The data processing apparatus according to claim 7, wherein the interleave switching signal is included as 1-bit data in data output from each of the transmission side storage devices, and the interleave switching signal is a logical sum of the data. The device according to claim 1. 12. An m set (m is an integer of 1 or more) including a first and a second storage device capable of storing a plurality of data having a data width of 2n bytes (n is an integer of 1 or more). ) And a set of m selectors corresponding to each set of the transmission-side storage devices, wherein a set of the first and second selectors is one set,
The first selector of the k-th (k = 1, 2,..., m) group receives the first half of the data output from the first storage device as a first input and uses the second storage device as a first input. And the second half of the data output from the first and second data according to the first and second logic levels of the k-th select signal.
Of the data output from the second storage device, respectively.
Is the first input, the second half of the data output from the first storage device is the second input, and the second half of the data is output according to the first and second logic levels of the k-th select signal. 2,
M sets of selectors each of which selects and outputs a first input, and m and a set of first and second data transfer ports to which outputs of the first and second selectors of each selector group are output. A set of data transfer ports, and a set of m data combiners corresponding to each set of the selector group, with the first and second two data combiners being one set, and And a second data combiner for combining the first half data and the second half data of the first storage device output from the first and second selectors. M sets of data combiners for combining the first half data and the second half data of the second storage device output from the first storage device and the first storage device and the second storage device as one set , M sets of receiving-side storage devices corresponding to each set of the data synthesizer group, wherein Each of the device first, second
Storing the data synthesized by the data synthesizer of m, a group of m receiving storage devices that activates a busy signal when the number of currently stored data exceeds a set value, and the transmitting storage device, The selector, the data transfer port, the data combiner, and the receiving storage device are provided for each set, and the select signal, the interleave switching signal, and the busy signal of the set are input, and the select signal is a first signal. When the interleave switching signal is inactive at a logic level, the busy signal of the first storage device is active, and the busy signal of the second storage device is inactive, the select signal is at the first logic level,
The interleave switching signal is active and the first
And when the busy signal of the second storage device is inactive, the select signal is at the first logic level, the interleave switching signal is active, the busy signal of the first storage device is active, and the second signal is active. When the busy signal of the storage device is inactive, the select signal is switched to the second logical level, the select signal is at the second logical level, the interleave switching signal is inactive, and the first and second signals are inactive. The select signal is at a second logical level, the interleave switching signal is inactive, and the select signal is active when the busy signal of the first storage device is active. Is at a second logical level, the interleave switching signal is active, and the first storage device is If the busy signal is active, the data transfer system having a control unit for switching the select signal to the first logic level. 13. Each set of the control units inputs a flip-flop holding the select signal, an output of the flip-flop, the interleave switching signal, and a busy signal of the first and second storage devices. The output of the flip-flop is at a first logic level, the interleave switching signal is inactive, the busy signal of the first storage device is active, and the second
When the busy signal of the storage device is inactive, the output of the flip-flop is at the first logic level, the interleave switching signal is active, and the busy signals of the first and second storage devices are inactive. ,
If the output of the flip-flop is at a first logic level, the interleave switch signal is active, the busy signal of the first storage device is active, and the busy signal of the second storage device is inactive, The second
When the output of the flip-flop is at a second logic level, the interleave switching signal is inactive, and the busy signals of the first and second storage devices are both inactive, Is at a second logic level, the interleave switching signal is inactive, and the busy signal of the first storage device is active, the output of the flip-flop is at a second logic level and the interleave switching signal is Is active and the busy signal of the first storage device is active, a logic circuit for switching an output to a first logic level; and an exclusive OR of an output of the flip-flop and an output of the logic circuit; 13. The device according to claim 12, further comprising an exclusive OR circuit for setting a result to the flip-flop. . 14. The interleaving switching signal according to claim 12, wherein the interleaving switching signal is included as 1-bit data in data output from each of the transmission side storage devices, and the interleaving switching signal is a logical sum of the data. apparatus.