JP3065001B2 - Burn-in device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for performing an acceleration test and a pass / fail judgment of a semiconductor integrated circuit, and more particularly to a burn-in apparatus.

[0002]

2. Description of the Related Art FIGS. 8 (a) to 8 (d) show an example of connection of various signal lines and a power supply to an IC socket 21 arranged on a burn-in board 20, and FIG.
This indicates that the same IC socket pattern is commonly connected. 22 is a burn-in board 20
Signal input terminal. Arrow A indicates the column direction, and arrow B indicates the row direction.

FIGS. 8A and 8B show a burn-in board 20, a bias power supply, an address signal, and other control signals CLK.
FIG. 8 (a) shows a mode in which signals are connected, and FIG. 8 (a) shows a mode in which the IC socket 21 is divided into upper and lower parts, and FIG. 21 illustrates a form in which the entire circuit 21 is connected in common.

In the case of FIG. 8C, a pass / fail test of an integrated circuit under test (hereinafter, referred to as an IC under test) inserted into IC sockets 21 arranged in the column direction A on the burn-in board 20 can be performed. Signal (hereinafter, SCAN)
Signal, and the burn-in board 20
The upper IC sockets 21 are commonly connected one by one in the column direction.

FIG. 8D shows a connection form of I / O signals, and the IC sockets 21 on the burn-in board 20 are commonly connected every row in the row direction.

As shown in FIGS. 8 (a) to 8 (d), in the burn-in board 20, the signal lines and the bias power supply are shared by one column (or row) in the column (or row) direction or the entire board (or half). Due to the connection, there is a case where a good IC to be measured is determined to be defective due to the influence of a bias power supply, a signal line failure, a burn-in board failure, or a defective device on the device side, and the column (row) direction. A case where the IC to be measured in one column (row) or the whole (or half) of the burn-in board is determined to be defective (hereinafter, referred to as a block defect; if only one column (row) among the block defects is determined to be a line defect). There is. For example, if the bias power supply has failed, all of the ICs to be measured in either the upper or lower half (or the entire board) are determined to be defective.

In order to find a block defect using a conventional apparatus, it is necessary to search for a block failure using a tool (hereinafter, referred to as a pass / fail map) for displaying a test result for each burn-in board after the test is completed. Usually, I
C is a lot in which a certain quantity is put together, and each process is managed. Pass / fail results of each IC under test are totalized to determine pass / fail of the whole lot. If the judgment value exceeds the standard value, a block defect is found by cause investigation etc., but if the judgment value is within the standard value, the lot with the block defect is sent to the next process as it is In many cases, block failure is not found.

A general burn-in device is shown in FIG.
As described in Japanese Patent Application Publication No.
External input / output device 36, storage unit 32, CRT 37, pattern generation unit 33, power supply unit 34, pass line 31, constant temperature bath 3
5. It is composed of a judgment unit 38. 39 is a burn-in board.

FIG. 10 shows a judgment unit 38 in the burn-in device shown in FIG. 9. The judgment unit 38 includes a comparison circuit 38a for comparing an output signal a from the IC under test with an expected value b, and a comparison circuit 38a. A data holding circuit 38b for capturing a test result in synchronization with a one-shot pulse signal (hereinafter, referred to as a strobe signal c) for capturing a test result output from the circuit 38a, and a test result captured by the data holding circuit 38b. And a data register 38c for temporarily capturing data. Data register 38
The test determination result captured in c is sent to the system of the apparatus, and is used as data for determination and data of a test result display tool (a pass / fail map and other tools).

[0010]

However, the conventional burn-in apparatus shown in FIGS. 9 and 10 does not always monitor the test results. It cannot be detected early. Therefore, even if the IC under test is good,
If the pass / fail judgment value of the lot exceeds the specified value due to a block failure, there is a problem that reburn-in is required, or if the judgment value is within the specified value, the next process is performed. In this case, there is a possibility that a defect that a good IC is discarded as defective is generated.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and a burn-in apparatus capable of detecting a block failure in real time and detecting a failure (aging) of a burn-in board. Is to provide.

[0012]

In order to achieve the above object, a burn-in device according to the present invention comprises a comparison circuit,
Burn-in device having a data holding circuit and a counter circuit
, The comparison circuit is provided on a burn-in board.
To be connected to IC sockets arranged in rows and rows
Compare the output signal from the integrated circuit with the expected data
And the data holding circuit outputs from the comparison circuit.
Is intended to capture the comparison result force, said counter
In the circuit, each signal line is commonly used for the semiconductor integrated circuit under test.
Any row or row of IC sockets connected to the road
The defect of the semiconductor integrated circuit under test in one column (or row)
Counted, all are determined to be defective and one column (or row)
Alarm when the number of failure occurrences reaches the reset value
By generating a signal, any column (or row)
The connection failure is detected.

Further, the data holding circuit includes a strobe signal.
At the rising edge of the signal
It is something that fits .

The counter circuit may store the data.
Using the strobe signal when the output of the circuit is High
AND circuit for generating one-shot pulse
And a one-shot pulse is generated at the output of the AND circuit.
Counter that counts at the rise when it is generated
It is composed of

[0015]

[0016]

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) In the embodiment described below, it is assumed that I / O0 is connected to all the ICs to be tested in the first row of the IC socket array on the burn-in board. Similarly, I / O1 is in the second row, I / O2 is in the third row,
It is assumed that / O3 is connected to the fourth row, I / O4 is connected to the fifth row, and I / O5 is connected to all the tested ICs in the sixth row. Simultaneously test all ICs (hereinafter, SCAN 0) → simultaneously test all ICs under test in column B (hereinafter, SCAN 1) → simultaneously test all ICs under test in column C (hereinafter, SCAN 0)
SCAN 2) → Simultaneously test all ICs under test in row D (hereinafter referred to as SCAN 3) → I under test in row E
Test all C simultaneously (hereinafter referred to as SCAN 4) →
Test all ICs under test in row F at the same time (hereinafter SCAN)
5).

The test results in the first and second embodiments described below are for detecting a line / block defect in the I / O or SCAN direction for each test item in the test program.

FIG. 1 is a diagram showing an I / O according to the first embodiment of the present invention.
It is a block diagram which shows the line defect detection circuit of O direction.

FIG. 1 shows one I / O circuit, but in an actual burn-in device, I / O0 to n
(N is an integer) each has a determination unit 1.

The determination unit 1 shown in FIG.
A comparison circuit 2 for comparing the O output a with an expected value b of the I / O output, a data holding circuit 3 for taking in the output d of the comparison circuit 2 at the rising timing of the strobe signal c, and an output e of the data holding circuit 3 Circuit 4 generates a one-shot pulse f using the strobe signal c when the signal is "H", and counts at the rising edge when a one-shot pulse is generated at the output f of the AND circuit 4. And a counter 5. g is an output from the counter 5 and h is a signal for resetting the counter 5. Here, the AND circuit 4 and the counter 5 constitute a counter circuit.

FIG. 4 is a view showing a test result (pass / fail map image) corresponding to the IC socket arrangement on the burn-in board. In the figure, f indicates a fail display, p indicates a pass display, and the fail display f indicates that the output e of the data holding circuit 3 is “H (High level)”.
, And the path display p is displayed when the output e of the data holding circuit 3 is “L (Low level)”. The operation of the circuit in the case of the test result in the pass / fail map shown in FIG. 4 is shown in FIGS. 5A and 5B, and the operation will be briefly described. FIG. 5 is a timing chart of the I / O direction continuous failure detection circuit, and FIG.
FIG. 5 (b) shows the I / O5 from 0 to 4. FIG.
Then, since it is a burn-in board 20 of 6 columns × 6 rows,
I / O is I / O0-5, SCAN signal is SCAN0-5
Are wired.

When attention is paid to I / O0, since SCAN0 fails, a one-shot pulse signal e is input to the counter 5 at the end of SCAN0, and one is counted up. Similarly, since all of SCAN1 to SCAN5 fail, the counter value of I / O0 at the end of SCAN5 is 6. Here, by setting the preset value of the counter 5 to 6 in advance, at the end of the SCAN 5, the counter 5 outputs an "H" signal g meaning that the preset value has been reached.

When this counter value reaches the preset value, the output "H" from the counter 5 is output to line 1 of I / O0.
By recognizing as an alarm signal g meaning that all of the ICs to be tested in the row are failed, I /
It can be used as an alarm generation signal that a line defect has occurred for each O line, and a line defect can be detected.

As shown in FIG. 5A, I / O1 to I / O4 are the same as I / O0. Further, as shown in FIG. 5B, since the I / O 5 has the path display p in the column E, the counter 5 is reset at that time, and the final counter value becomes 1. The counter value is cleared when a pass is determined and at the start of each test.

(Embodiment 2) FIG. 2 is a block diagram showing a block / line defect detection circuit in the SCAN direction according to Embodiment 2 of the present invention.

FIG. 2 shows a second embodiment of the present invention.
The block (line) failure detection circuit in the CAN direction is provided by I /
It comprises a plurality of determination units 1o to 1n O0 to n and a counting unit 6.

Each of the determination units 1o to 1n determines the I / O of the IC under test.
A comparison circuit 2 for comparing the O output a with the expected value b; a data holding circuit 3 for taking in the output d of the comparison circuit 2 at the rising timing of the strobe signal c;
And an AND circuit 4 for generating a one-shot pulse by using the strobe signal c when the output e of the signal is "H".

The counting unit 6 counts when an error occurs in one column in the SCAN direction by using an AND circuit 6a for ANDing the outputs fo to fn of the respective AND circuits 4 from I / Oo to I / On and an output k from the AND 6a. Up counter 6d
And an AND circuit 6b and a holding circuit 6c for generating a reset signal for the counter 6d. Where AN
A counter circuit is configured by the D circuit 6a and the counter 6d.

Next, the operation of the circuit in the case of the test result in the pass / fail map shown in FIG. 4 is shown in FIG. 6, and the operation will be briefly described. FIG. 6 shows a timing chart of the SCAN direction continuous failure detection circuit.

Considering the same as in the case of the I / O direction, SC
In AN0, outputs fo... F of AND circuits 4 of I / Os 0 to 5
A one-shot pulse signal is output to n. I / O0
When the outputs fo... Fn of all of the AND circuits 4 to 5 are input to the AND circuit 6a, the one-shot pulse signal k is obtained only when all the I / Os 0 to 5 to be tested are in the fail display f.
Is output from the AND circuit 6a, and the output is
By inputting to d, if all of the I / Os 0 to 5 are in the fail display f, the count is incremented.

The count is incremented as the scan proceeds to SCAN1, SCAN2, SCAN3, and SCAN4.
Since the IC under test in the column is the path display p, the counter value is cleared. For example, if the preset value of the counter 6d is set to 3, SCAN2 is completed when SCAN2 ends.
A signal counter output "H" having a meaning of occurrence of a block failure in three columns in the direction is output, and by using this as an alarm signal g, a block failure can be detected. Also, by arbitrarily changing the preset value,
Block defects of the entire burn-in board can be detected from one row in the SCAN direction.

The timing for resetting the counter 6d is as follows.
There are a case where all C are not in fail display and a case where a reset signal is used at the start of each test.

By removing the AND circuit 6b and the holding circuit 6c in FIG. 2, the timing for resetting the counter 6d is only at the start of each test, and at the end of each test, all the ICs under test in one row in the SCAN direction per burn-in board are defective. The value of the column where the error occurred will remain. Also in this case, by arbitrarily setting the preset value of the counter 6d, it is possible to generate an alarm and detect a line defect in an arbitrary column.

The first and second embodiments are for detecting the occurrence of a line / block failure while each test item is being executed. However, by providing a counter for each IC under test, An example in which it is possible to detect the failure of the above will be described below.

(Embodiment 3) The embodiment 3 of the present invention shown in FIG.
It is a circuit that detects each time. The configuration of the circuit shown in FIG. 3 differs from the circuit of the first embodiment only in that a counter 5 is provided for each IC under test. The operation of the circuit is the same as that of the first embodiment, and the counter output g becomes “H” when any of the counters for each IC under test reaches a preset value. FIG. 7 shows the operation of the counter and the state of the counter value.

(Embodiment 4) As an embodiment 4, an identification number (hereinafter, referred to as a burn-in board ID) assigned to each burn-in board is used to burn-in information (fail count number in this case) for each burn-in board. A method of detecting a defect through an IC socket on a burn-in board by storing it in a device (or a server if the burn-in device is connected to a network) will be described.

The fact that the IC under test at a specific position is continuously determined to be defective may be a failure of the IC socket at the corresponding location. Thus, a burn-in board failure detection circuit will be described with reference to FIG. 3 as an example capable of detecting a burn-in board failure.

In this embodiment, if each test in the test program fails, the count is incremented.
If it is a pass, it will not be counted up or cleared.

At the end of the test, the value of the counter is written in the information file for each burn-in board ID. A limit value is set in the system of the device for the value written in this information file, and an alarm is issued when the value written in the information file reaches the limit value, so that an arbitrary burn-in board can be set. Continuous defects across lots can be detected.

(Fifth Embodiment) As a fifth embodiment, an example in which the timing of counting up the fail is changed from a test item to each test program will be described. The accuracy of burn-in board defect detection can be increased each time the test program is started by the counter reset signal h in FIG. FIG. 7 shows the operation of the counter and the counter value.

[0043]

As described above, according to the present invention, the burn-in device, the burn-in board abnormality or the abnormality of the IC under test is detected at an early stage, and unnecessary burn-in time can be reduced and defective due to erroneous determination caused by the abnormality. The erroneously determined IC can be relieved.

The burn-in is usually performed for several to several tens of hours, and the present invention can greatly reduce the dead time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an I / O direction continuous failure detection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a SCAN direction continuous failure detection circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a burn-in board failure detection circuit according to Embodiments 3, 4, and 5 of the present invention.

FIG. 4 is a diagram showing a tool (path / fail map) for displaying test results in a burn-in board layout image.

FIG. 5 is a diagram showing a timing chart of the I / O direction continuous failure detection circuit.

FIG. 6 is a diagram showing a timing chart of the SCAN direction continuous failure detection circuit.

FIG. 7 is a diagram illustrating an operation of a counter and a counter value according to the third and fourth embodiments of the present invention.

FIG. 8 is a diagram showing an example of a signal connection form in a burn-in board.

FIG. 9 is a block diagram showing a burn-in device according to a conventional example.

FIG. 10 is a block diagram illustrating a determination unit in a burn-in device according to a conventional example.

[Explanation of symbols]

 1 judgment unit 2 comparison circuit 3 data holding circuit 4 AND circuit 5 counter 6 counting unit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/26 J01L 21/66

Claims (3)

(57) [Claims] A comparison circuit; a data holding circuit;
A burn-in apparatus having a burn-in board , wherein the comparison circuits are arranged in rows and columns on a burn-in board.
Semiconductor integrated circuit to be connected to the mounted IC socket
The data holding circuit compares the output signal from the comparator with expected data.
In the counter circuit, each signal line is commonly tested.
There is a row of IC sockets connected to the semiconductor integrated circuit
Semiconductor integrated circuit under test in any one row (or row)
Counts circuit failures, all are determined to be defective and one row
When the number of failures (or rows) reaches the reset value
In addition, by generating an alarm signal,
Or burn-in apparatus for detecting continuous failures in the burn-in apparatus. 2. A data holding circuit comprising : a strobe signal;
The output of the comparison circuit is taken at the
The burn-in device according to claim 1 , wherein the burn-in device is installed. 3. The data holding circuit according to claim 2 , wherein
When the output of the road is High, the strobe signal is used to
An AND circuit for generating a one-shot pulse;
A one-shot pulse is generated at the output of the AND circuit.
A counter that counts at the rising edge when
The burn-in device according to claim 1 , wherein the burn-in device is constituted by: