JP3062678B2 - Waveform output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform output circuit for outputting an acoustic waveform or the like.

[0002]

2. Description of the Related Art Conventionally, a circuit as shown in FIG. 8 has been known as a speaker driving circuit having high sound generation efficiency capable of obtaining a large output even when a power supply voltage is low.

[0003] The waveform data generation circuit WDG is configured using an audio signal synthesis processing circuit, a tone generation circuit, and the like, and generates n-bit digitally expressed waveform data. This waveform data is represented by a complement as shown in FIG. 9. The most significant bit (MSB) is a sign bit, and the other (n-1) bits are amplitude data representing the amplitude value of the waveform. It has become. When the waveform data is negative (MSB = 1), the complement circuit CMP outputs data obtained by converting (n-1) -bit input data into a complement, and when the waveform data is positive (MSB = 0), the input data remains unchanged. Output. The D / A converter DAC1 performs D / A conversion only on the positive side of the waveform data.
The converter DAC2 performs D / A conversion only on the negative side of the waveform data. The drive circuit DR includes a D / A converter D
The speaker SP is driven by receiving output signals from the AC1 and the DAC2.

When the waveform data is positive (MSB = 0), the transistor TR1 is turned on and the transistor TR2 is turned off.
Is amplified by the transistor TR3 and output from the speaker SP. When the waveform data is negative (M
In SB = 1), the transistor TR2 is turned on and the transistor TR1 is turned off, so that the output signal of the DA converter DAC2 is amplified by the transistor TR4 and output from the speaker SP. in this way,
When the waveform data is positive and when the waveform data is negative, the currents flowing through the speaker SP are in opposite directions, and a class B push-pull output with good sounding efficiency is obtained.

[0005]

In recent years, as electronic devices have been required to have higher added value, the situations in which sound generating LSIs are used have been diversified. For example, a speech synthesis LSI and a melody generation LSI may be used in parallel,
In order to increase the number of simultaneous sounds of a melody, various uses are made, such as simultaneous sounding of a plurality of LSIs for a melody or connection to other audio equipment. In such a case, it is necessary to use a class A output signal. To obtain a class A output signal using the circuit shown in FIG.
It is necessary to connect a current-voltage conversion circuit using four transistors as shown in FIG. Therefore, there has been a problem that the miniaturization and cost reduction of the circuit are hindered.

It is an object of the present invention to provide a waveform output device which can normally obtain a class B push-pull output and can obtain a class A output by adding a simple circuit.

[0007]

SUMMARY OF THE INVENTION A waveform output circuit according to the present invention generates a digitally expressed waveform data consisting of a sign bit indicating a polarity and amplitude data, and a selecting means for selecting a first mode or a second mode. Waveform data generating means, and first and second D / A converters for D / A converting the waveform data
/ A conversion means, and the first mode is selected when the sign bit of the waveform data is positive when the first mode is selected.
The D / A converter is operated to convert the amplitude data of the waveform data as a positive analog signal,
When the D / A conversion circuit is deactivated and the sign bit of the waveform data is negative, the second D / A conversion means is operated to convert the amplitude data of the waveform data as a negative analog signal and to perform the first D / A conversion. When the A conversion circuit is in a non-operating state and the second mode is selected by the selection means, only the first D / A conversion means of the first and second D / A conversion means is operated and the amplitude of the waveform data is increased. Control means for converting the waveform data obtained by adding the sign bit to the data to always output a positive analog signal irrespective of the polarity of the waveform data; and when the first mode is selected , the sign bit becomes positive. Above
A current flows in a certain direction based on the output of the first D / A conversion means.
When the sign bit is negative, the second D / A conversion
A current flowing in a direction opposite to the above direction based on the output of the means B
A drive circuit for generating a class push-pull output, and an output terminal for generating a class A output based on the output of the first D / A converter when the second mode is selected.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment will be described below with reference to FIGS.

FIG. 1 is a diagram showing a waveform output circuit according to an embodiment.

The waveform data generation circuit WDG generates digitally represented waveform data by digitally processing an audio signal, and corresponds to a voice signal synthesis processing circuit, a musical sound generation circuit, and the like. The n-bit digital waveform data generated from the waveform data generation circuit WDG is represented by a complement (2's complement (2's complement) or 1's complement (1's complement)). However, in this embodiment, it is assumed that the complement is represented by one's complement.In the following, in this embodiment, the complement means the one's complement unless otherwise specified.) (MSB) is a sign bit, and the other (n-1) bits are amplitude data representing the amplitude value of the waveform (see FIG. 3).

The complement circuit CMP has a waveform data generation circuit W
When (n-1) -bit amplitude data from the DG is input, and when the enable signal EN3 input to the control terminal is a logical value "1", data obtained by converting the input data into a complement representation is output, and the enable signal EN3 is output. When the logical value is "0", the input data is output as it is.

The D / A converter DAC1 is an n-bit current addition type D / A converter, and includes a plurality of switch circuits SA1 to SAn and a plurality of current sources IA1 to IA.
It consists of n. That is, the current sources IA1 to IA
n is weighted from 20 to 2n-1 respectively.
The current corresponding to the on / off state of the switch circuits SA1 to SAn (the on state when the logical value of the control terminal is "1" and the off state when the logical value of the control terminal is "0") is supplied from the D / A converter DAC1. Is output.

The D / A converter DAC2 has (n-1)
This is a bit current addition type D / A converter, and includes a plurality of switch circuits SB1 to SBn and a plurality of current sources IB1 to IB1.
IBn. This D / A converter DAC
The basic configuration of D / A converter DAC1 is the same as that of D / A converter DAC1 except that the configuration is (n-1) bits.

The selection switch SEL selects the mode of the waveform output circuit. When the selection switch SEL is in the off state (output is a logical value "0"), the first mode is selected, and in the on state (output is a logical value "1"). "), The second mode is selected. When the first mode is selected, the D / A converter DAC1 or the D / A converter DA1 depends on the polarity of the waveform data generated from the waveform data generation circuit WDG.
C2 is in an operating state, and a class B push-pull output can be obtained by connecting a circuit as shown in FIG. 2, for example. When the second mode is selected, a class A output can be obtained from the D / A converter DAC1 regardless of the polarity of the waveform data generated from the waveform data generation circuit WDG. As the selection switch SEL, an external manual switch may be used, or an internal switch such as a transistor may be used.

Next, the operation of the embodiment will be described with reference to FIGS.

First, the operation in the case where the first mode is selected by the selection switch SEL and a class B push-pull output is obtained will be described with reference to FIGS.

Since the selection switch SEL is in the off state, its output logic value is "0". Hereinafter, the case where the complemented waveform data (consisting of n bits) output from the waveform data generation circuit WDG is positive (when the most significant bit (MSB) of the waveform data, that is, the sign bit is 0 (MSB = 0)) The description will be made separately for the case of negative (MSB = 1).

First, when the waveform data is positive (MSB =
Operation 0) will be described. In this case, the enable signal EN2 input to one of the terminals of the AND gates GB1 to GBn-1 becomes "0", so that the D / A converter DAC2 is in a non-operating state. On the other hand, AND gate G
Since the enable signal EN1 input to one of the terminals A1 to GAn-1 is "1", the D / A converter DAC
1 is in the operating state. In the complement circuit CMP, the enable signal EN3 input to the control terminal thereof becomes “0”, so that the complement data of the (n−1) -bit complemented amplitude data from the waveform data generation circuit WDG is output from the complement circuit CMP. It is output (see FIGS. 3 and 4A). These (n-1) -bit complemented amplitude data DA
Since 1 to DAn-1 are input to the control terminals of the switch circuits SA1 to SAn-1 through the other terminals of the AND gates GA1 to GAn-1, the amplitude data DA1 expressed in complements is input.
The on / off states of the switch circuits SA1 to SAn-1 are determined according to .DELTA.DAn-1. Also, since one terminal of the AND gate GAn is always "0", the switch circuit S
An is always off. Therefore, D / A
From the output terminal OUT1 of the converter DAC1, an analog signal corresponding to (n-1) -bit complemented amplitude data from the waveform data generation circuit WDG is output.

Next, when the waveform data is negative (MSB =
The operation 1) will be described. In this case, the enable signal EN1 input to one of the terminals of the AND gates GA1 to GAn-1 becomes "0", so that the D / A converter DAC1 is in a non-operating state. On the other hand, AND gate GB
Since the enable signal EN2 input to one of the terminals 1 to GBn-1 becomes "1", the D / A converter DAC2
Is in the operating state. In the complement circuit CMP, the enable signal EN3 input to the control terminal thereof becomes "1", so that the complement circuit CMP further outputs (n-1) -bit complemented amplitude data from the waveform data generation circuit WDG. The complemented amplitude data is output. Therefore, data representing the absolute value of the waveform data is output from the complement circuit CMP (FIGS. 3 and 4B).
reference). These (n-1) -bit amplitude data DB1 to DBn-1 expressed in absolute values are provided by AND gates GB1 to GB1.
Switch circuits SB1 to SB1 through the other terminal of GBn-1.
Bn-1 is input to the control terminal of the switch circuit SB according to the amplitude data DB1 to DBn-1 expressed in absolute values.
The on / off states of 1 to SBn-1 are determined. Therefore, D
From the output terminal OUT2 of the / A converter DAC2, an analog signal corresponding to data obtained by converting (n-1) -bit complemented amplitude data from the waveform data generation circuit WDG into an absolute value is output. Become.

As described above, when the first mode is selected by the selection switch SEL, the complemented n-bit waveform data (sign bit and (n−1)) output from the waveform data generation circuit WDG are output. ) Bit amplitude data (see FIG. 3) is output from the D / A converter DAC1 as a positive analog signal when the polarity is positive (see FIG. 4A), and when the polarity is negative. The signal is output from the D / A converter DAC2 as a negative analog signal (see FIG. 4B). Therefore, a class B push-pull output can be obtained by connecting the waveform output circuit shown in FIG. 1 to the drive circuit DR shown in FIG. Less than,
The operation in this case will be described.

When the waveform data is positive (MSB = 0), the transistor TR1 shown in FIG. 2 is turned on and the transistor TR2 is turned off. Therefore, the output terminal O of the DA converter DAC1 shown in FIG.
The signal from UT1 is amplified by transistor TR3 and output from speaker SP. When the waveform data is negative (MSB = 1), the transistor TR shown in FIG.
2 is turned on, and the transistor TR1 is turned off. Therefore, the DA converter DAC shown in FIG.
2 from the output terminal OUT2 of the transistor TR4
And amplified by the speaker SP. As described above, the current flowing through the speaker SP is opposite to each other when the waveform data is positive and when the waveform data is negative, so that a class B push-pull output with high sound generation efficiency can be obtained.

Next, the operation when the second mode is selected by the selection switch SEL and a class A output is obtained will be described.
This will be described with reference to FIGS. 1, 3, and 5.

Since the selection switch SEL is in the ON state, its output logic value is "1". Therefore, the enable signal EN1 input to one terminal of the AND gates GA1 to GAn-1 and the AND gate GAn
Is always "1", so that the D / A converter DAC1 is in the operating state. In the complement circuit CMP, the enable signal EN3 input to the control terminal of the complement circuit CMP is always "0".
1) The amplitude data represented by the complement of bits is output as it is (see FIG. 3). The other terminal of the AND gate GAn has a logical value "1" when the waveform data is positive (MSB = 0), and has a negative value (MSB =
1) has a logical value "0". Therefore, the data DA input to the other terminals of the AND gates GA1 to GAn
1 to DAn are as shown in FIG. 5, and these data DA1 to DAn are directly input to the control terminals of the switch circuits SA1 to SAn. That is, the data input to the control terminals of the switch circuits SA1 to SAn (see FIG. 5) always takes a positive value in absolute value expression regardless of the polarity of the waveform data generated from the waveform data generation circuit WDG. . Therefore, a positive analog signal is always output from the D / A converter DAC1, and a class A output can be obtained from the terminal OUT1. in this case,
By connecting the resistor R0 and the capacitor C0, the terminal OUT
The signal may be extracted from the third signal.

As described above, the second selection switch SEL
By selecting a mode, a class A output can be obtained. Therefore, as shown in FIG. 6, the outputs of the plurality of waveform output circuits shown in FIG. 1 are connected to each other, or as shown in FIG.
Can be easily connected to the outputs of the other waveform output circuits and the like.

In the above embodiment, the DA converter D
AC1 and DAC2 used current addition type,
Other DA converters such as a ladder resistance type may be used.

In the above embodiment, a current mirror or an amplifier having a high input impedance may be connected to the outputs of the DACs DAC1 and DAC2 in order to prevent the output potentials of the DACs DAC1 and DAC2 from fluctuating.

[0027]

In the invention according to the present invention, a class B push-pull output is normally obtained, and A is obtained by simply adding a simple circuit.
Since a waveform output device capable of obtaining a class output can be obtained, it is possible to reduce the size and cost of the circuit. Therefore, it is possible to easily connect a plurality of outputs of a plurality of waveform output circuits or to connect outputs of a waveform output circuit and other waveform output circuits.

[Brief description of the drawings]

FIG. 1 is a diagram showing a waveform output circuit according to an embodiment of the present application.

FIG. 2 is a diagram showing a circuit for driving a speaker using a B-type push-pull output obtained by the circuit shown in FIG. 1;

FIG. 3 is a diagram for explaining the operation of the waveform output circuit shown in FIG. 1;

FIG. 4 is a diagram for explaining the operation of the waveform output circuit shown in FIG.

FIG. 5 is a diagram for explaining the operation of the waveform output circuit shown in FIG.

FIG. 6 is a diagram showing a configuration example of a sound generator using an A-type output obtained by the circuit shown in FIG. 1;

FIG. 7 is a diagram showing a configuration example of a sound generator using an A-type output obtained by the circuit shown in FIG. 1;

FIG. 8 is a diagram showing a waveform output circuit according to a conventional example.

9 is a diagram for explaining the operation of the waveform output circuit shown in FIG.

FIG. 10 is a diagram showing a circuit for obtaining a class A output using the circuit shown in FIG. 8;

[Explanation of symbols]

SEL ... Selecting means WDG ... Waveform data generating means DAC1 ... First D / A converting means DAC2 ... Second D / A converting means CC ... Control means DR ... Drive circuit OUT3 ... Output terminal

Claims (1)

(57) [Claims] A selecting means for selecting a first mode or a second mode; a waveform data generating means for generating digitally expressed waveform data comprising a sign bit indicating a polarity and amplitude data; First and second D / A for A conversion
Converting means, when the first mode is selected, when the sign bit of the waveform data is positive, operates the first D / A converting means to convert the amplitude data of the waveform data as a positive analog signal; The second D / A conversion circuit is deactivated, and when the sign bit of the waveform data is negative, the second D / A conversion means is operated to convert the amplitude data of the waveform data as a negative analog signal. The 1D / A conversion circuit is deactivated, and when the second mode is selected by the selection means, only the first D / A conversion means of the first and second D / A conversion means is operated to generate the waveform data. Control to convert the waveform data obtained by adding the sign bit to the amplitude data of, and always output a positive analog signal regardless of the polarity of the waveform data Means, and when the first mode is selected , the code code
When the value is positive, the output of the first D / A conversion means is used.
Current in a certain direction, and the above sign bit is negative
The direction and the direction based on the output of the second D / A conversion means.
Is a drive circuit that generates a class B push-pull output that allows current to flow in the reverse direction; and the first D / D when the second mode is selected.
An output terminal for generating a class A output based on the output of the A conversion means.