JP3060611B2 - Differential amplifier circuit with built-in low-pass filter - Google Patents

Differential amplifier circuit with built-in low-pass filter

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Publication number
JP3060611B2
JP3060611B2 JP3171303A JP17130391A JP3060611B2 JP 3060611 B2 JP3060611 B2 JP 3060611B2 JP 3171303 A JP3171303 A JP 3171303A JP 17130391 A JP17130391 A JP 17130391A JP 3060611 B2 JP3060611 B2 JP 3060611B2
Authority
JP
Japan
Prior art keywords
resistor
input terminal
capacitor
operational amplifier
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3171303A
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Japanese (ja)
Other versions
JPH0522077A (en
Inventor
聡 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
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Priority to JP3171303A priority Critical patent/JP3060611B2/en
Publication of JPH0522077A publication Critical patent/JPH0522077A/en
Application granted granted Critical
Publication of JP3060611B2 publication Critical patent/JP3060611B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、CD(コンパクトディ
スク)オーディオ装置に適用して好適なローパスフィル
タ内蔵差動増幅回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit with a built-in low-pass filter suitable for use in a CD (compact disk) audio device.

【0002】[0002]

【従来の技術】近時、多用される1ビットデジタル・ア
ナログコンバータ(以下、1bitDACと記載する)
等のPWM(パルス幅変調)回路の後段の差動入力回路
には、平均化(積分)アナログ信号を得るための、抵抗
器R、コンデンサCからなる積分回路と、演算増幅器を
用いた差動増幅回路と、同様に演算増幅器を用いたノイ
ズ除去用のローパスフィルタ(以下、必要に応じてLP
Fと記載する)が設けられるのが一般的である。
2. Description of the Related Art Recently, frequently used 1-bit digital-to-analog converters (hereinafter referred to as 1-bit DACs) have been used.
The differential input circuit at the subsequent stage of the PWM (pulse width modulation) circuit includes an integrating circuit including a resistor R and a capacitor C for obtaining an averaged (integrated) analog signal, and a differential circuit using an operational amplifier. An amplifier circuit and a low-pass filter for noise removal using an operational amplifier (hereinafter referred to as LP
F) is generally provided.

【0003】[0003]

【発明が解決しようとする課題】ところで上記従来例の
差動増幅回路をCDオーディオ装置に利用する場合、最
低でも差動増幅器およびLPFに用いる二つの演算増幅
器が必要である。この場合、部品数が多くなり、構成が
複雑化して製造コストが嵩み、さらに製造工程における
不良率が上昇するという不都合がある。また信号処理規
模も大きくなり消費電流が増大してしまう。
When the above-described conventional differential amplifier circuit is used for a CD audio device, at least two differential amplifiers and two operational amplifiers for LPF are required. In this case, the number of parts is increased, the configuration is complicated, the manufacturing cost is increased, and the defective rate in the manufacturing process is increased. In addition, the scale of signal processing increases, and the current consumption increases.

【0004】本発明は上述の点に鑑みてなされ、演算増
幅器の数が低減し、その構成が簡素化されるととともに
信号処理規模が縮小されて、消費電流が低減できる優れ
たLPF内蔵差動増幅回路を提供することを目的とす
る。
The present invention has been made in view of the above points, and has an excellent differential with a built-in LPF capable of reducing the number of operational amplifiers, simplifying the configuration, reducing the scale of signal processing, and reducing current consumption. It is an object to provide an amplifier circuit.

【0005】[0005]

【課題を解決するための手段】一方の入力端子(Ti1
を第1及び第2の抵抗器(R1 ,R3 )の直列回路を介
して演算増幅器(2)の非反転入力端に接続し、上記第
1及び第2の抵抗器(R1 ,R3 )の接続点を第1のコ
ンデンサ(C1 )を介して上記演算増幅器(2)の出力
端に接続し、上記演算増幅器(2)の非反転入力端を第
3の抵抗器(R 5 )及び第2のコンデンサ(C3 )の並
列回路を介して接地すると共に他方の入力端子(Ti2
を上記第1の抵抗器(R1 )と抵抗値の等しい第4の抵
抗器(R 2 )及び上記第2の抵抗器(R3 )と抵抗値の
等しい第5の抵抗器(R4 )の直列回路を介して上記演
算増幅器(2)の反転入力端に接続し、上記第4及び第
5の抵抗器(R2 ,R4 )の接続点を上記第1のコンデ
ンサ(C1 )と容量値の等しい第3のコンデンサ
(C2 )を介して接地し、上記演算増幅器(2)の反転
入力端を上記第3の抵抗器(R5 )と抵抗値の等しい第
6の抵抗器(R6 )及び上記第2のコンデンサ(C3
と容量値の等しい第4のコンデンサ(C4 )の並列回路
を介して上記演算増幅器(2)の出力端に接続し、増幅
率、遮断周波数及びQ値を定めて上記各抵抗器及びコン
デンサの大小関係を決定するようにしたことを特徴とす
るローパスフィルタ内蔵差動増幅回路。
Means for Solving the Problems One input terminal (T)i1)
To the first and second resistors (R1, RThreeVia a series circuit)
And connected to the non-inverting input terminal of the operational amplifier (2).
The first and second resistors (R1, RThree) To the first connector
Capacitor (C1) Via the output of the operational amplifier (2)
Terminal of the operational amplifier (2).
3 resistors (R Five) And a second capacitor (CThreeAverage)
Ground via the column circuit and the other input terminal (Ti2)
To the first resistor (R1) And a fourth resistor having the same resistance value.
Anti-arm (R Two) And the second resistor (RThree) And the resistance value
An equal fifth resistor (RFour) Through the series circuit
Connected to the inverting input terminal of the operational amplifier (2).
5 resistors (RTwo, RFour) Is connected to the first condenser
Sensor (C1) And a third capacitor having a capacitance value equal to
(CTwo) To ground, and invert the operational amplifier (2)
Connect the input terminal to the third resistor (RFive) And the resistance value is equal
6 resistors (R6) And the second capacitor (CThree)
And a fourth capacitor (CFour) Parallel circuit
Connected to the output terminal of the operational amplifier (2) through
Rate, cut-off frequency and Q value, and
The feature is to determine the size relationship of DENSA
Low-pass filter built-in differential amplifier circuit.

【0006】[0006]

【作用】本発明のLPF内蔵差動増幅回路によれば、差
動増幅器に正帰還をかけた抵抗器およびコンデンサから
なるアクティブLPFが設けられているため、従来、こ
のLPFを構成していた演算増幅器が不要になり、その
演算増幅器の数が低減して、構成が簡素化されるととも
に信号処理規模が縮小して消費電流が低減できる。
According to the differential amplifier circuit with a built-in LPF of the present invention, the differential amplifier is provided with an active LPF comprising a resistor and a capacitor to which positive feedback is applied. The need for an amplifier is eliminated, the number of operational amplifiers is reduced, the configuration is simplified, the signal processing scale is reduced, and the current consumption can be reduced.

【0007】[0007]

【実施例】以下、本発明のLPF内蔵差動増幅回路の一
実施例について図面を参照して説明する。図1は第1の
実施例の構成を示している。この例は、入力信号(電
圧)VA が入力端子Ti1に接続された抵抗器R1の一端
に供給される。この抵抗器R1 の他端に抵抗器R3 の一
端が接続されるとともに、抵抗器R3 の他端が演算増幅
器2の正極入力端(+非反転入力端)に接続されてい
る。抵抗器R1 と抵抗器R3 との接続点にコンデンサC
1 の一端が接続され、この他端が演算増幅器2の出力端
に接続されている。さらに、演算増幅器2の正極入力端
(+)に、並列接続した抵抗器R5 とコンデンサC3
夫々の一端が接続され、夫々の他端が接地されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the differential amplifier circuit with a built-in LPF of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the first embodiment. In this example, the input signal (voltage) V A is supplied to the one end connected to the resistor R 1 to the input terminal T i1. One end of the resistor R 3 is connected to the other end of the resistor R 1, the other end of the resistor R 3 is connected to the positive input terminal of the operational amplifier 2 (+ non-inverting input terminal). Capacitor C to a connection point between the resistor R 1 and the resistor R 3
1 is connected to one end, and the other end is connected to the output terminal of the operational amplifier 2. Further, the arithmetic positive input terminal of the amplifier 2 to the (+), one end of each of the resistor R 5 and capacitor C 3 connected in parallel is connected, the other end of each is grounded.

【0008】入力信号(電圧)VB が入力端子Ti2に接
続された抵抗器R2 の一端に供給されている。この抵抗
器R2の他端に抵抗器R4 の一端が接続されるとともに
抵抗器R4 の他端が演算増幅器2のマイナス(−反転入
力端)入力端に接続されている。抵抗器R2 と抵抗器R
4 との接続点にコンデンサC2 の一端が接続され、さら
に他端が接地されている。また、演算増幅器2のマイナ
ス入力端に、並列接続した抵抗器R6 とコンデンサC4
の夫々の一端が接続され、さらに夫々の他端が演算増幅
器2の出力端に接続されている。この出力端から入力端
子TO を通じて出力信号(電圧)VO が得られる。
An input signal (voltage) V B is supplied to one end of a resistor R 2 connected to an input terminal T i2 . The resistor R 2 at the other end to a resistor minus the other end of the resistor R 4 is an operational amplifier 2 with one end of the R 4 is connected - is connected to the (inverting input terminal) input. Resistor R 2 and resistor R
4 is connected to one end of the capacitor C 2 to the connection point of the further other end is grounded. A resistor R 6 and a capacitor C 4 connected in parallel to the minus input terminal of the operational amplifier 2 are connected.
Are connected to one another, and the other ends are connected to the output terminal of the operational amplifier 2. An output signal (voltage) V O is obtained from the output terminal through the input terminal T O.

【0009】次に、第1の実施例における動作について
説明する。ここで、各抵抗器(R1 乃至R6 )コンデン
サ(C1 乃至C4 )の関係を、R 1 =R2 =RA 、R3
=R4 =RB 、R5 =R6 =RC 、C1 =C2 =CA
3 =C4 =CB 、Sは複数変数(ラプラス演算子)と
し、この場合の各接点において節点方程式を立て、ラプ
ラス変換を行い伝達関数を求めると、この伝達関数は、
Next, the operation in the first embodiment will be described.
explain. Here, each resistor (R1Or R6) Conden
Sa (C1Or CFour) Is R 1= RTwo= RA, RThree
= RFour= RB, RFive= R6= RC, C1= CTwo= CA,
C Three= CFour= CB, S are multiple variables (Laplace operator)
In this case, a nodal equation is established at each contact point,
When a transfer function is obtained by performing a Lath transform, this transfer function is

【0010】[0010]

【数1】 (Equation 1)

【0011】で表される。この(数1)は、次に示す一
般の2次のLPFの式で表わされる。
## EQU1 ## This (Equation 1) is expressed by the following general second-order LPF equation.

【0012】[0012]

【数2】 (Equation 2)

【0013】上記式においてIn the above equation,

【0014】[0014]

【数3】 (Equation 3)

【0015】となり、そのQ値は、And the Q value is

【0016】[0016]

【数4】 (Equation 4)

【0017】となる。## EQU1 ##

【0018】このように、抵抗器R1 と抵抗器R2 、抵
抗器R3 と抵抗器R4 および抵抗器R5 と抵抗器R6
夫々等しい抵抗値にし、さらにコンデンサC1 とコンデ
ンサC2 、コンデンサC3 とコンデンサC4 を夫々等し
い容量とする正帰還アクティブLPFが演算増幅器2に
設けられて、この回路の増幅率、遮断周波数およびQ値
を定めて、各素子の大小値関係を決定している。
As described above, the resistors R 1 and R 2 , the resistors R 3 and R 4, the resistors R 5 and R 6 have the same resistance, and the capacitors C 1 and C 6 have the same resistance. 2, a positive feedback active LPF is provided to the operational amplifier 2 to the capacitor C 3 and the capacitor C 4 and respectively equal capacity, the amplification factor of this circuit, defining a cutoff frequency and Q value, the magnitude value relationship of the elements I have decided.

【0019】この場合、従来LPFを構成していた演算
増幅器の数が低減し、その構成が簡素化されるとととも
に信号処理規模が縮小されて消費電流が減少することに
なる。
In this case, the number of operational amplifiers that have conventionally constituted the LPF is reduced, the structure is simplified, and the scale of signal processing is reduced, so that the current consumption is reduced.

【0020】図2は、第2の実施例の構成を示してい
る。この例は、例えば、CDオーディオ装置に適用する
場合の実施例であり、1bitDACから、入力端子T
i1,Ti2に夫々PWMプラス・マイナス信号が供給され
ている。1bitDACは時間軸方向に高精度な分解能
を有するPWM(パルス幅変調)方式を採用しており、
アナログ信号に変換する積分回路が必要である。またオ
ーバーサンプリング技術とノイズシェーピング技術を用
いて16bitのデータを数bitにbit圧縮しなが
ら量子化ノイズを可聴周波数から高周波数に形成してい
るため、ノイズ除去用のLPFが必要となる。
FIG. 2 shows the configuration of the second embodiment. This example is an example in which the present invention is applied to, for example, a CD audio device.
PWM plus / minus signals are supplied to i1 and Ti2 , respectively. The 1-bit DAC adopts a PWM (pulse width modulation) method having a highly accurate resolution in the time axis direction.
An integration circuit for converting to an analog signal is required. Also, since the quantization noise is formed from an audible frequency to a high frequency while 16-bit data is compressed into several bits by using the oversampling technique and the noise shaping technique, an LPF for noise removal is required.

【0021】このため、図2に示すように、第1の実施
例の構成(図1)の前段に、PWMプラス・マイナス信
号が入力端子Ti1、Ti2を通じて、夫々の一端に供給さ
れる抵抗器R8 、抵抗器R9 を設けるとともに、これら
の他端間にコンデンサC5 (CX )を接続した構成の積
分回路4を付加している。この場合、R8 =R9 =R X
とし、全体として3次のLPFで構成されており、演算
増幅器2から出力端子TO を通じてオーディオ出力信号
AOが出力される。
For this reason, as shown in FIG.
Before the example configuration (Fig. 1), the PWM plus / minus
Signal is input terminal Ti1, Ti2Supplied to one end of each
Resistor R8, Resistor R9Along with these
Between the other end of the capacitor CFive(CX) Connected product
A dividing circuit 4 is added. In this case, R8= R9= R X
And is composed of a third-order LPF as a whole.
Output terminal T from amplifier 2OThrough the audio output signal
VAOIs output.

【0022】次に、第2の実施例における動作について
説明する。この回路の伝達関数は、
Next, the operation of the second embodiment will be described. The transfer function of this circuit is

【0023】[0023]

【数5】 (Equation 5)

【0024】で表される。遮断周波数は、可聴周波数よ
り高く設定するため可聴帯域内での伝達関数は、
## EQU2 ## Since the cutoff frequency is set higher than the audio frequency, the transfer function in the audio band is

【0025】[0025]

【数6】 (Equation 6)

【0026】で表され、利得はRX ,RA ,RB の和と
C の比で任意に設定することができる。
The gain can be arbitrarily set by the ratio of the sum of R X , R A , and R B to R C.

【0027】このように、例えば、携帯用CDオーディ
オ装置における1bitDACからのPWMプラス・マ
イナス信号を処理する際に、積分およびノイズ除去が夫
々できることになる。この場合、回路を構成する素子数
が低減されるため信号劣化が生じ難くなり、音質が向上
するとともに消費電流ならびに部品点数が減少して小型
化および長時間使用が可能となり、携帯の利便性が向上
するものとなる。
As described above, for example, when processing a PWM plus / minus signal from a 1-bit DAC in a portable CD audio device, integration and noise removal can be respectively performed. In this case, the number of elements constituting the circuit is reduced, so that signal degradation hardly occurs, the sound quality is improved, the current consumption and the number of components are reduced, and the device can be reduced in size and used for a long time. It will improve.

【0028】[0028]

【発明の効果】上記説明から理解されるように、本発明
のLPF内蔵差動増幅回路によれば、差動増幅器に正帰
還をかけた抵抗器及びコンデンサからなるアクティブL
PFが設けられているため、演算増幅器の数が低減し、
その構成が簡素化できるととともに信号処理規模が縮小
されて、消費電流が低減できるという効果を有する。
As can be understood from the above description, according to the LPF built-in differential amplifier circuit of the present invention, the active amplifier composed of a resistor and a capacitor that apply positive feedback to the differential amplifier.
Since the PF is provided, the number of operational amplifiers is reduced,
This has the effect that the configuration can be simplified, the scale of signal processing can be reduced, and the current consumption can be reduced.

【0029】加えて、当該LPF内蔵差動増幅回路を携
帯用CDオーディオ装置等に適用する場合、回路を構成
する素子数が低減されるため信号波形の劣化が生じ難く
なり、音質が向上するとともに消費電流ならびに部品点
数が減少して小型化および長時間使用が可能となり、携
帯の利便性が向上するという効果を有する。
In addition, when the LPF built-in differential amplifying circuit is applied to a portable CD audio device or the like, the number of elements constituting the circuit is reduced, so that the signal waveform hardly deteriorates and the sound quality is improved. The current consumption and the number of components are reduced, miniaturization and long-term use are possible, and there is an effect that the convenience of carrying is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のLPF内蔵差動増幅回路の第1の実施
例の構成を示す回路図である。
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a differential amplifier circuit with a built-in LPF of the present invention.

【図2】本発明のLPF内蔵差動増幅回路の第2の実施
例の構成を示す回路図である。
FIG. 2 is a circuit diagram showing a configuration of a second embodiment of the differential amplifier circuit with a built-in LPF according to the present invention.

【符号の説明】[Explanation of symbols]

2 演算増幅器 C1 、C2 、C3 、C4 、C5 コンデンサ R1 、R2 、R3 、R4 、R5、R6 、R8 、R9
抗器 VA 、VB 入力信号(電圧) VO 出力信号(電圧)
Second operational amplifier C 1, C 2, C 3 , C 4, C 5 capacitors R 1, R 2, R 3 , R 4, R 5, R 6, R 8, R 9 resistors V A, V B input signal (Voltage) V O output signal (voltage)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 一方の入力端子を第1及び第2の抵抗器
の直列回路を介して演算増幅器の非反転入力端に接続
し、上記第1及び第2の抵抗器の接続点を第1のコンデ
ンサを介して上記演算増幅器の出力端に接続し、上記演
算増幅器の非反転入力端を第3の抵抗器及び第2のコン
デンサの並列回路を介して接地すると共に他方の入力端
子を上記第1の抵抗器と抵抗値の等しい第4の抵抗器及
び上記第2の抵抗器と抵抗値の等しい第5の抵抗器の直
列回路を介して上記演算増幅器の反転入力端に接続し、
上記第4及び第5の抵抗器の接続点を上記第1のコンデ
ンサと容量値の等しい第3のコンデンサを介して接地
し、上記演算増幅器の反転入力端を上記第3の抵抗器と
抵抗値の等しい第6の抵抗器及び上記第2のコンデンサ
と容量値の等しい第4のコンデンサの並列回路を介して
上記演算増幅器の出力端に接続し、増幅率、遮断周波数
及びQ値を定めて上記各抵抗器及びコンデンサの大小関
係を決定するようにしたことを特徴とするローパスフィ
ルタ内蔵差動増幅回路。
1. An input terminal is connected to a non-inverting input terminal of an operational amplifier via a series circuit of first and second resistors, and a connection point of the first and second resistors is connected to a first node. And a non-inverting input terminal of the operational amplifier is grounded through a parallel circuit of a third resistor and a second capacitor, and the other input terminal is connected to the other input terminal of the operational amplifier. A fourth resistor having the same resistance value as the first resistor and a fifth resistor having the same resistance value as the second resistor are connected to the inverting input terminal of the operational amplifier via a series circuit;
The connection point of the fourth and fifth resistors is grounded via a third capacitor having the same capacitance value as the first capacitor, and the inverting input terminal of the operational amplifier is connected to the third resistor and the resistance value. Connected to the output terminal of the operational amplifier via a parallel circuit of a sixth resistor having the same value and a fourth capacitor having the same value as the second capacitor, and determining the amplification factor, cutoff frequency and Q value, A differential amplifier circuit with a built-in low-pass filter, wherein the magnitude relationship between each resistor and capacitor is determined.
JP3171303A 1991-07-11 1991-07-11 Differential amplifier circuit with built-in low-pass filter Expired - Fee Related JP3060611B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3171303A JP3060611B2 (en) 1991-07-11 1991-07-11 Differential amplifier circuit with built-in low-pass filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3171303A JP3060611B2 (en) 1991-07-11 1991-07-11 Differential amplifier circuit with built-in low-pass filter

Publications (2)

Publication Number Publication Date
JPH0522077A JPH0522077A (en) 1993-01-29
JP3060611B2 true JP3060611B2 (en) 2000-07-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP3171303A Expired - Fee Related JP3060611B2 (en) 1991-07-11 1991-07-11 Differential amplifier circuit with built-in low-pass filter

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JP (1) JP3060611B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100819119B1 (en) 2006-01-09 2008-04-04 삼성전자주식회사 CMOS Amplifier of Filter for Ultra Wideband Application and Method of the Same
JP4729658B2 (en) * 2009-12-21 2011-07-20 オンキヨー株式会社 Filter circuit
JP5996017B2 (en) * 2015-03-03 2016-09-21 プライムアースEvエナジー株式会社 Voltage detection circuit

Also Published As

Publication number Publication date
JPH0522077A (en) 1993-01-29

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