JP3059361B2 - Switching power supply circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a so-called DC-D
The present invention relates to a switching power supply circuit suitably implemented in a C converter or the like.

[0002]

2. Description of the Related Art It is used in portable small electronic equipment and the like, and switches a DC current obtained by rectifying and smoothing a commercial AC or a DC current from a battery at a high frequency. A switching power supply circuit that transforms the voltage with high efficiency is widely used.

FIG. 5 is a block diagram showing an electrical configuration of a typical conventional switching power supply circuit 51 disclosed in Japanese Patent Application Laid-Open Nos. 3-270673 and 4-150764. Input AC currents from input terminals T1 and T2 connected to a commercial AC power supply or the like are rectified by a rectifier circuit 52 composed of a diode bridge or the like, then smoothed by a smoothing capacitor 53, and output between power supply lines 54 and 55. Is done. A series circuit including a primary winding 56a of a pulse transformer 56 and a switching element 57 is interposed between the power supply lines 54 and 55, and the switching element 57 is controlled to be turned on / off by a gate pulse from a control circuit 58. You. Thereby, when the switching element 57 is cut off, the secondary winding 5 of the pulse transformer 56 is turned off.
6b, an induced electromotive voltage is generated, and a current due to the electromotive voltage is:
Rectified and smoothed by a diode 59 and a smoothing capacitor 60, and output terminals T3, T
4 respectively.

A current detection resistor 63 is interposed in one of the power supply lines 61 and 62 (62 in FIG. 5), and an output current, that is, a voltage generated between terminals of the current detection resistor 63 due to a load current. Is the overcurrent detection circuit 6
4 is read. When the voltage exceeds a predetermined voltage, the overcurrent detection circuit 64 determines that an overcurrent state has occurred, derives an output to the control circuit 58, and shortens the pulse width of the gate pulse to the switching element 57. ,
That is, the duty is reduced. Such an overcurrent protection operation is performed for each gate pulse.

That is, when the drain current waveform of the switching element 57 is shown in FIG. 6A and the current waveform of the diode 59 is shown in FIG. 6B, in a rated load state before time t11, the control circuit 57 , Per cycle W11, O
The switching element 57 is conductive only for the N period W12. On the other hand, as shown after time t11,
The overcurrent state continues, and when the current level detected by the overcurrent detection circuit 64 becomes equal to or higher than a predetermined level L11 as shown at time t12, the overcurrent detection circuit 6
4 causes the control circuit 58 to shut off the switching element 57,
As a result, the ON period becomes shorter as shown by reference numerals W13 to W14, and an overcurrent state is avoided.

[0006]

However, during the ON period of the gate pulse from the control circuit 58, the control circuit 5
Due to the time required from the rise to the fall of the gate pulse in 8, and the influence of the inductance of the pulse transformer 56, it cannot be shortened below the predetermined minimum time indicated by the reference numeral W14. Therefore, when the impedance is reduced due to the secondary side being short-circuited or the like, as shown from time t13, the secondary side diode current is not fully reduced in response to the primary side drain current supply. Further, the drain current on the primary side starts to flow, and the peak value of the drain current increases, and as shown after time t14, the output impedance on the secondary side and the input impedance on the primary side become larger. From the relationship,
The rising point of the drain current on the primary side and the falling point of the diode current on the secondary side converge to a level L12 where they coincide.

Therefore, in the switching power supply circuit 51 as described above, it is necessary to provide a sufficient margin to the current rating of the switching element 57, the pulse transformer 56, the diode 59, and the like so that the current rating can correspond to the level L12. There is a problem that the cost increases.

FIG. 7 is a block diagram showing an electrical configuration of another conventional switching power supply circuit 71 capable of avoiding a long-term overcurrent state. Note that the configuration is similar to that of the switching power supply circuit 51 shown in FIG. 5, and the corresponding parts are denoted by the same reference numerals and description thereof will be omitted.

In the switching power supply circuit 71, the drain current is detected by a resistor 72 connected in series to the switching element 57. The resistance value of the resistor 72 is set corresponding to the level L11. A terminal voltage of the resistor 72 is input to a control circuit 76 via a filter circuit 75 including a resistor 73 and a capacitor 74. Is done. This prevents erroneous detection of overcurrent due to noise or the like.

However, FIG. 6A and FIG.
8 (a) and 8 (b) corresponding to (b), respectively.
As shown by, the period W15 from when the drain current of the switching element 57 becomes equal to or higher than the level L11 to when the drain current is actually cut off becomes longer due to a delay in the detection timing by the filter circuit 75. .

In this switching power supply circuit 71,
An output voltage detection circuit 77 is provided, and a detection result of the output voltage detection circuit 77 is input to an output cutoff circuit 79 via an output cutoff delay circuit 78. Output cutoff circuit 79
Detects a short circuit on the secondary side from the output voltage, and when a short circuit occurs, the control circuit 76 performs an output cutoff operation of stopping the output of the gate pulse to the switching element 57. The output cutoff delay circuit 78 is provided to prevent erroneous detection of a short circuit due to an instantaneous voltage drop on the secondary side. Therefore, the drain current of the switching element 57 is reduced as shown in FIG.
At the time point t15, the output cutoff delay circuit 78
Due to the delay of the detection result, the drain current is actually cut off after time t16.

Therefore, the switching power supply circuit 7
Even in the case of 1, the current exceeding the permissible current indicated by the level L11 flows in the output cut-off delay state between the times t15 and t16, and it is necessary to provide a margin for the current rating as described above.

An object of the present invention is to provide a switching power supply circuit capable of reducing the cost without unnecessarily increasing the current rating of a circuit element by reliably preventing an overcurrent state. That is.

[0014]

According to a first aspect of the present invention, there is provided a switching power supply circuit in which a primary current of a transformer is switched by a switching element to obtain a secondary current of a desired voltage. An overcurrent detecting means for detecting an overcurrent of the switching element;
Output voltage detection means for detecting a drop in output voltage; and control means for controlling a switching operation of the switching element, wherein when the overcurrent is detected by the overcurrent detection means, the ON period of the switching element is shortened. And
And control means for lowering the switching frequency of the switching element when the output voltage detection means detects a drop in the output voltage, and output voltage detection means.
In succession, when the output voltage falls below a predetermined voltage,
Stop switching operation of switching element by control means
Output shutoff means for causing the
The stopping of the switching operation is delayed by a predetermined delay time.
Output cut-off delay means, and the control means comprises:
The switching frequency is reduced during the delay time .

According to the above configuration, in a switching power supply circuit used as a DC-DC converter or the like, a current detection resistor provided in series with a switching element,
When the overcurrent is detected by the overcurrent detection means realized by a load current detection resistor or the like interposed in the next power supply line, the control means shortens the ON period of the switching element,
That is, the duty is reduced, and a protection operation against overcurrent is performed. Further, when the output voltage detecting means detects that the output voltage has decreased due to the overcurrent protection operation, the control means reduces the switching frequency of the switching element to decrease the output voltage.

Therefore, when the secondary side is short-circuited and the current of the switching element increases, the ON period of the switching element is first shortened, and the ON period of the ON period determined by the structure of the control means and the transformer is determined. If the overcurrent state is not avoided even in the shortest state, the switching frequency is further reduced, and the primary current and the secondary current are suppressed. As a result, the overcurrent state can be reliably avoided, and the current rating of the switching element, the transformer, the rectifying element on the secondary side, and the like does not need to be unnecessarily increased, and the cost can be reduced.

Further, the output shut-off means detects a drop in output voltage, in performing short circuit protection operation for stopping the switching operation of the switching element to the control means, provided in order to prevent a malfunction against momentary shorting During the delay operation by the output cut-off delay means, the control means lowers the switching frequency of the switching element .

Therefore, even in the delay time for preventing the malfunction, the overcurrent state can be reliably prevented.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described.
The following is a description based on FIGS. 1 to 4.

FIG. 1 is a block diagram showing an electrical configuration of a switching power supply circuit 1 according to an embodiment of the present invention. Input terminals P1 and P2 connected to a commercial AC power supply
Is rectified by a rectifier circuit 2 composed of a diode bridge or the like, is smoothed by a smoothing capacitor C1, and is output between the power supply lines 3 and 4. A primary winding 5 of a pulse transformer 5 is provided between the power supply lines 3 and 4.
a, a series circuit including a switching element Q1 composed of an N-channel type power MOSFET and a resistor R1 for detecting overcurrent is interposed, and the switching element Q1 is controlled to be turned on / off by a gate pulse from the control circuit 6. As a result, when the switching element Q1 is cut off, an induced electromotive voltage is generated in the secondary winding 5b of the pulse transformer 5, and the current caused by the electromotive voltage is rectified and smoothed by the diode D1 and the smoothing capacitor C2, and the power supply line 8 and 9 are output to output terminals P3 and P4, respectively.

The control circuit 6 includes an overcurrent detection circuit 12
, PWM comparator 13, circuit breaker 14, reference voltage source 3
3 is provided. The terminal voltage of the resistor R1 is input to the overcurrent detection circuit 12 of the control circuit 6 via the blanking circuit 11. Blanking circuit 11
Is interrupted only during a period in which noise may occur due to the switching operation of the switching element Q1 in response to a gate pulse from the control circuit 6 to the switching element Q1. Therefore, the overcurrent detection circuit 12 can accurately detect the overcurrent without performing a malfunction due to the noise.

On the other hand, the gate pulse is generated by the PWM comparator 13 as described later, and is input to the switching element Q1 via the circuit breaker 14. When the terminal voltage, that is, the drain current of the switching element Q1 becomes higher than a predetermined level, for each gate pulse, the overcurrent detection circuit 12 shuts off the circuit breaker 14 and shuts off the gate pulse to the switching element Q1. Thus, the protection operation of the switching element Q1 and the secondary circuit against overcurrent is realized.

An output voltage detection circuit 15, an output cutoff circuit 16, and an output cutoff delay circuit 17 are provided for detecting a short circuit on the secondary side. The output cut-off delay circuit 17 includes a capacitor C3 and a constant current source 21 for charging the capacitor C3.
Is input to the non-inverting input terminal of the comparator 23 of the output cutoff circuit 16.

The output cutoff circuit 16 includes the comparator 23,
It comprises a reference voltage source 24 and a power supply circuit 25. The reference voltage source 24 is connected to the inverting input terminal of the comparator 23. Therefore, as described later, the comparator 23 operates when the potential of the connection point 22 becomes higher than the reference voltage Vref1 of the reference voltage source 24. 25, and the power supply from the power supply circuit 25 to each circuit such as the control circuit 6 is stopped.

On the other hand, the output voltage detecting circuit 15 includes a phototransistor Q2, a pull-up resistor R2, a comparator 27, a reference voltage source 28, a Zener diode D3,
It comprises a transistor Q3, an output voltage error detection circuit 26 interposed on the secondary side, and a light emitting diode D2. The output voltage error detection circuit 26 controls the cathode current of the diode D2 according to the line voltage between the power lines 8 and 9. The diode D2 and the phototransistor Q2 form a pair to form a photocoupler, and the phototransistor Q2 is connected to a high-level power supply line 29 via a pull-up resistor R2.

Therefore, a feedback voltage corresponding to the output voltage on the secondary side is output from the connection point 30 between the pull-up resistor R2 and the phototransistor Q2,
Is input to the inverting input terminal. A non-inverting input terminal of the comparator 27 has a predetermined reference voltage Vre from a reference voltage source 28.
f2 is input, and its output is applied to the base of transistor Q3. The collector of the transistor Q3 is
It is connected to the connection point 22 via a Zener diode D3.

Therefore, in the steady state, the collector current of the phototransistor Q2 flows, and the potential at the node 30 is lower than the reference voltage Vref2, for example, 2.8 V, whereby the comparator 27 changes the high level to the base of the transistor Q3. And the transistor Q3 is conducting. Therefore, the charging current from constant current source 21 to capacitor C3 is bypassed, and the terminal voltage of capacitor C3 is a voltage defined by the Zener voltage of Zener diode D3 and the voltage between the emitter and collector of transistor Q3, for example, 3. It is kept at 6V. As a result, the input voltage to the inverting input terminal of the comparator 23 becomes lower than the reference voltage Vref1, for example, 7.8 V, and the comparator 23 activates the power supply circuit 25 to supply power to each circuit. I have.

On the other hand, when the output voltage decreases, the collector current of the phototransistor Q2 decreases, and the potential at the connection point 30 increases. When the potential of the connection point 30 becomes equal to or higher than the reference voltage Vref2, the comparator 27 derives a low-level output, whereby the transistor Q3 and the Zener diode D3 are cut off, and the capacitor C3 is charged by the charging current from the constant current source 21. Is started. The terminal voltage of the capacitor C3 is equal to the reference voltage Vr.
When ef1 or more, the comparator 23 deactivates the power supply circuit 25 and stops power supply to each of the circuits.

Further, the potential at the connection point 22 is input to an oscillation frequency lowering circuit 31. As will be described later, the oscillation frequency lowering circuit 31 lowers the oscillation frequency of the oscillation circuit 32 when the potential of the connection point 22 rises. The oscillation signal of the oscillation circuit 32 is based on the PWM comparator 1
3 is input to the input terminal T1. The PWM comparator 13 further has three input terminals T2, T3, and T4, and receives the potential at the connection point 22, the potential at the connection point 30, and the reference voltage Vref3 from the reference voltage source 33, respectively. The PWM comparator 13 outputs a gate pulse having the cycle of the oscillation signal from the oscillation circuit 32 and a duty corresponding to the lowest voltage among the input voltages to the input terminals T2 to T4.

FIG. 2 is an electric circuit diagram showing a specific configuration of the oscillation circuit 32 and the oscillation frequency lowering circuit 31.
The oscillation circuit 32 includes comparators 34 and 35 and constant current sources 36 and
37; 38, 39 and voltage dividing resistors R11, R12, R13
And transistors Q11, Q12, Q13, Q14,
And a capacitor C11. A series circuit of voltage dividing resistors R11 to R13 is interposed between the power supply line 40 to which the high-level voltage Vs is applied and the ground line. The connection point between the voltage dividing resistors R11 and R12 is connected to the inverting input terminal of the comparator 34 and the non-inverting input terminal of the comparator 35, respectively. An oscillation signal output to the PWM comparator 13 is input to a non-inverting input terminal of the comparator 34 and an inverting input terminal of the comparator 35. A bypass transistor Q11 is provided in parallel with the voltage dividing resistor R13.
11 is turned on / off by a comparator 34. The output of comparator 35 is provided to the base of bypass transistor Q12.

A series circuit of a constant current source 36 and a transistor Q13 is interposed between the power supply line 40 and the ground line. The constant current source 36 is also provided with a constant current source 37 in parallel. The constant current source 37 is selectively connected by a transistor Q16 in the oscillation frequency lowering circuit 31. The transistor Q13 forms a pair with the transistor Q14 to form a current mirror circuit. The bases of the transistors Q13 and Q14 are connected to the collector of the transistor Q13 and the constant current source 36 and to the collector of the bypass transistor Q12. Therefore, when the bypass transistor Q12 conducts, these transistors Q13, Q1
4 shuts off. The transistor Q14 is a capacitor C11
Is provided in parallel with the capacitor C11.
A charging current is supplied from the power supply line 40 via a constant current source 38. A constant current source 39 is also provided in parallel with the constant current source 38. The constant current source 39 is connected to the oscillation frequency lowering circuit 31 similarly to the transistor Q16.
Are selectively connected by a transistor Q15 in the inside.

In the oscillation frequency lowering circuit 31, the transistors Q15 and Q16 are turned on when the potential of the connection point 22, that is, the terminal voltage of the capacitor C3 becomes higher than the reference voltage Vref11 set by the reference voltage source 41, for example, 4V or more. , And the comparator 42 conducts.

For example, the voltage Vs is selected to be 4 V, and the voltage dividing resistors R11, R12, and R13 each have a voltage of 9.
68 kΩ, 2.42 kΩ and 18 kΩ are selected. Therefore, the comparator 34 includes the bypass transistor Q11
Is cut off, the output voltage of the oscillation circuit 32, that is, the terminal voltage of the capacitor C11 is: (R12 + R13) · Vs / (R11 + R12 + R13) = (2.42 + 18) · 4 / (9.68 + 2.42 + 18) = 2 .71V, a high-level output is derived, and the bypass transistor Q11 is turned on.

Thus, once the bypass transistor Q
11 conducts, even if the output voltage drops from the 2.71V, the bypass transistor Q11 can be used until R12 · Vs / (R11 + R12 + R13) = 2.42.4 / (9.68 + 2.42 + 18) = 0.8V. Is conducting,
When the voltage reaches 0.8 V, the bypass transistor Q11
Is shut off and remains shut off until the voltage again reaches 2.71V.

On the other hand, the output from the comparator 35 is opposite to that of the comparator 34, that is, the output voltage rises.
Up to 71 V, a high-level output is derived, so that the transistor Q12 is conducting. When the voltage reaches 2.71 V, a low-level output is derived until the voltage drops to 0.8 V, and the bypass transistor Q12 is cut off. I have.

Here, the current amount of the constant current source 38 is I
0, for example, 5.2 μA, whereas the current amount of the constant current source 39 is I1, for example, 10.4 μA.
A is set. The current amount of the constant current source 36 is 2
I0 = 10.4 μA is selected, and the current amount of the constant current source 37 is selected as 2I1 = 20.8 μA. Furthermore, the capacitance of the capacitor C11 is selected to be 41 pF.

Therefore, transistors Q15, Q16
When the bypass transistor Q12 is turned off while the transistor is conducting, the transistor Q14 is turned off, and the constant current sources 38 and 39 cause the capacitor C11 to output a current amount I0.
The battery is charged at + I1. Therefore, assuming that the terminal voltage, that is, the output voltage of the oscillation circuit 32, is a change time t, t = ΔV · C11 / (I1 + I0) = (2.71-0.8) × 41 × 10 ⁻¹² / ( 10.4 + 5.2) × 10 ⁻⁶ = 5 (μsec), and increases from 0.8 V to 2.71 V in 5 μsec.

On the other hand, the bypass transistor Q1
2 is turned on, the transistor Q14 is turned on, and the capacitor C11 is supplied with the current I
While being charged by 0 + I1, it is discharged by the sum of the currents 2 (I0 + I1) of the constant current sources 36 and 37. Therefore, from the above equation, it is 5 μs from 2.71 V to 0.8 V.
ec.

As described above, the oscillation circuit 32 operates while the transistors Q15 and Q16 are conducting, as shown in FIG.
As shown in (a), a period of 10 μsec, that is, 10
At 0 kHz, a triangular wave in the range of 0.8 V to 2.71 V is oscillated.

On the other hand, transistors Q15, Q1
When the oscillation frequency drops, which is cut off by I.6, I1 = 0 in the above equation, and as shown in FIG.
A triangular wave oscillating at 5 μsec, that is, at 33 kHz is output.

FIG. 4 is a waveform diagram for explaining the operation of the switching power supply circuit 1 configured as described above.
FIG. 4A shows a drain current waveform of the switching element Q1, and FIG. 4B shows a current waveform of the diode D1. In the rated load state shown before time t1, the control circuit 6
Is the switching element Q for the ON period W2 per cycle W1.
1 is conducting.

On the other hand, as shown after time t1, a short circuit occurs and an overcurrent state occurs.
As shown by 2, when the drain current becomes equal to or higher than the overcurrent detection level L1 set by the resistor R1, the overcurrent detection circuit 12 shuts off the circuit breaker 14, and the current from the PWM comparator 13 to the switching element Q1 is changed. Cut off the gate pulse. However, actually, the delay time for preventing malfunction by the blanking circuit 11 and the overcurrent detection circuit 1
Due to a response delay such as 2, the gate pulse is cut off at time t3 which is delayed from the time t2 by the delay time W3. With this operation, the gate pulse O
The N period becomes shorter, and after time t4, the control circuit 6
Is the shortest time determined by the response performance and the like.

On the other hand, as a result of the limitation of the gate pulse width as described above, the electromotive force generated on the secondary side decreases, and the output voltage decreases. As a result, the output voltage error detection circuit 26 reduces the amount of light emitted from the light emitting diode D2, and thus the collector current of the phototransistor Q2 decreases, and the potential at the connection point 30 increases. Connection point 3
When the potential of 0 becomes equal to or higher than the reference voltage Vref2, the comparator 27 sets the transistor Q3 and the Zener diode D3
And charging of the capacitor C3 by the constant current source 21 is started.

In the steady state, as described above, the terminal voltage of the capacitor C3 is maintained at 3.6 V, and the terminal voltage rises by charging the capacitor C3.
In 5, when the reference voltage Vref11 becomes 4 V or more, the oscillation frequency lowering circuit 31 lowers the oscillation frequency of the oscillation circuit 32 from 100 kHz to 33 kHz.

The charging current from the constant current source 21 is set to, for example, 10 μA.
3, the capacitance is selected to be 0.1 μF. Therefore, when the oscillation frequency is reduced from the time t5 and the short-circuit state on the secondary side is not eliminated and the output voltage continues to decrease, the capacitance from the time t5 starts. From the time W4, that is, the time t6 after the lapse of 38 msec, the terminal voltage of the capacitor C3 becomes the reference voltage Vref1, that is, 7.8 V or more, the power supply from the power supply circuit 25 to each circuit is stopped, and the output is cut off. Become.

As described above, in the switching power supply circuit 1 according to the present invention, when the output is short-circuited, first, the ON period of the gate pulse is shortened to set the overcurrent limiting state, and thereafter, when the overcurrent state is not resolved, In performing the overcurrent protection operation by setting the output cutoff state through the output cutoff delay state for preventing a malfunction, in the output cutoff delay state, the primary current and the secondary current are suppressed by the pulse width limitation of the gate pulse. If not, the switching frequency is reduced.

Therefore, in the output cutoff delay state,
After the diode current on the secondary side has sufficiently decreased, the drain current on the primary side starts to flow, so that the drain current does not increase, and the output impedance on the secondary side and the input impedance on the primary side in a short-circuit state are reduced. Therefore, the drain current of the level L2 in which the rising point of the drain current on the primary side coincides with the falling point of the diode current on the secondary side flows. This level L2 is sufficiently smaller than the level L12 of the prior art shown in FIG. 6, so that it is not necessary to excessively increase the current ratings of the switching element Q1, the pulse transformer 5 and the diode D1. Thus, cost reduction can be achieved.

In the above-described embodiment, the oscillation frequency lowering circuit 31 performs an oscillation operation by detecting that the output cutoff delay circuit 17 is activated by the terminal voltage of the capacitor C3, that is, the output voltage detecting circuit 15. Although it is configured, as another embodiment of the present invention, the connection point 3
An output from another means for detecting a decrease in the output voltage, such as directly detecting the feedback voltage of 0, may be used as a trigger input. Further, instead of the blanking circuit 11, as a configuration for delay, R as shown in FIG.
Another delay circuit such as the C filter circuit 75 may be used.

[0049]

As described above, in the switching power supply circuit according to the first aspect of the present invention, when an overcurrent state such as a short circuit occurs, first, the ON period of the switching element is shortened, that is, the duty is reduced. When a decrease in the output voltage is detected, the switching frequency of the switching element is reduced to lower the output voltage.

Therefore, when the secondary side is short-circuited and the current of the switching element increases, the ON period of the switching element is first shortened. Is not avoided, the switching frequency is lowered and the overcurrent suppressing operation is performed. In this way, an overcurrent state can be reliably avoided, and it is not necessary to excessively increase the current rating of the switching element, the transformer, the rectifying element on the secondary side, and the like, and the cost can be reduced.

[0051] Further, when performing the output cutoff delay operation for preventing a malfunction for between short circuit instantaneous lowers the switching frequency of the switching element during the delay operation period.

Therefore, even if an output cutoff delay time for realizing a stable operation is set, an overcurrent state can be reliably prevented even within this delay time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of a switching power supply circuit according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a specific configuration of an oscillation circuit and an oscillation frequency lowering circuit used in the switching power supply circuit shown in FIG.

FIG. 3 is a waveform diagram for explaining an oscillation frequency lowering operation of the oscillation circuit by the oscillation frequency lowering circuit.

FIG. 4 is a waveform chart for explaining an operation of the switching power supply circuit shown in FIG. 1;

FIG. 5 is a block diagram showing an electrical configuration of a typical conventional switching power supply circuit.

FIG. 6 is a waveform chart for explaining the operation of the switching power supply circuit shown in FIG.

FIG. 7 is a block diagram illustrating an electrical configuration of another conventional switching power supply circuit.

FIG. 8 is a waveform chart for explaining the operation of the switching power supply circuit shown in FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Switching power supply circuit 2 Rectifier circuit 5 Pulse transformer 6 Control circuit 11 Blanking circuit 12 Overcurrent detection circuit 13 PWM comparator 14 Circuit breaker 15 Output voltage detection circuit 16 Output cutoff circuit 17 Output cutoff delay circuit 25 Power supply circuit 26 Output voltage error Detection circuit 31 Oscillation frequency lowering circuit 32 Oscillation circuit C1 Smoothing capacitor C2 Smoothing capacitor C3 Capacitor D1 Diode Q1 Switching element R1 Resistance

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 3/28 H02M 3/335

Claims (1)

(57) [Claims] 1. A switching power supply circuit in which a primary current of a transformer is switched by a switching element to obtain a secondary current of a desired voltage, wherein an overcurrent detection means for detecting an overcurrent of the switching element. Output voltage detection means for detecting a decrease in output voltage; and control means for controlling a switching operation of the switching element, wherein when the overcurrent is detected by the overcurrent detection means, the ON period of the switching element is reduced. Control means for reducing the switching frequency of the switching element when the output voltage detection means detects a decrease in the output voltage, and an output voltage which is predetermined in relation to the output voltage detection means.
When the voltage becomes equal to or less than the predetermined voltage, the control means controls the switching operation of the switching element.
An output shut-off means for stopping, and
The switching operation is stopped by a predetermined delay time.
Output cut-off delay means for extending the switching frequency in the delay time.
A switching power supply circuit characterized by being reduced.