JP3056141B2 - Bus bridge circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus bridge circuit, and more particularly to a bus bridge circuit for connecting a plurality of system buses in a multiprocessor system having a shared memory.

[0002]

2. Description of the Related Art The expandability of a multiprocessor system can be enhanced by connecting a plurality of system buses by a bus bridge in order to expand a shared memory type multiprocessor system. For example, JP-A-8
According to Japanese Patent Publication No. -297642, a technique for connecting two system buses by a kind of bus bridge called a directory and further maintaining coherency of a store-in cache is described.

According to this, the store-in cache is I
V (Invalid: invalid), CE (Clean Ex)
plus: coincident and exclusive with main memory, CS (Cl
ean Shared: Matched and shared with main memory), DE
(Dirty Exclusive: inconsistent and exclusive with main memory). This cache updates the main memory at the same time as the shared block read (SBR) sent to the bus at the time of a cache mishit when the other cache returns a block in the DE state as a reply, and transits the cache to the CS state. Let it. This cache protocol is described in Information Processing Vol. 32 No. 1 (19
91) pp. This can be said to be based on the Illinois protocol introduced in 64-73 (hereinafter referred to as Reference 1).

When the main memory to be updated is connected to the other bus when the data transfer between the caches accompanied by the update of the main memory occurs on one bus, the above-mentioned directory is stored in one bus. The received reply is converted into a memory block write request on the other bus and output, but the specific method is not disclosed at all.

As another conventional example, there is a bus bridge that connects a local bus to which a plurality of store-in caches are connected and a global bus to which a main memory is connected. This bus bridge includes a copy of a tag memory of a store-in cache (hereinafter, referred to as a copy tag to distinguish it from a tag of the cache). With this, a local bus and a global bus are snooped and indexed / updated. .

The bus used here starts with bus states 1 to 5 for both the local bus and the global bus. The above-described copy tag simplifies the access circuit of the copy tag by fixing the index / update timing from both the local bus and the global bus to a specific timing of the bus state, and competing for access to the copy tag. Eliminates the waiting time caused by

FIG. 4 is an explanatory diagram showing the timing of sending the index / update address to the copy tag. In the figure, indexes and updates from the local bus and the global bus are folded between bus states 1 to 5. Bus state 3 is a dead cycle for switching read / write.

In this system, the store-in cache connected to the local bus has an I / C / DE / DS
And the copy tag has four states of I / C / DE / D. The states of the store-in cache and the copy tag are maintained as shown in Table 10.

[0009]

[Table 10]

[0010] These cache protocols are based on the Berkeley protocol described in the above-mentioned document 1 in the store-in cache on the local bus (hereinafter referred to as I / C / DE / DS type protocol). On the global bus, it can be said that it is based on the Illinois protocol (hereinafter referred to as I / CE / CS / D type protocol).

[0011]

The conventional bus bridge as described above has the following disadvantages.

The first problem is that the control logic on the store-in cache side is complicated in the I / C / DE / DS type protocol adopted for the store-in cache on the local bus.

That is, in the I / CE / CS / DE type protocol, the store-in cache sends a reply only when the cache holds the data in the D state, and transmits the data in the CE / CS state. In the case of holding, the main memory sends out a reply. Since the D state is exclusive in the cache connected to the same bus, it is easy to determine the store-in cache to which the reply should be sent. Further, since the D state is exclusive, writing back from the plurality of store-in caches to the main storage (B
W: block write).

On the other hand, in the I / C / DE / DS type protocol, the cache sends the reply to the C / C / DE / DS.
An arbitration circuit for determining a reply is indispensable because a plurality of store-in caches connected to the same bus may share the same data. Becomes Further, since the DS state exists, BWs from a plurality of store-in caches may cause a conflict, which is also caused by I / C / D.
This is a factor that complicates the design of the E / DS cache.

The second problem is that it is difficult to use an I / CE / CS / D type protocol as a cache protocol on the local bus when indexing / updating is performed at a fixed timing synchronized with the bus state. It is. The reason is that, as in the directory described in Japanese Patent Application Laid-Open No. 8-297624, data transfer between caches occurring in the local bus must be simultaneously received by the bus bridge and transmitted to the global bus as BW. This is because access is performed at a fixed timing when a request is received from both the local bus and the global bus, so that access by such a reply is further added.

A first object of the present invention is to provide a bus bridge for connecting a local bus to which a plurality of store-in caches are connected and a global bus to which a main memory is connected.
An object of the present invention is to provide a function of supporting an I / CE / CS / D type protocol in which control of a cache memory is easier in addition to an I / C / DE / DS type protocol.

A second object of the present invention is to connect a local bus to which a plurality of store-in caches are connected and a global bus to which a main memory is connected, and to copy a tag of the store-in cache. In a bus bridge incorporating a certain copy tag and indexing / updating the copy tag at a fixed timing upon receiving a request from the local bus and the global bus, the bus bridge simultaneously receives data transfer between caches occurring in the local bus. , And a function of transmitting the BW to the global bus.

[0018]

A bus bridge circuit according to the present invention includes a plurality of store-in caches, a local bus connecting the plurality of store-in caches, and a bus bridge circuit connecting the local bus and a global bus. In an information processing system in which a plurality of central processing units including a plurality of main storage devices are connected to the plurality of main storage devices via the global bus, the bus bridge circuit monitors a data reply sent by the store-in cache, and When it is detected that the main storage device should be updated, the data reply is replaced with a block write command and sent to the global bus.

Further, the bus bridge circuit of the present invention comprises a detecting section for monitoring a data reply sent from the store-in cache to the local bus and detecting a condition for updating the main storage device, and a block write when the condition is detected. A selector for generating and transmitting a command, and transmitting a command from the local bus when the condition is not detected.

Further, a bus bridge circuit of the present invention includes a plurality of store-in caches, a local bus connecting the plurality of store-in caches, and a bus bridge circuit connecting the local bus and the global bus. An information processing system in which a central processing unit is connected to a plurality of main storage devices via the global bus,
A local bus interface unit for transferring information to and from the local bus, a global bus interface unit for transferring information to and from the global bus, a first management table for associating requests and replies corresponding to the local bus, A second management table for associating requests and replies corresponding to the first command buffer for temporarily holding commands to be sent to the local bus, and a second command buffer for temporarily holding commands to be sent to the global bus. A detecting unit that fetches information from the local bus interface unit, detects a condition for updating the main storage device with reference to the first management table, and transmits a command to the global bus according to a signal transmitted by the detecting unit. Select A selector and a command sent by the selector and a command fetched by the global bus interface unit are monitored, and the first command buffer and the second command buffer are operated to correspond to the global bus and the local bus, respectively. And a control unit for transmitting and deleting unnecessary information.

Further, in the bus bridge circuit according to the present invention, the selector includes a command code generation unit that generates a block write command when the detection unit detects a condition for updating the main storage device, A switch unit for selecting any of the block write command and the command from the local bus.

That is, the bus bridge circuit according to the present invention transmits a data reply transmitted by a store-in cache connected to a local bus under its control to a global bus.
(Hereinafter, in order to distinguish the BW due to such an operation from a normal BW, in particular, RBW: Reply w
It is written as "is Block Write". RBW detection circuit for detecting a condition, a request received from the local bus, and a reply to be transmitted as a BW to the global bus, selected by the RBW detection circuit, and a copy tag (CTAG) control unit and a global bus command are selected. A selector for sending to the buffer, an LRTMT (local bus read resource management table) for holding a request address of a request in a reply waiting state on the local bus, and a cancel for sending a cancel signal to the local bus based on a signal from the RBW detection circuit. A generation circuit is provided.

The above-mentioned bus bridge circuit has a RBW
When the detection circuit receives RBW from the local bus, RB
It is possible to cancel a request received in the same bus cycle as W, suppress access to a copy tag (CTAG), and transmit a BW to the global bus by storing an RBW command in a global bus command buffer. I do.

The RBW address is sent to the CTAG controller simultaneously with the storage in the global bus command buffer, and the CTAG is indexed and updated.

Thus, the I / C on the local bus
An E / CS / D type cache protocol can be realized.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory diagram showing a configuration example of an information processing system including a bus bridge circuit according to the present invention. In FIG. 1, a CPU (central processing unit) 1 includes SICs (store-in caches) 101 to 104 and a bus bridge circuit 1.
L bus (local bus) 110 connecting
The bus bridge circuit 120 is connected to MMUs (main storage devices) 3 and 4 by a G bus (global bus) 5. CPU2 is also SIC2 similarly to CPU1.
01 to 204, a bus bridge circuit 220, and an L bus 210, and are connected to the MMUs 3 and 4 via a G bus.

Here, in the CPU 1, the SICs 101 to
104, bus bridge circuit 120, and L bus 110
Are implemented in the same package. Also, CPU2
The same is true for The G bus 5 is mounted on the back board of the housing, and the CPUs 1 and 2 and the MMUs 3 and 4 are connected to the G bus 5 in package units.

The number of SICs connected to the L bus,
The number of CPUs and MMUs connected to the G bus should be determined in consideration of the driving capability of the driver of the LSI and the operating frequency of the bus, and is not particularly limited to the configuration described here.

Although not shown in FIG.
Is connected to one or more processors. In general, processors often include a primary cache, but the configuration of the primary cache, the number of processors connected to the SIC, and the like do not affect the effects of the present invention, and thus are not described in detail.

The above-mentioned L bus and G bus are split transaction buses operating according to the same bus protocol. Further, it is possible to separate the address line and the data line and operate them independently.
After that, only when necessary especially,
Described separately from the data bus. Commands operating on the address bus are described as address bus commands, and commands operating on the data bus are described as data bus commands.

In the case of an operation in which a request and a response form a pair, such as an operation of reading data into a cache, a request and a reply are sometimes described in order to distinguish them.

[0033]

[Table 1]

Table 1 shows the operation timing of the address bus command. The bus states 1 to 5 are timing signals that are constantly counted in synchronization with the clock during the bus operation.

The address bus command is executed in ten stages from the REQ stage to the OWN stage. The execution timing of each stage is completely synchronized with the bus states 1 to 5.

Address bus commands can operate overlapping each other in each bus cycle. For example, in the cancel (CAN) stage of the preceding command, the request (REQ) stage of the immediately following bus cycle is started.

Here, the CAN stage and the OWN stage will be particularly described. First, cancel the address bus command (ACA) sent in the CAN stage.
N) is a signal transmitted when the address bus command being executed cannot be executed for some reason. The data may be transmitted from any node connected to the bus. Since the command is promised to complete the transmission only when the ACAN is not transmitted from any node, the request transmission source (requester) cancels the transmission of the command if the command is ACAN, or Has to be repeated until the data is no longer ACAN.

In the OWN stage, the read request (S
In the case of BR or EBR), OWN (I), OWN (C), OWN
The three types of information (D) are transmitted. The node on the bus monitors the value of OWN, registers SIC and CTAG, and determines a node (replier) that sends a reply. The procedure for determining such a reply on the L bus is hereinafter referred to as reply arbitration.

[0039]

[Table 2]

Table 2 shows the procedure of reply arbitration on the L bus. It should be noted here that the bus bridge has a priority in acquiring the reply right, and that if the output from any node is OWN (I), the bus bridge becomes a reply. .

On the G bus side, the node that sent OWN (D) becomes the replyer. Although details will be described later, this is because a plurality of nodes do not simultaneously transmit OWN (D) on the G bus. Otherwise, the value sent is O
Regardless of WN (C) and OWN (I), the main storage device is always the replier.

[0042]

[Table 3]

Table 3 shows the operation timing of the data bus command. Similarly to the address bus command, all eight stages from the REQ stage to the D3 stage are executed in synchronization with the bus states 1 to 5. Further, as in the case of the address bus command, it is possible to operate overlapping each bus cycle.

It should be noted that the reply sends out the main memory update instruction flag in the RID stage. The main memory update instruction flag is a flag indicating that writing to the main memory is performed simultaneously when the reply is transferred to the requester.

If the main memory update instruction flag is "true" in the reply on the G bus, the MMU receives the reply and writes the reply to the main memory. If the main memory update instruction flag is “true” in the reply on the L bus, the bus bridge receives the reply to perform writing to the main memory, and sends the reply data to the G bus side as a block write BW. Must be sent. In addition, the main memory update instruction flag can be set to “true” at the time of reply in the case of data transfer between SICs in both L bus and G bus, and when the original cache status is DE / DS ( (The cache status will be explained later.)
Limited to

As described above, in the case where the main memory update instruction flag = “true” is given to the reply on the L bus side, the operation of transmitting the block write BW to the G bus side is described as follows.
RBW (Reply with Block Write)
e).

In a bus of the split transaction system as described above, usually, a node called a read resource management table (RRMT) is provided at each node on the bus in order to associate a request with a reply. Read request (SBR and EBR)
Is sent to the bus, the request is given a unique ID number and registered in the RRMT. Since the reply sending source (replier) attaches the ID of the corresponding request when sending the reply and returns the reply to the request sending source (requester) (RID stage in Table 3), the requester is sent out on the data bus. It is possible to determine which request the reply corresponds to.

Another function of the RRMT is to hold the request address together with the ID of the request at the time of sending the request, and to allow another node to access the same address from the memory until the reply is returned. Used to deter. As a result, the order of guaranteeing the memory update for blocks at the same address is solved.

Table 4 shows a list of information stored in the RRMT. These are only the minimum necessary to realize the function of the RRMT, and more information may be added in an actual implementation.

[0050]

[Table 4]

[0051]

[Table 5] Table 5 shows commands defined as bus commands.
Here, the shared read SBR and the exclusive read EBR are address bus commands, and the reply RPY is a data bus command. The block write BW is transmitted using the address bus and the data bus simultaneously.

FIG. 2 is a block diagram showing the configuration of the bus bridge circuit 120 of the present invention. In the figure, a bus bridge circuit 120 is connected to the L bus 110 and the G bus 5.

The L bus interface unit 11 is provided for the L bus 1
10 is an interface between the bus bridge 120 and the inside. All inputs and outputs to the L bus 110 are performed via the L bus interface unit 11.

Similarly, the G bus interface unit 21
This is an interface between the bus 5 and the inside of the bus bridge 120, and all inputs and outputs to the G bus 5 are performed via the G bus interface unit 21.

LRRMT12 and GRRMT24 are
Read resource management table (RRMT) described above
It is. The bus bridge 120 includes the L bus 110 and the G bus 5
Are provided with independent RRMTs corresponding to each of.

The G bus command buffer 22 stores the G bus 5
The command to be sent to is stored. Similarly, the L bus command buffer 15 stores a command to be sent to the L bus 110. Also, as described above, the bus separates the address bus and the data bus, and each has a structure that can operate independently. Therefore, these command buffers are also a buffer for the address bus command and a buffer for the data bus command. However, since the buffer structure does not affect the effect of the present invention, it is collectively shown as one command buffer in the drawing.

The cancel generating circuits 14 and 23 generate the cancel signals (ACAN, DCAN) of the command received from the L bus 110 and the G bus 5, respectively, and send them to the L bus interface unit 11 and the G bus interface unit 21. .

The RBW detection circuit 13 detects a condition for transmitting the data reply (RPY) command transmitted on the L bus 110 to the G bus 5 as BW.

The selector 16 operates under the control of the RBW detection circuit 13. That is, the address bus command received from the L bus interface unit 11 and the LRRMT1
2 is selected and sent to the G bus command buffer 22.

The CTAG control unit 30 includes a copy (CTAG: Copy Tag) of a tag of a store-in cache (SIC) connected under the L bus 110 and a control circuit therefor. Indexing / updating of CTAG is performed by address bus commands of L bus and G bus. This indexing / updating is performed at a fixed timing after receiving the command, as shown in FIG.

Table 6 shows the status of the CTAG. CT
The AG is managed in four states of I / CE / CS / D. At this time, the cache status of the SIC can take any one of the four states of I / C / DE / DS as shown in Table 7. However, as will be described later, it is also possible to operate with the cache status limited to only three states of I / C / DE / (see Table 8). In any case, at this time C
The status of the TAG and the cache status of the SIC must be managed so as to be a combination as shown in Table 9 (indicated by a triangle in Table 9).

[0062]

[Table 6]

[0063]

[Table 7]

[0064]

[Table 8]

[0065]

[Table 9] Next, the operation of the bus bridge circuit will be described.

(1) Data reply to the L bus (RBW)
Is sent out, a data reply (RPY) is sent out on the L bus, the requester and the replyer are both SICs on the same L bus, and the main memory update instruction flag =
When the RBW detection circuit 13 detects the condition to which “true” is given, an instruction to start the RBW operation is given to the cancel generation circuit 14 and the selector 16.

The cancel generation circuit 14 detects that an address bus command has been sent to the L bus in the same bus cycle as the data reply (RBW), and detects ACA.
N. If no address bus command has been sent, there is no need to send ACAN.

The selector 16 selects a signal from the LRRMT 12 according to an instruction from the RBW detection circuit 13 and sends the signal to the G bus command buffer 22 and the CTAG control unit 30.

FIG. 3 is an explanatory diagram showing details of the RBW detection circuit 13 and the selector 16 described above. In the figure,
The selector includes a BW command code generation circuit 51 and switches 52 to 54, and the RBW detection circuit 13 includes AND circuits 61 to 62.

The signal input from LRRMT 12 is V
/ AD / S. V is a flag (Valid) indicating that the signal is valid, AD is a request address, and S is a flag (Self source flat) indicating that the request transmission source is itself.
g).

The signal input from the L bus interface section 11 is composed of the elements V, CD, AD, DT, RM. V, CD, and AD are a flag (Valid) indicating that the address bus command received from the L bus is valid, a command code, and a request address. DT is data of a data bus command received from the L bus, and R is a flag (Reply) indicating that a valid data bus command (RPY) has been received from the L bus.
flag) and M are input with the value of the main memory update instruction flag in the RID stage of the data bus command.

The signal sent from the selector 16 is V ·
It consists of CD, AD and DT elements. These are each a valid flag (Valid), like the input signal.
Command code, request address, and data.
The interface between the cancel generation circuit 14 and the RBW detection circuit 13 includes an ACAN instruction signal and an RBW reception suppression instruction signal.

The RBW detection circuit 13 is composed of two AND circuits, and first detects an RBW condition by the first AND circuit 61. That is, a valid data reply is transmitted on the L bus (R), which is not a reply to the request transmitted from itself (NOTS), and the main memory update instruction flag (M) is set to “true” at the RID stage. Is detected. The second AND circuit 62 prevents the cancel circuit 14 from starting the RBW operation.

The reason why the RBW operation cannot be started is that there is no empty entry for receiving new data in the G bus command buffer 22, which is notified by a control signal from the G bus command buffer 22 to the cancel generation circuit 14. You. In this case, the address bus command A
No CAN is performed.

When the RBW operation is started by the above logic, an ACAN instruction signal is sent to the cancel generation circuit 14.
A command select signal is sent to the selector 16. This select signal is distributed to the switches 52 to 54, and in the RBW operation, (V) from the LRRMT, the command code generated by the BW command code generation circuit 51 (generates the same code as BW), LRR
Select (AD) from MT.

Referring again to FIG. 2, the signal output from selector 16 is distributed to CTAG control unit 30 and G bus command buffer 22. Whether or not a command needs to be sent to the G bus is determined by the CTAG control unit 30 based on these signals, and the result is passed as a storage instruction signal to the G bus command buffer 22.

The RBW (BW) stored in the G bus command buffer 22 is finally sent to the G bus interface unit 2
1 to the G bus 5.

The LRRMT 12 deletes the information of the entry corresponding to the ID number when the reply is sent out on the L bus.

As described above, at the time of RBW reception, the address bus command received in the same bus cycle is
Then, the received reply is replaced with BW and stored in the G bus command buffer. The reason why the address bus command must be ACAN in this way is that, as shown in FIG. 4, index / update of CTAG is performed at fixed timing when address bus commands of L bus and G bus are received. This is because there is no room to newly add the index / update timing of the CTAG by the RBW command.

As has been clarified in the description so far,
On the L bus, by setting the main memory update instruction flag (M) to "true" in the RID stage at the time of sending out a reply, a cache protocol consisting of three states of I / C / DE as shown in Table 8 can be used. It is possible to realize.
If the main memory update instruction flag (M) is always set to “false” when sending a reply, the SIC operates according to the cache protocol having the original four states of I / C / DE / DS as shown in Table 7. Needless to say.

That is, the cache protocol on the L bus depends on how the reply (SIC) handles the main memory update instruction flag, and special hardware such as a mode setting flag is provided in the bus bridge circuit. No need.

Needless to say, an implementation not using the main memory update instruction flag is also possible. In this case, a mode setting flag is provided for each node (SIC and bus bridge) connected to the L bus, and instead of the main memory update flag, The protocol can be switched by referring to this mode setting flag.

(2) When L-Bus Data Reply (Except RBW) is Sent When the RBW operation does not need to be started by the reply sent to the L-bus 110, the bus bridge circuit 120 performs one of the following operations. Do.

When the reply is a reply to the request sent by itself, the reply data is sent from the L bus interface unit 11 to the G via the selector 16.
It is stored in the bus command buffer 22. At this time, the storage instruction signal to the G bus command buffer 22 is LRRM.
This is the flag (S) passed from T12.

Alternatively, if the reply is not to itself, the bus bridge circuit does nothing to that reply.

The LRRMT 12 erases the information of the entry corresponding to the ID number when the reply is sent out on the L bus.

(3) An address bus command (S
When BR / EBR / INV is sent The received command is passed from the L bus interface unit 11 to the CTAG control unit 30 via the selector 16 (only when RBW is not received in the same cycle). CT
If it is determined that the command is to be transmitted to the G bus as a result of indexing and updating the AG, the command is stored in the G bus command buffer 22 and transmitted to the G bus via the G bus interface unit 21.

Also, if the received address bus command is S
Only for BR or EBR, LRRMT1
Registration to 2 is performed.

(4) When the L Bus BW is Sent BW is a command executed by simultaneously performing both the address bus and the data bus. At this time, RBW cannot be executed in the same bus cycle.
There is no instruction from the BW detection circuit 13 to the cancel generation circuit 14 and the selector 16.

Therefore, the BW received by the L bus interface unit 11 is passed to the G bus command buffer 22 via the selector 16. The CTAG control unit 30 indexes and updates the CTAG according to the address of the BW, and issues an instruction to store the received BW to the G bus command buffer 22.

The BW stored in the G bus command buffer 22 is sent to the G bus via the G bus interface unit 21.

(5) A data bus command (RP
When Y) is sent When the reply is a reply to the request sent by itself, the reply data is stored from the G bus interface unit 21 into the L bus command buffer 15. At this time, the storage instruction signal to the L bus command buffer 15 is GRRMT 24 (the stored information is LRRMT1).
2 is the same as the flag (S).

Alternatively, if the reply is not to itself, the bus bridge does nothing to that reply.

The GRRMT 24 erases the information of the entry corresponding to the ID number when the reply is transmitted on the G bus.

(6) An address bus command (S
(BR / EBR / INV) is transmitted.
It passes to the TAG control unit 30. If it is determined that a command is to be transmitted to the L bus as a result of indexing and updating the CTAG, L
The command is stored in the bus command buffer 15 and transmitted to the L bus via the L bus interface unit 11.

When the received address bus command is S
GRRMT2 at reception only for BR or EBR
4 is registered.

(7) When BW is sent out to G bus The BW sent out to the G bus is received by the main storage unit MMU and updates the main storage. The bus bridge circuit transfers the BW received from the G bus to the CTA control unit 30 via the G bus interface unit 21 and performs only index / update of the CTAG. BW is not stored in the L bus command buffer 15.

[0098]

As described above, the first effect of the present invention is that when sending a data reply on the L bus, the
C can selectively use a cache protocol having three states of I / C / DE and a cache protocol having four states of I / C / DE / DS by changing the handling of the main memory update instruction flag. It is.

The second effect of the present invention is that an I / C / DE type cache protocol can be used in addition to an I / C / DE / DS type protocol requiring a complicated logic circuit by the SIC. By doing so, if there is a logic defect in the SIC, this can be avoided and the initial setting quality of the system can be improved.

A third effect of the present invention is that the bus bridge ACANs the address bus command of the same bus cycle when receiving the RBW, selects the RBW instead of the address bus command by the selector, and selects the CTAG.
When the address bus command is received from both the L bus and the G bus,
In a system for indexing / updating a TAG memory, RB
W operation is to be enabled.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration example of a system including a bus bridge circuit of the present invention.

FIG. 2 is a block diagram showing one embodiment of the present invention.

FIG. 3 is an explanatory diagram showing details of a selector and an RBW detection circuit.

FIG. 4 is an explanatory diagram showing a conventional copy tag index / update timing.

[Explanation of symbols]

 1, 2 CPU 3, 4 MMU 5 G bus 11 L bus interface unit 12 LRRM 13 RBW detection circuit 14, 23 cancellation generation circuit 15 L bus command buffer 16 selector 21 G bus interface unit 22 G bus command buffer 24 GRRMT 30 CTAG control Unit 51 BW command code generation circuit 52 to 54 switch 61 to 62 AND circuit 101 to 104 SIC 110 L bus 120 bus bridge circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁷ , DB name) G06F 15/16 645 G06F 13/16 510 G06F 13/36 320 G06F 15/177 682 INSPEC (DIALOG) JICST file ( JOIS) WPI (DIALOG)

Claims (4)

(57) [Claims] A plurality of store-in caches; a local bus connecting the plurality of store-in caches;
In an information processing system in which a plurality of central processing units including a bus bridge circuit for connecting the local bus and the global bus are connected to a plurality of main storage devices via the global bus, the bus bridge circuit includes the store-in circuit. A bus bridge for monitoring a data reply transmitted by a cache and, when detecting that the main memory is to be updated by the data reply, replacing the data reply with a block write command and transmitting the data reply to the global bus; circuit. 2. The bus bridge circuit according to claim 1, wherein the bus bridge circuit monitors a data reply sent from the store-in cache to the local bus, and detects a condition for updating the main storage device. A bus bridge circuit comprising: a selector that generates and sends a block write command when the condition is detected, and sends a command from the local bus when the condition is not detected. 3. A plurality of store-in caches, a local bus connecting the plurality of store-in caches,
A plurality of central processing units including a bus bridge circuit connecting the local bus and the global bus transfer information to and from the local bus in an information processing system connected to a plurality of main storage devices via the global bus. A local bus interface unit, a global bus interface unit that transfers information to and from the global bus, a first management table that associates requests and replies corresponding to the local bus, and associates requests and replies that correspond to the global bus A second management table, a first command buffer for temporarily holding commands to be sent to the local bus, a second command buffer for temporarily holding commands to be sent to the global bus, and information from the local bus interface unit. A detector for detecting a condition for updating the main memory by referring to the first management table captures, a selector for selecting a command to be sent to the global bus in accordance with a signal the detection unit is sent,
The command sent by the selector and the command fetched by the global bus interface unit are monitored, and the first command buffer and the second command buffer are operated to send the corresponding command to the global bus and the local bus, respectively. A bus bridge circuit comprising: a control unit that deletes unnecessary information. 4. The bus bridge circuit according to claim 2, wherein the selector comprises: a command code generator for generating a block write command when the detector detects a condition for updating the main storage device; A switch unit for selecting one of the block write command and the command from the local bus in accordance with an instruction from the detection unit.