JP3055992B2 - Data transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission system in which a plurality of terminals communicate by transmitting and receiving information packets via a common line (bus). The present invention relates to a data transmission system using a method.

[0002]

2. Description of the Related Art As described in Japanese Patent Application Laid-Open No. 61-274028, when a plurality of terminals perform information packet communication via a bus, each device is connected to an interface device for connecting the terminals to the bus. Then, an inquiry signal for inquiring a communication request of the terminal is transmitted from the central control device, a response signal is transmitted when there is a packet to be communicated, and a self-packet is transmitted when the bus is free.

[0003]

In the above-mentioned prior art, the inquiry procedure transmitted by the central control unit must be changed according to the type of terminal, so that the inquiry procedure is complicated. That is, since the inquiry signal from the central control device is transmitted for the number of terminals, if the terminal moves and there is no terminal connected to the interface device, the inquiry from the central control device must be deleted. In addition, since the above inquiry to each interface device is performed equally, when information packet communication is concentrated on the host terminal or the like, the number of inquiries from the centralized control device is increased as a whole, and the bus corresponding to this is increased. It was necessary to measure preferential use. An object of the present invention is to provide a data transmission method capable of stabilizing the number of inquiries from a centralized control device regardless of the type and number of terminals connected to a bus, thereby enabling a bus to be used with high efficiency. Is to do.

[0004]

In order to solve the above-mentioned problems, a selection circuit for selecting communication requests from a plurality of terminals belonging to each interface device and a response circuit for transmitting the response signal are provided in each interface device. In response to the inquiry signal, the selection circuit selects each terminal in the interface device having a packet to be communicated, and sends a packet to the bus following the response signal to the common bus. Further, a buffer for storing packets from the terminal is provided in each of the interface devices, and each of the interface devices receives the inquiry signal and transmits a predetermined number of packets in the buffer to the bus. Further, a counter circuit for counting the number of packets stored in the buffer is provided in each of the interface devices, and each of the interface devices receives the inquiry signal and counts a predetermined number of packets corresponding to the count value of the counter circuit. Try to send to the bus.

[0005]

Each of the above interface devices manages a plurality of grouped terminals. For this reason, the response circuit in the interface device monitors the transmission status of the packet of the other terminal, and when detecting the status in which the packet of the other terminal is lost, responds to the inquiry signal from the central control device to perform the selection. The terminal that has the transmission packet is selected from the grouped terminals managed by the interface device by controlling the circuit, and the response signal is transmitted. The buffer stores communication packets of the terminal group, and transmits a predetermined number of packets selected by the selection circuit to the common bus via the bus interface following the response signal. Also,
The counter circuit transmits a predetermined number of packets corresponding to the count value to the bus in response to the inquiry signal.

[0006]

FIG. 1 is a block diagram of a data transmission system according to an embodiment of the present invention. A plurality of terminals 101-11 to 101-1i and the like are connected to the interface device 103-1 via transmission lines 102-11 to 102-1i, respectively. Similarly, a plurality of terminals 101-N1 to 101-Ni are connected to the interface device 103-N, respectively.
2-N1 through 102-Ni are connected. The interface devices communicate with each other via a common bus 105. The terminal groups connected to each interface device are 101-11 to 10-10, respectively.
1-1i, and 101-N1 to 101-Ni.

Each interface device is a central control device 10
4 (polling operation) from the common bus 10
5 usage rights. The polling line for the inquiry is an address 10 specifying the interface device.
6; a line for transmitting an address enable signal 107 indicating that the address 106 is valid; a transmission line for a response signal 108 in response to a communication request inquiry; A line for sending a transmission permission signal 109 for permitting use of the common bus to the interface device that is transmitting the response signal when there is a response signal in a state where the packet is lost, and a packet is being transmitted from the interface device to the common bus 105. And a line for transmitting a bus busy display signal 110 indicating that

The central control unit 104 includes a timing generation unit 301 for inquiry, an address counter unit 302 for transmitting an address line, and polling lines 106 to 1.
10 is configured by a polling logic unit 303 and the like for controlling the control unit 10. In each interface device, a terminal interface and a bus interface corresponding to each terminal are provided. Hereinafter, as an example, the common bus 105
The operation of the terminal 101-11 relating to the packet transmission to the terminal 101 will be described.

The packets from the terminal 101-11 are stored in the transmission buffer / bus transmission control 202-11 via the terminal interface unit 201-11, and when a transmission right to the common bus is given, a predetermined number of packets are transmitted. The data is read from the buffer and transmitted to the common bus 105 via the bus interface unit 203-11. Note that the terminal interface unit 201-11 controls bidirectional transmission with the terminal.
The selection circuit 204-1 selects one of the communication request signals of the same terminal group according to the selection signal.

In response to a communication request inquiry from the central control unit 104, the bus transmission control unit in the above-mentioned 202-11 selects the communication request signal 206-11 and responds to the response circuit 205.
-1. When the selection circuit 204-1 receives the transmission permission signal 109 from the central control device 104, the selection circuit 204-1 transmits the bus transmission permission signal 207-11 to the bus transmission right control unit 20.
2-11. Packets on the common bus 105 are received by the reception buffers / bus reception controllers 208-11 to 208- via the bus interfaces 203-11 to 203-1i.
1i, the reception buffer / bus reception control unit writes a packet whose destination address matches the local address in the reception buffer, and transmits this to the corresponding terminal via the terminal interface unit. Interface device 103-N
The same applies to.

FIG. 2 is a circuit diagram of the selection circuit 204-1, the response circuit 205-1, the bus interface unit 203-1 and the like. The selection circuit 204-1 is often configured by a cyclic control method using a ring counter, a polling method using a master counter, an arbitration method, and the like, but FIG. 2 employs a cyclic control method using a ring counter. The same applies to the interface device 103-N. In FIG. 2, although i indicating the correspondence with the terminal in each number given in FIG. 1 is omitted,
Reference numerals 105 to 109, 202 to 207, and the like correspond to the numbers in FIG.

In the selection circuit 204-1, 402-1
To 402-i are ring counters that output cyclic selection signals 403-1 to 403-i for selecting communication request signals of terminal groups. One of the ring counters is sequentially set by a signal from the reset line 401, and the others are reset. AND gates 404-1 to 4-4
04-i and the OR gate 405
3-1 to 403-i, the communication request signal 206-1 to 206-2
Select 06-i. Also, AND gates 410-1 to 410-1
410-i transmits the bus transmission permission signals 207-1 to 207-i to each bus transmission control unit in correspondence with the communication request signal and the transmission permission signal 109.

The response circuit 205 sets the response signal RS flip-flop 406 according to the communication request signal selected by the selection circuit, and circulates the cyclic selection signal of the ring counters 403-1 to 403-i via the NOT gate 411. To stop. The comparator 408 compares the inquiry from the central control unit with the address 106 and the address enable signal 107 and the own polling address 407 possessed by each interface unit. When the RS flip-flop 406 is set, the response signal 108 is transmitted to the central control device.

The AND gate 414 detects the coincidence between the output of the comparator 8 and the transmission permission signal 109, and resets the response signal RS flip-flop 406. In response to this, the transmission of the response signal is stopped, and the ring counters 403-1 to 403-1
The tour of 403-i is restarted. RS flip-flops 412-1 to 412 in the bus interface unit 203
i is set by the bus transmission permission signals 207-1 to 207-i, and transmits the bus busy indication signal 110. 2
02 is a transmission end signal 413-1 to 4-4.
13-i to transmit the RS flip-flops 412-1 to 412-1.
412-i is reset, and the bus busy display signal 110 is stopped.

FIG. 3 is a block diagram of the transmission buffer / bus transmission control unit. The method of the buffer 417 determining the number of internal packets and transmitting the packets continuously includes a method based on the number of packets in the buffer, a method based on the capacity of the packets stored in the buffer, and the like. Here, the former will be described. In FIG. 3, i indicating the correspondence with the terminal in each number given in FIG.
6, 207, 413, etc. correspond to the numbers in FIG.
Terminal reception packet data 41 from the terminal interface unit
5 and its packet valid bit 416 are input to the transmission buffer / bus transmission control unit. Packet valid bit 416
Is "1", the packet data 415 is written to the buffer 417 by the write address value of the write address counter 418.

When the packet ends, the packet valid bit 416 changes from "1" to "0". In response to this, the counter circuit 422 counts up and the number of packets in the buffer is updated. The read address counter 421 sends the read address value to the buffer 417 in response to the bus transmission permission signal 207 from the selection circuit 204, and the buffer 417 transmits the bus transmission packet data 419 and the packet valid bit 420 to the bus 105 in response to this. .

If the packet valid bit 420 is "1", the packet data is valid, and this changes from "1" to "0".
The counter circuit 422 counts down and updates the number of packets in the buffer and sends the transmission request signal 206 to the selection circuit 204. At this time, if the value of the counter circuit 422 is “1”, the buffer 417 continuously reads the packet and transmits the packet to the bus. When the packet ends, the above “1” becomes “0”, so that the counter circuit 422 outputs the transmission end signal 4
13 is output. FIG. 4 is a diagram showing the data structure in the buffer 417. A packet valid bit is added to the packet data in the buffer 417, and packet data having consecutive packet valid bits of "1" is treated as one packet.

[0018]

According to the present invention, since a plurality of terminals are grouped and connected to one interface device for each group, the interface device can absorb the influence of the change in the number of terminals due to the movement of the terminals. Accordingly, an inquiry from the centralized control device to the interface device can be made irrespective of a change in the number of terminals. As a result, it is possible to reduce the number of times of the above inquiry, increase the probability of responding to one inquiry at the same time, and reduce the number of empty polls for inquiring of interface devices having no communication packet, thereby increasing the effective use efficiency of the common bus. Can be.

When information packet communication from a host terminal or the like is concentrated, packets can be stored in a buffer and the priority transmission can be performed by continuously transmitting the packets to a bus. It is not necessary to increase the number of queries from. Further, since the number of various information packets of the terminals connected to the interface device can be dynamically adjusted for each terminal and continuously transmitted to the common bus, the use efficiency of the common bus can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data transmission system according to the present invention.

FIG. 2 is a circuit diagram of a selection circuit, a response circuit, and a bus interface unit used in the data transmission system of the present invention.

FIG. 3 is a circuit diagram of a transmission buffer / bus transmission control unit used in the data transmission system of the present invention.

FIG. 4 is a configuration diagram of data in a buffer according to the present invention.

[Explanation of symbols]

101-11-101-Ni Each terminal 102-11-102-Ni Each transmission line 103-1-103-N Each interface device 104 Centralized control device 105 Common bus 106 Address 107 Address enable signal 108 Response signal 109 Transmission permission signal 110 Bus transmission display signal 201-11 to 201-Ni Each terminal interface 202-11 to 202-Ni Each transmission buffer / bus transmission control unit 203-11 to 203-Ni Each bus interface unit 204-1 to 204-N Each selection Circuits 205-1 to 205-N Response circuits 206-11 to 206-Ni Communication request signals 207-11 to 207-Ni Bus transmission permission signals 208-11 to 208-Ni Reception buffer / bus reception control unit 301 Timing generator 302 Address counter 3 03 Polling logic unit 401 Reset line 402-1 to 402-i Each ring counter 403-1 to 403-i Each cyclic selection signal 404-1 to 404-i, 410-1 to 410-i, 4
14 AND gate 405 OR gate 406, 412 RS flip-flop 407 Own polling address 408 Comparator 409 Tristate gate 411 NOT gate 413 Transmission end signal 415 Terminal received packet data 416 Packet valid bit 417 Buffer 418 Write address counter 419 Bus transmission Packet data 420 Packet valid bit 421 Read address counter 422 Counter circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Setsuo Shimoe 180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Communication Systems Co., Ltd. In the Totsuka Plant of Hitachi, Ltd. (72) Inventor Michio Iizuka 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo Inside the Hitachi Microcomputer System (56) References JP-A-61-30145 (JP, A) JP-A-5-102975 (JP, A) JP-A-1-276940 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 12/28

Claims (3)

(57) [Claims] 1. A central control unit sends a communication request inquiry signal to a terminal, and in accordance with the response signal, the terminals permitted to communicate are connected to a common bus via an interface device to perform communication between the terminals. In the data transmission system, a selection circuit for selecting communication requests from a plurality of terminals belonging to each of the interface devices and a response circuit for transmitting the response signal are provided, and each of the interface devices responds to the inquiry signal. A data transmission system which selects each terminal in the interface device having a packet to be communicated by the selection circuit, and sends a packet to the bus following the response signal to the common bus. 2. The apparatus according to claim 1, wherein a buffer for storing packets from the terminal is provided in each of the interface devices, and each of the interface devices receives the inquiry signal and stores a predetermined number of packets in the buffer. A data transmission system characterized by transmitting data to a bus. 3. The device according to claim 2, further comprising a counter circuit for counting the number of packets stored in said buffer in each of said interface devices, wherein each of said interface devices receives said inquiry signal and counts the count value of said counter circuit. A data transmission system wherein a predetermined number of corresponding packets are transmitted to the bus.