JP3050704B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of operating at high speed by reducing the load on a sense amplifier.

[0002]

2. Description of the Related Art Conventionally, a static random access memory (hereinafter referred to as "SRAM") and a dynamic random access memory (hereinafter referred to as "DRAM").
Such semiconductor memory devices include a redundant circuit in order to improve the production yield. When a defect exists in the manufactured semiconductor memory device, the semiconductor memory device is relieved by the function of the redundant circuit. That is, in a conventional semiconductor memory, a row or column including a defective memory cell is functionally replaced with a predetermined spare row or column.

On the other hand, the applicant of the present application has proposed a redundant circuit in a semiconductor memory using a redundant memory cell array instead of a repair method in units of rows or columns using spare rows or spare columns (1991). Filed on December 12; Japanese Patent Application No. 3-28867). In the following description, an SRAM including a redundant circuit using a redundant memory cell array will be described.

FIG. 4 is a block diagram of an SRAM showing the background of the present invention. Referring to FIG.
Includes a total of 64 blocks each including a memory cell array, and one redundant block RB including a redundant memory cell array 1. To simplify the explanation, FIG.
Four blocks BL1 to BL4 are shown.

[0005] One of the 64 blocks, for example, block BL3, has a memory cell array divided into eight areas, a row decoder, a column decoder, and a sense amplifier including eight sense amplifiers (not shown). And a write driver circuit (WD). In each block, the basic circuit configuration of the memory cell array and peripheral access circuits is the same as that of a general SRAM, but no spare memory cell column or row is provided in each block.

The redundant block RB includes a redundant memory cell array 1 having a total of 16 redundant memory cell columns, a row decoder (RD) 2, and a switching circuit 13 for selectively accessing the redundant memory cell columns. Including. Row decoder 2 selectively activates a word line (not shown) in the redundant memory cell array in response to a row address signal RA applied via address bus 11. Switching circuit 13 responds to an activated one of signals CO1 to CO16 provided from address program circuit 3 to switch a corresponding one of the redundant memory cell columns to a sense amplifier circuit and / or a write driver. Connect to circuit.

By performing a test before shipment, it is checked whether or not a defect exists somewhere in the total of 64 memory cell arrays. When a defect exists in one column of a certain memory cell array, an address indicating the position of the defective memory cell column (hereinafter, referred to as “defect address”) is programmed in the address program circuit 3. The address program circuit 3 can program a total of 16 defective addresses.

When a request for access to a defective memory cell column is issued from outside, address program circuit 3 detects a match between a programmed address and a column address given from the outside, and outputs a match detection signal (signals CO1 to CO1). C
O16) and the group selection signal GS1,
GS2 is supplied to the I / O program circuit 4.

I / O program circuit 4 provides switching control signals S11 to S14 and S21 to S24 to selector circuits 5a and 5b in response to a match detection signal and group selection signals GS1 and GS2 supplied from address program circuit 3. Give each. Each of the selector circuits 5a and 5b includes four transmission gates (not shown), which are selectively turned on in response to the switching control signals S11 to S14 or S21 to S24, thereby causing a fault. Access to the redundant memory cell column is performed instead of access to the memory cell column.

Test mode control circuit 8 detects the application of a high voltage HV (for example, about 7 volts when the power supply voltage is 5 volts) applied from the outside and is called "super VCC", and outputs test mode signal TM. . Selector circuits 5a and 5b apply data read from the memory cell array to output buffer 10 when test mode signal TM is not applied. Output buffer 10 outputs the applied data as output data Do.

On the other hand, when test mode signal TM is applied, selector circuits 5a and 5b apply data read from the memory cell array to comparison circuit 6. In response to test mode signal TM, comparison circuit 6 detects whether or not the two data provided from selector circuits 5a and 5b match. The signal indicating the detection result is output to the outside via the output buffer 10. When the comparison circuit 6 outputs the coincidence detection signal, it can be understood that no defect exists in the memory cell column storing the two read data. When the comparison circuit 6 outputs a signal indicating a mismatch, it is understood that a defect exists in the memory cell column storing the two read data.

An input buffer 9 receives input data Di to be written from the outside, and supplies the input data Di to a write driver circuit (WD). Therefore, input data Di is written to a memory cell specified by a row decoder and a column decoder.

FIG. 5 is a circuit diagram of one memory cell array shown in FIG. Referring to FIG. 5, for simplicity of display, only four memory cells 24a to 24d in the memory cell array are shown. Memory cells 24a and 2
4c is connected between bit lines 20a and 20b.
Memory cells 24b and 24d are connected to bit lines 21a and 2d.
1b.

The bit line load circuit 17a has one bit line 20a, 20b, 2 corresponding to the power supply potential Vcc.
NMOS transistors 25a, 25b, 26a and 26b connected between the transistors 1a and 21b. On the other hand, the multiplexer 8a includes a read data line pair RD1 ',
/ RD1 'and bit lines 20a, 20b, 21a and 2
1b, the NMOS transistor 27a,
27b, 28a and 28b.

The row decoder is connected to one of word lines WL0 and WL1 connected to a memory cell to be accessed.
Activate the book selectively. Memory cells 24a and 24b connected to word line WL0 constitute one memory cell row. When word line WL0 is activated, a memory cell row including memory cells 24a and 24b is accessed. On the other hand, column decoder 6 has column selection signals Y0 and Y for selecting a memory cell column to be accessed.
Activate one of the two. For example, when column select signal Y0 is activated, transistors 27a and 27b are turned on, so that a memory cell column including memory cells 24a and 24c is accessed.

FIG. 6 is a circuit diagram showing an example of the memory cell shown in FIG. Referring to FIG. 6, this memory cell M
C1 (for example, 24a in FIG. 5) includes NMOS transistors 41a and 41b and a resistor 43 as a high resistance load.
a and 43b, and NMOS transistors 42a and 42b as access gates.

FIG. 7 is a circuit diagram showing another example of the memory cell shown in FIG. Referring to FIG. 7, memory cell MC2 includes NMOS transistors 41a and 41b
And PMOS transistors 44a and 44b serving as loads, and NMOS transistors 42a and 42b as access gates.

FIG. 8 is a timing chart for describing a read operation of memory cell 24a shown in FIG.
Referring to FIG. 8, the abscissa indicates the passage of time, and the ordinate indicates the potential (volt). Line ADi indicates changes in input signals of the row address buffer and the column address buffer.
Line ADo indicates a change in the output signal of a row and column address buffer (not shown). Line WL0 indicates a change in word line WL0 connected to memory cell 24a.
Line RD indicates a change in read data line pair RD1 ', / RD1'. Line SAo indicates a change in the output voltage of the sense amplifier. The line Do indicates a change in the output signal of the output buffer 10.

At time t0, input address signal AD
i is changed. Therefore, the output signal ADo of the address buffer changes at time t1. At time t2, the potential of word line WL0 changes, so that the data signal stored in memory cell 24a is applied to bit line pair 2
0a and 20b. In addition to this, since the column selection signal Y0 output from the column decoder goes high,
Transistors 27a and 27b are turned on. Therefore, at time t3, the potentials of read data line pair RD1 'and / RD1' change.

At time t4, the sense amplifier is activated, so that the data signal is amplified by the sense amplifier. Therefore, at time t5, output signal Do of output buffer 10 is changed according to the data read from memory cell 24a.

FIG. 9 is a block diagram showing connections between sense amplifiers 90 to 94 shown in FIG. 4 and data transmission lines. Referring to FIG. 9, each of sense amplifiers 91 to 9
4 receives and amplifies the data signal read from the memory cell array in the corresponding block BL1 to BL4. The data signal amplified by sense amplifiers 91 and 92 is applied to read data line RD1 '. The data signal amplified by sense amplifiers 93 and 94 is applied to read data line RD2 '. The sense amplifier 90 is connected to the redundant memory cell array 1 of the redundant block RB.
Amplify the data signal read out from. Sense amplifier 9
The data signal amplified by 0 is applied to redundant read data line RRD '.

The selector circuit 5a shown in FIG. 4 includes the switching circuits 51 and 52 shown in FIG. The selector circuit 5b shown in FIG. 4 includes the switching circuits 53 and 54 shown in FIG. Each of the switching circuits 51 to 54 includes two transmission gates TG. The comparison circuit 6 compares data read from two blocks in a test operation. After the same data is written to the memory cell arrays in the test operation, data is read from the two memory cell arrays, and the read data is compared by comparison circuit 6. When a match is detected in the comparison circuit 6, it is determined that no defect exists in the SRAM. If no match is detected, the SRAM is determined to have a defect.

For example, in a test operation, when two data signals amplified by sense amplifiers 91 and 94 are compared, transmission gates 51a, 52b, 53a and 54b shown in FIG. 9 are turned on. Switching control of all transmission gates (TG) shown in FIG. 9 is performed by switching control signal S provided from I / O program circuit 4 shown in FIG.
This is performed in response to 11 to S14 and S21 to S24.

When data signals read by sense amplifiers 90 and 91 are compared, transmission gates 51a, 52b, 53b and 54
b turns on. Thereby, sense amplifiers 90 and 9
The data signal amplified by 1 is supplied to the comparison circuit 6.

FIG. 10 is a circuit diagram of one sense amplifier (for example, 91) shown in FIG. Referring to FIG. 10, sense amplifier 91 operates in response to complementary data signals D and / D read from the corresponding memory cell array, and outputs a current mirror circuit 911 that receives an output signal from current mirror circuit 911. And a state buffer 912. A drive circuit 913 for driving the read data line RD1 'is provided at the last stage of the tristate buffer 912.

In operation, the current mirror circuit 911
Is a signal ATD supplied from the ATD circuit shown in FIG.
1 in response to the supplied complementary data signal D
And / D. Tri-state buffer 912
When the signal ATD1 is not supplied, the driving circuit 913
Output node to a high impedance state. On the other hand, when signal ATD1 is applied, tristate buffer 912 outputs an amplified data signal via drive circuit 913 in response to applied data signals D and / D.

[0027]

Referring again to FIG.
When a normal data read operation is performed, for example, when data is read from the memory cell array of block BL1, transmission gates 51a and 52a are turned on. Therefore, the sense amplifier 91
Is amplified by an arrow AR shown in FIG.
As shown in FIG. This means that sense amplifier 91 needs to drive data bus DB 'via two transmission gates 51a and 52a. Therefore, since the load to be driven by the sense amplifier 91 is large,
This causes a reduction in the data reading speed.

In addition, in a normal data read operation, as indicated by broken line arrow AR2, transmission gates 53a and 54a are also on, so that the load to be driven by sense amplifier 91 is further increased. This also hinders the high-speed reading operation.

The present invention has been made to solve the above-described problems, and has as its object to improve the data reading speed in a semiconductor memory device.

[0030]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cell arrays; a redundant memory cell array for functionally replacing defective memory cells in the plurality of memory cell arrays; each There a plurality of sense amplifying means for amplifying a data signal read from the corresponding memory cell array, a plurality of Senpuanpu means
Are connected to the first drive circuit means of each of a plurality of sense amplifier means, the first and second drive circuit means included in the first and second drive circuit means, the redundant sense amplifier means for amplifying the data signal read from the redundant memory cell array. A data transmission line, data output circuit means for outputting a data signal to the outside, and a first connected between the data transmission line and the data output circuit means, the first being electrically connected when data signals are read from the plurality of memory cell arrays. Switching means, connected between the redundant sense amplifier means and the data output circuit means,
A second switching means for data signals from the redundant memory cell array is conducted when it is read, a plurality of Memorise
Plurality of second drive circuit means respectively corresponding to the array
And data signal output from redundant sense amplifier means
Comparison circuit for comparing between two data signals of
Including steps .

According to a third aspect of the present invention, there is provided a semiconductor memory device including a plurality of memory cell arrays, a plurality of sense amplifiers each amplifying a data signal read from the corresponding memory cell array, and at least one of the plurality of sense amplifiers. A first data transmission line connected to one output node, a second data transmission line connected to output nodes of a plurality of sense amplifiers excluding the at least one output node, and a test mode provided from outside A comparing means for comparing data signals on the first and second data transmission lines in response to the signal; and a test mode signal connected between the first and second data transmission lines and responsive to an externally applied test mode signal. Switching means that is non-conductive.

[0032]

According to the semiconductor memory device of the present invention, a plurality of sense amplifiers and a redundant sense amplifier are provided.
The stage and the data output circuit means are connected by first and second switching means, ie, one switching means, respectively . Therefore, the comparison circuit means
For multiple memory cell arrays and redundant memory cell arrays
Therefore, in a configuration that can be shared, the data output circuit means
Therefore, when a data signal is output, the load to be amplified by the sense amplifier means is reduced, and the data reading speed is improved.

In the semiconductor memory device according to the third aspect of the present invention, the switching means is turned off only in the test mode operation, and is turned on in the normal reading operation. Therefore, in the normal read operation, the first and second data transmission lines are connected via one switching means, so that the load to be amplified by the sense amplifier means is reduced, and the data read speed is improved.

[0034]

FIG. 1 is a block diagram showing a connection between a sense amplifier and a data transmission line according to an embodiment of the present invention. Referring to FIG. 1, each of sense amplifiers 71 to 74
Receives data signals read from the memory cell arrays in corresponding blocks BL1 to BL4. Sense amplifier 90 receives a data signal read from a memory cell array in a redundant block. Each of the sense amplifiers 71 to 74 includes two drive circuits described later (not shown). Each first drive circuit of the sense amplifiers 71 to 74 is connected to a read data line RD.
On the other hand, the second drive circuits of sense amplifiers 71 and 72 are connected to test data line TD1. On the other hand, the second drive circuits of sense amplifiers 73 and 74 are connected to test data line TD2. The drive circuit of sense amplifier 90 is connected to redundant read data line RRD. Redundant read data line RRD is connected to redundant test data line RTD.

The switching circuit 57 includes a read data line R
D and redundant read data line RRD and data bus DB. The switching circuit 57 includes two transmission gates 57a and 57b. When data is read from a normal memory cell array, transmission gate 57a is turned on, and the data signal amplified by any of sense amplifiers 71 to 74 is applied to data bus DB. When data is read from the redundant memory cell array, transmission gate 57b is turned on, and the data signal amplified by sense amplifier 90 is applied to data bus DB.

The switching circuit 55 is connected between the test data line TD 1 and the redundant test data line RTD and the first input node of the comparison circuit 6. Switching circuit 55 includes two transmission gates 55a and 55b. In the test operation, the block BL
When the data signal read from the memory cell array of BL1 or BL2 is compared, the transmission gate 5
5a turns on. On the other hand, when data signals read from the redundant memory cell array are compared, transmission gate 55b is turned on.

The switching circuit 56 also has two transmission gates 56a and 56b, and is connected and operates in the same manner as the switching circuit 55. By improving the I / O program circuit 4 shown in FIG. 4, a switching control signal for controlling the switching circuits 55 to 57 is generated.

When a normal data read operation is performed,
For example, when the data signal amplified by sense amplifier 71 shown in FIG. 1 is read, the data signal amplified along the path indicated by arrow AR3 is transferred to data bus DB.
Given to. That is, the data signal amplified by sense amplifier 71 is applied to data bus DB via read data line RD and conductive transmission gate 57a. Therefore, the first drive circuit in the sense amplifier 71 includes one transmission gate 5
It suffices to drive the data bus DB via 7a, and the load to be driven is reduced as compared with the case shown by arrows AR1 and AR2 in FIG. Therefore, a faster data read operation can be achieved.

FIG. 2 is a circuit diagram of one sense amplifier (for example, 71) shown in FIG. Referring to FIG. 2, sense amplifier 71 includes a current mirror circuit 711 operating in response to complementary data signals D and / D read from the memory cell array, and a tristate buffer connected to an output of current mirror circuit 711. 712 and 71
3 is included. Each tri-state buffer 712 and 7
13 is a read data line RD and a test data line TD1
Are provided with drive circuits 714 and 715 for driving.

The current mirror circuit 711 is activated in response to a signal ATD1 provided from the ATD circuit.
When signal ATD1 is not applied, tri-state buffers 712 and 713 bring the output nodes of corresponding drive circuits 714 and 715 into a high impedance state. When test mode signal / TM at a high level is applied, an amplified data signal is applied to read data line RD via drive circuit 714. On the other hand, when the low-level test mode signal / TM is applied, the drive circuit 7
The amplified data signal is supplied to the test data line TD1 via the line 15.

FIG. 3 is a block diagram showing a connection between a sense amplifier and a data transmission line according to another embodiment of the present invention. In the embodiment shown in FIG. 1, an example is shown in which the present invention is applied to an SRAM having a redundant memory cell array, but in the embodiment shown in FIG. 3, the present invention is applied to an SRAM having no redundant memory cell array. The example applied to is shown. Referring to FIG. 3, each of sense amplifiers 91 to 94 receives a data signal read from a memory cell array in corresponding block BL1 to BL4. Drive circuits (not shown) for sense amplifiers 91 and 92 are connected to first read data line RD1. Similarly, drive circuits (not shown) for sense amplifiers 93 and 94 are
Is connected to the read data line RD2. First read data line RD1 is connected to second read data line RD2 via transmission gate 58.

In a normal data read operation, transmission gate 58 is turned on. Therefore, first and second read data lines RD1 and RD2 function as one read data line functionally. Each sense amplifier 91
And the drive circuits in 92 need only drive the second read data line RD2 via the transmission gate 58. Therefore, the load to be driven by the drive circuits in the sense amplifiers 91 and 92 corresponds to the arrow AR in FIG.
1 and AR2, so that a higher data read speed can be obtained.

In the test mode operation, transmission gate 58 turns off in response to test mode signal TM. Therefore, the data signal amplified by sense amplifier 91 or 92 and sense amplifier 93 or 9
The data signal amplified by 4 is supplied to the comparison circuit 6. By detecting a match in the comparison circuit 6,
It is determined that no defect exists in the SRAM.
Conversely, if a mismatch is detected, it is determined that a defect exists in the SRAM.

Thus, as shown in the embodiments of FIGS. 1 and 3, the drive circuit in one sense amplifier drives the read data line via one transmission gate in a normal data read operation. can do. Therefore, the load to be driven by the drive circuit in the sense amplifier is reduced as compared with the case of the circuit configuration shown in FIG. 9, so that the data reading speed in the SRAM can be improved.

In the above embodiment, an example in which the present invention is applied to an SRAM has been described. However, it is pointed out that the present invention can be generally applied to a semiconductor memory.

[0046]

As it is evident from the foregoing description, according to the present invention, compared
The circuit means may include a plurality of memory cell arrays and a redundant memory cell.
Data output circuit under a configuration that can be shared by
In the case where the data signal is output by the switching means , each sense amplifier means can drive a load for data reading through one switching means, so that a semiconductor memory device having a higher data reading speed can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a connection between a sense amplifier and a data transmission line according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of one sense amplifier shown in FIG.

FIG. 3 is a block diagram showing a connection between a sense amplifier and a data transmission line according to another embodiment of the present invention.

FIG. 4 is a block diagram of an SRAM showing the background of the present invention.

FIG. 5 is a circuit diagram of one memory cell array shown in FIG. 4;

FIG. 6 is a circuit diagram illustrating an example of a memory cell illustrated in FIG. 5;

FIG. 7 is a circuit diagram showing another example of the memory cell shown in FIG. 5;

FIG. 8 is a timing chart illustrating a read operation of the memory cell shown in FIG. 5;

FIG. 9 is a block diagram illustrating a connection between the sense amplifier and the data transmission line illustrated in FIG. 4;

FIG. 10 is a circuit diagram of one sense amplifier shown in FIG. 9;

[Explanation of symbols]

 6 Comparison circuit 55, 56, 57 Switching circuit 71-74, 90 Sense amplifier TG Transmission gate RD Read data line RRD Redundant read data line TD1, TD2 Test data line RTD Redundant test data line DB Data bus

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ identification code FI G11C 11/34 371A (58) Investigated field (Int.Cl. ⁷ , DB name) G11C 29/00 G11C 11/413 G11C 11 / 401

Claims (3)

(57) [Claims] A plurality of memory cell arrays each including a plurality of memory cells arranged in rows and columns; and a plurality of memory cell arrays arranged in rows and columns and including defective memory cells in the plurality of memory cell arrays. includes a redundant memory cell array having a plurality of redundant memory cells for replacing, and a plurality of sense amplifying means each for amplifying a data signal read from a corresponding one of said plurality of memory cell array, said plurality Each of the first and the second
Of a drive circuit unit, wherein the redundant sense amplifier means for amplifying data read signals from the redundant memory cell array, driving each of said first of said plurality of sense amplifiers means
A data transmission line connected to the driving circuit; a data output circuit for outputting the data signal to the outside; a plurality of memory cell arrays connected between the data transmission line and the data output circuit; A first switching unit that is turned on when a data signal is read from the memory cell array, and is connected between the redundant sense amplifier unit and the data output circuit unit, and is turned on when a data signal is read from the redundant memory cell array. Second switching means, and a plurality of memory cells respectively corresponding to the plurality of memory cell arrays.
The second drive circuit means and the redundant sense amplifier
Two of the data signals output from the stage
A semiconductor memory device further comprising comparison circuit means for comparing between the two . 2. The comparison circuit means is provided externally.
In response to the test mode signal, the two input nodes
A comparison is made between the given data signals, and the semiconductor memory device is connected to at least one of the second drive circuit means.
A first test data transmission line and the second test circuit except the at least one second drive circuit means;
Test data transmission connected to the second drive circuit means
And the first test data transmission line and the redundant sensor.
Sampling means and one of the two input nodes
A third switching means for connecting the second test data transmission line and the redundant sensor to each other;
Sampling means and one of the two input nodes
And a fourth switching means for connecting the other.
The semiconductor memory device according to claim 1, comprising: 3. A plurality of memory cell arrays each having a plurality of memory cells arranged in rows and columns, and a plurality of each amplifying data signals read from a corresponding one of the plurality of memory cell arrays. , A first data transmission line connected to at least one output node of the plurality of sense amplifiers, and connected to output nodes of the plurality of sense amplifiers except the at least one output node. Comparing means for comparing data signals on the first and second data transmission lines in response to an externally applied test mode signal; and the first and second data transmission lines. Switching means connected between the lines, and turned off in response to an externally applied test mode signal.