JP3048160B2 - Wafer scale semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] Overview Industrial application field Conventional technology (FIGS. 3 and 4) Problems to be solved by the invention Means for solving the problem Actions Example Principle of the present invention (No. 1) One embodiment of the present invention (FIG. 2) Effects of the Invention [Overview] Regarding a wafer scale semiconductor device, a defective chip can be electrically insulated, and an abnormal current flowing through the defective chip can be completely prevented. The purpose of the present invention is to provide a wafer-scale semiconductor device capable of performing operations, comprising a plurality of chips on a wafer as constituent elements, avoiding defective chips, reconfiguring a communication path between the chips, and setting a predetermined path for the entire wafer. In the wafer scale semiconductor device having the function of (1), the chip is provided with a cutoff means for cutting off a signal line connecting the chips, and the cutoff means is provided when a chip has a defect. Characterized by being adapted to block the signal line input to and output from the defective chip by not performing the bonding to the defective chip high-potential-side power supply.

Further, the blocking means is provided in a path of the signal line, a transistor having a gate connected to a high-potential-side power supply, and a resistor connected between the gate of the transistor and the low-potential-side power supply. It is characterized by having.

[Industrial applications]

The present invention relates to a wafer scale semiconductor device, and more particularly, to a defect avoidance technology in wafer scale integration (WSI) configured by combining all chips formed on one semiconductor wafer. Regarding improvement.

Wafer scale integration (WSI) integrates circuits over the entire area of the wafer, and this technology offers the following advantages:

What kind of LSI (large scale integrated circuit)
Larger-scale circuits can be integrated.

By integrating the system on one wafer,
The interconnection length between circuits is shortened, and the signal extension time can be shortened.

The reliability of the mounting can be improved by reducing the number of assembling steps, and the reliability of the system can be improved by the defect relief technique.

The WSI is suitable for monolithically configuring a repetitive logic circuit or memory in which a plurality of basic constituent circuits are connected. In the case of a monolithic WSI, circuits must be integrated in a wide area that always includes a defective part. Therefore, a defect avoidance technique for providing a redundant configuration and bypassing the defect to configure a system is indispensable.

[Conventional technology]

In a wafer-scale memory, which is a type of conventional WSI, if the direction of the orientation main flat is the X direction and the direction orthogonal thereto is the Y direction, the X and Y directions between chips are connected by a local line. When a signal is applied from the input terminal, the signal is configured to bypass the defective chip and pass only the non-defective chips serially to appear at the output terminal. Further, in the Y direction, a command line and a command line are provided for each chip column. A parallel connection is performed by a global line composed of WCK lines, V _CC lines, V _SS lines, V _BB lines, etc. (see JP-B-58-18778 and JP-B-62-6267). . Note that the above chips are not simply connected by a local line, but a logic circuit is interposed therebetween.It is also necessary to connect only good chips serially, bypassing defective chips. Is referred to as constituting a spiral passage.

A conventional wafer scale memory is shown, for example, in FIG. FIG. 3 is a diagram schematically showing a part of a chip portion of the wafer scale memory, and the blocks in the figure show each chip 1. Signal lines 2 to 5 for exchanging bidirectional information are connected between the chips 1. The exchange of signals between the chips of the wafer scale memory will be specifically described. FIG. 4 is a diagram for explaining the exchange of signals between the A chip 11 and the B chip 12, and shows a hardware configuration of an input / output stage of the chip. In FIG. 4, an A chip 11 surrounded by a broken line includes an inverter 13 including a P-channel transistor Trl and an N-channel transistor Tr2, and an inverter 14 including a P-channel transistor Tr3 and an N-channel transistor Tr4.
And an N-channel transistor Tr5 for low-clamping the input level input to the inverter 14. Similarly, the B chip 12 has an inverter 16 composed of a P-channel transistor Tr6 and an N-channel transistor Tr7 for outputting a signal to the inverter 14 of the A chip 11 via a signal line 15, and a signal from the inverter 13 of the A chip 11 An inverter 18 composed of a P-channel transistor Tr8 and an N-channel transistor Tr9 input via a line 17, an N-channel transistor Tr10 for low-clamping an input level input to the inverter 18,
It consists of. The reason that the transistors Tr5 and Tr10 are inserted before the inverters 14 and 18 and clamped to the low side is because it is not known what kind of signal is input as an input signal, and the voltage level is inserted by inserting Tr5 and Tr10. In order to stabilize the circuit operation.

[Problems to be solved by the invention]

However, in such a conventional wafer scale semiconductor device, the chip for transmitting information and the chip for receiving information are simply connected by the signal lines 15 and 17 as shown in FIG. Therefore, when a certain chip is defective, there is a problem that an abnormal current flows from the next electrically connected chip to the defective chip. For example, if the A chip 11 shown in FIG. 4 has a defect, a measure is taken to prevent such a defective chip from being bonded. However, even if the bonding is not performed, the high potential of the adjacent B chip 12 is used. A from power supply V _CC via signal lines 15 and 17
The situation that an abnormal current flows into the chip 11 was inevitable.

Therefore, an object of the present invention is to provide a wafer-scale semiconductor device that can electrically insulate a defective chip and completely prevent abnormal current flowing through the defective chip.

[Means for solving the problem]

A wafer-scale semiconductor device according to the present invention has a plurality of chips on a wafer as constituent elements to achieve the above object,
In a wafer-scale semiconductor device in which a communication path between chips is reconfigured by avoiding a chip having a defect and a predetermined function is provided to the entire wafer, the chip is provided with a cutoff means for cutting off a signal line connecting the chips. The interrupting means interrupts a signal line input / output to / from the defective chip by not performing bonding of the defective chip to a high-potential-side power supply when a certain chip has a defect. And

Further, the blocking means is provided in a path of the signal line, a transistor having a gate connected to a high-potential-side power supply, and a resistor connected between the gate of the transistor and the low-potential-side power supply. It is characterized by having.

[Action]

In the present invention, the input / output circuit of the chip is provided with a cut-off means for cutting a signal line connecting the chips, and when there is a defective chip, the defective chip is electrically disconnected by the cut-off means.

Therefore, an abnormal current flowing from a chip around the defective chip to the defective chip is reliably prevented.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

Explanation of principle FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, reference numeral 21 denotes a wafer scale memory (wafer scale semiconductor device), and reference numerals 22 to 25 denote a wafer scale memory.
The memory 21 is a chip, and the chips 22 to 25 are signal lines 31 to 38.
, And switches (cutoff means) 41 to 48 for electrically disconnecting the defective chip when a certain chip has a defect are provided on the signal lines 31 to 38.

Therefore, the signal line 31 for chip-to-chip exchange
38, switches 41 to 48 are provided, and if there is an abnormal current source chip 25, the abnormal chip 25 is separated by the switches 45 to 48 connected to the abnormal chip 25. Insulated from surrounding chips 23, 24
The abnormal current from flowing into the abnormal chip 25 is completely prevented.

One Embodiment An actual device based on the above principle will be described as an embodiment. FIG. 2 is a view showing one embodiment of a wafer scale semiconductor device according to the present invention, and the same components as those of the conventional example shown in FIG. 2 are denoted by the same reference numerals and symbols. FIG. 2 is a diagram in which some chips (A chip 51 and B chip 52) in the wafer scale semiconductor device are extracted, and the output stage of the A chip 51 has an inverter composed of a P-channel transistor Tr1 and an N-channel transistor Tr2. 13, an N-channel transistor Tr11 (blocking means) provided in the path of the signal line 17 and having a gate connected to the high-potential-side power supply V _CC , and a gate of the transistor Tr11 and the low-potential-side power supply V _SS (or V _BB )
And an input stage of the A chip 51 is a P-channel transistor Tr3.
And an inverter 1 consisting of an N-channel transistor Tr4
4, an N-channel transistor Tr5 for low-clamping the input level input to the inverter 14, and a signal line 1
An N-channel transistor Tr12 (interrupting means) provided in five paths and having a gate connected to the power supply V _CC ,
High resistance R2 connected between the gate of Tr12 and the power supply V _SS
, And is constituted.

Similarly, the output stage of the B chip 52 is provided in a path of the signal line 15 and an inverter 16 including a P-channel transistor Tr6 and an N-channel transistor Tr7 for outputting a signal to the inverter 14 of the A chip 11 via the signal line 15. An N-channel transistor Tr13 (blocking means) having a gate connected to the power supply V _CC , and a high resistance R3 connected between the gate of the transistor Tr13 and the power supply V _SS (or V _BB ), , The input stage of the B chip 52 receives the signal from the inverter 13 of the A chip 11 via the signal line 17 to the P stage.
An inverter 18 composed of a channel transistor Tr8 and an N-channel transistor Tr9, an N-channel transistor Tr10 for low-clamping the input level input to the inverter 18, and a signal line 17 provided in the path, and a gate connected to the power supply V _CC N-channel transistor Tr14
(Cutoff means), the gate of transistor Tr14 and power supply V _SS
And a high resistance R4 connected between them. Therefore, the signal line from the A chip 51 to the B chip 52
17 is connected to transistors Tr11 and Tr14, and high and low resistances R1 and R4 are connected to the gates of the transistors Tr11 and Tr14, respectively.
The signal line 15 from the chip 52 to the A chip 51 is a transistor
High resistances R2 and R3 are connected to the gates of Tr12 and Tr13 and the respective transistors Tr11 and Tr14. FIG. 2 shows only an input / output stage of a pair of adjacent chips (A chip 51 and B chip 52) among a large number of chips of the wafer scale memory. As shown in the figure, a similar signal line, a switch composed of a transistor and a high resistance is connected to all chips adjacent to the front, rear, left and right.

In the above configuration, assuming that there is a short circuit between V _SS and V _BB in the A chip 51 and does not bond the V _{CC of the} A chip 51, the gates of the transistors Tr11 and Tr12 have high and low resistances R1 and R2. because it is connected to V _SS (or V _BB) through the gate of the transistor Tr11, Tr12 by not Bonding the V _CC falls to L level, the transistors Tr11, Tr12 is cut off. As a result, the A chip 51 and the B chip 52 are completely electrically insulated from each other, and the flow of an abnormal current from the B chip 52 to the A chip 51 is prevented. In particular, in the present embodiment inserts a transistor Tr11~Tr14 to the signal lines 17 and 15, as well as a gate connected to V _CC, and so as to connect the gate to V _SS via a high resistance R1~R4 Therefore, avoiding bonding of a defective chip itself directly leads to cutting of the signal line, and does not cause an increase in the number of working steps as compared with the conventional example. Therefore, with a simple circuit configuration, it is possible to reliably prevent abnormal current in the wafer that could not be cut off with or without bonding, and to improve the defect avoidance technology of the wafer-scale semiconductor device.

〔The invention's effect〕

According to the present invention, a defective chip can be electrically insulated, and abnormal current flowing through the defective chip can be completely prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view for explaining the principle of the present invention, FIG. 2 is an input / output circuit diagram of a chip showing one embodiment of a wafer-scale semiconductor device according to the present invention, and FIGS. FIG. 3 is a diagram showing a conventional wafer scale semiconductor device, FIG. 3 is a diagram showing a connection state between chips, and FIG. 4 is an input / output circuit diagram of the chip. 13, 14, 16, 18 ... inverter, 15, 17 ... signal line, 21
…… Wafer-scale memory (wafer-scale semiconductor device), 22-24… Normal chip, 25 …… Abnormal chip,
31-38: signal line, 41-48: switch (cutoff means),
51 A chip, 52 B chip, Tr1, Tr3, Tr6, Tr8
...... P-channel transistor, Tr2, Tr4, Tr5, Tr7, Tr
9, Tr10: N-channel transistor, Tr11 to Tr14 ...
N-channel transistor (blocking means), R1 to R4: high resistance, V _CC: high-potential power supply, V _SS (V _BB ): low-potential power supply.

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁷ Identification code FI H01L 27/04 M

Claims (2)

(57) [Claims] A plurality of chips on a wafer as constituent elements;
In a wafer scale semiconductor device in which a communication path between chips is reconfigured by avoiding a chip having a defect and a predetermined function is provided to the entire wafer, the chip is provided with a cutoff means for cutting off a signal line connecting the chips. The interrupting means is configured to interrupt a signal line input / output to / from the defective chip by not bonding the defective chip to a high-potential-side power supply (V _CC ) when the defective chip is defective. A wafer-scale semiconductor device. 2. The circuit according to claim 1, wherein said shut-off means is provided in a path of said signal line, and has a gate connected to a high-potential-side power supply (V _cc ) and transistors (Tr11, Tr12, Tr13, Tr14). The resistors (R1, R2) connected between the gates of the transistors (Tr11, Tr12, Tr13, Tr14) and the low-potential-side power supply (V _SS )
2, R3, R4), and the following.
Scale semiconductor device.