JP3047386B2 - Feedback type pulse width modulation A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a feedback type pulse width modulation A / A
The present invention relates to a D converter, and more particularly to improvement of a circuit in which an analog section and a digital section are insulated by a photocoupler.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing an example of a conventional feedback pulse width modulation (hereinafter referred to as PWM) A / D converter. In the figure, 1 is a PWMA / D unit, 2 is an input unit for switching a gain and the like, and 3 is a control unit for controlling the PWMA / D unit 1 and the input unit 2. The PWMA / D unit 1 and the control unit 3 are connected to a CP (not shown).
Photocouplers PC1 to PC6 for optically coupling the digital part and the analog part are provided between the external circuit such as U.

That is, the PWMA / D unit 1 is provided with a photocoupler PC1 for transmitting a PWM output PW, a photocoupler PC2 for transmitting a feedback signal FB, and a photocoupler PC3 for transmitting a carrier EC. Is a photocoupler P for transmitting control data DATA
Photocoupler PC5 for transmitting C4 and data clock DCLK and strobe pulse STR for data latch
A photocoupler PC6 for transmitting B is provided.

In such a configuration, the input unit 2 is controlled under the control of the control unit 3 so as to normalize the input signal to a value suitable for the conversion characteristics of the PWMA / D unit 1, and the PWMA
An offset is added to the / D unit 1 as needed so that the conversion range of, for example, ± 2 V becomes 0 to 4 V based on the control of the control unit 3. FIG. 4 is a circuit diagram showing an example of the PWMA / D unit 1. Reference numeral 8 denotes an input terminal of the converted analog input signal Vin, which is connected via a resistor 9 to an inverting input terminal of an operational amplifier 10 constituting an integrator I. A capacitor 1 is connected between the inverting input terminal and the output terminal of the operational amplifier 10.
1 is connected, and the non-inverting input terminal is connected to the common potential point. An operational amplifier 12 is used as a comparator. The output terminal of the operational amplifier is connected to a non-inverting input terminal, and the inverting input terminal is connected to a common potential point. The output terminal of the operational amplifier 12 is connected to the data terminal of the flip-flop 14 via the photocoupler 13. The output terminal of the flip-flop 14 is AND gate 1
5 is connected to one input terminal, and its output signal PWM 'is supplied via a photocoupler 16 to a changeover switch 17
Is added as a switching drive signal. One fixed contact a of the changeover switch 17 is connected to the anode side of the reference voltage source + Vs, and the other fixed contact b is connected to the reference voltage source -Vs
The movable contact is connected to the inverting input terminal of the operational amplifier 10 via the resistor 18. Reference numeral 19 denotes a count clock generation circuit that outputs a count clock CCK, and its output terminal is connected to the clock terminal of the flip-flop 14 and to the other input terminal of the AND gate 15. The output terminal of the AND gate 15 is connected to a counter (not shown). Reference numeral 20 denotes a basic clock generation circuit for outputting a basic clock CK for keeping the integration cycle of the integrator I constant for removing the influence of the frequency of the commercial power supply. It is connected to an inverting input terminal of the operational amplifier 10 via a capacitor 23 for cutting off components and a resistor 24. Note that the basic clock CK and the count clock CCK are synchronized.

Here, the basic clock CK corresponds to a carrier. The photocouplers 13, 16, and 21 are used to electrically insulate the analog and digital sections. The photocoupler 13 corresponds to PC1, the photocoupler 16 corresponds to PC3, and the photocoupler 21. Corresponds to PC2. In such a configuration, the comparator 12 outputs a signal PWM having a pulse width proportional to the amplitude of the converted analog input signal Vin. That is, by measuring the pulse width of the signal PWM, the value of the amplitude of the converted analog input signal Vin can be obtained. Therefore, using the signal PWM as a gate signal, the time related to the pulse width is counted by the count clock CCK. The flip-flop 14
Is provided to output a signal PWM synchronized with the count clock CCK.

[0006]

However, according to such a conventional structure, six photocouplers are required for signal insulation transmission with an external circuit, which is preferable in terms of cost and component mounting space. Absent. Also, when the carrier is supplied via a photocoupler, the duty ratio deviates from 50% due to a signal delay in the photocoupler or the like, so that the PWMA
There is also a problem that an offset error occurs in the output of the / D unit 1.

An object of the present invention is to solve such a problem. An object of the present invention is to realize a feedback type pulse width modulation A / D converter which can reduce the number of photocouplers for signal insulation transmission and has a small offset error. Is to do.

[0008]

SUMMARY OF THE INVENTION In order to solve such a problem, the present invention solves the above-mentioned problems by providing an analog input based on a carrier.
Feedback pulse width modulation A for converting a force signal into a pulse width signal
/ D converter and analog input signal amplitude is feedback pulse
Gain to match the conversion characteristics of the width modulation A / D converter
Input section and the data clock
These feedback pulse width modulations A
And / D converter and a control unit for controlling the input unit, these de
Data clock and control data from the outside to the control unit.
Photocouplers that are individually supplied and this photocoupler
Divides the data clock applied via
And a frequency dividing circuit for generating the rear .

[0009]

According to the present invention, feedback pulse width modulation A
The carrier of the / D converter is generated by dividing the frequency of a data clock applied via a photocoupler. This allows
It is possible to omit a photocoupler for insulatingly transmitting a carrier which is conventionally required.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of one embodiment of the present invention, and the same parts as those in FIG. 3 are denoted by the same reference numerals. In the figure, reference numeral 4 denotes a frequency dividing circuit, which is a photocoupler PC5.
A carrier is generated by dividing the frequency of a data clock externally applied via the external clock (see FIG. 3) and supplied to the PWMA / D unit 1.

FIG. 2 is a timing chart for explaining the operation of FIG. In the figure, control data DATA for setting the gain of the input unit 2 and the offset of the PWMA / D unit 1 is transmitted from the CPU in synchronization with the data clock DCLK, and is latched by the strobe STRB. On the other hand, the data clock DCLK is sequentially frequency-divided and supplied to the PWMA / D unit 1 as a carrier. Specifically, for example, the frequency of the data clock DCLK having a frequency of 4.8 KHz is divided to 1.2 KHz.

Since the operation of the circuit is the same as that of the conventional circuit, the description is omitted. With this configuration, only five photocouplers, which were required in the past, are now required, and component cost and mounting space can be improved. In addition, since the carrier is generated by dividing the data clock DCLK, the duty of the carrier is 50% because the waveform is shaped by the divider circuit 4, so that the offset error due to the photocoupler transmission can be improved. .

[0013]

As described above, according to the present invention,
The number of photocouplers for signal insulation transmission can be reduced, and a feedback pulse width modulation A / D converter having a small offset error can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of FIG.

FIG. 3 is a block diagram showing an example of a conventional feedback pulse width modulation A / D converter.

FIG. 4 is a circuit diagram showing an example of a conventional feedback pulse width modulation A / D converter.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PWMA / D part 2 Input part 3 Control part 4 Divider circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-60525 (JP, A) JP-A-57-49866 (JP, A) JP-A-61-81029 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (1)

(57) [Claims] An analog input signal is transmitted based on a carrier.
Feedback pulse width modulation A / D converter for converting to pulse width signal
And the amplitude of the analog input signal is changed by the feedback pulse width modulation A / D conversion.
Switch the gain to match the conversion characteristics of the
Based on power and control data applied according to the data clock
These feedback pulse width modulation A / D converters and input units
Control section and externally control these data clock and control data
And the data clock applied via this photocoupler.
Frequency dividing circuit for generating the carrier by dividing the feedback type pulse width, characterized in that it is constituted by a capital modulation A
/ D converter.