JP3047009B2 - Image creation apparatus and image creation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus, and more particularly to speeding up drawing input (brush input).

[0002]

2. Description of the Related Art In an image forming apparatus, it is required to increase the speed of input processing of drawing data, and this is becoming more difficult as the resolution is improved. The processing amount required for processing the drawing data is proportional to the square of the resolution. For this reason, a low-resolution image memory and a high-resolution image memory are prepared, the drawing data is processed at a low resolution for the time being, and displayed on a monitor. In parallel with this, processing is also performed at a high resolution, and a high-resolution image is displayed after the processing is completed. In this processing, real-time processing is maintained by processing at a low resolution, and image quality is maintained by processing at a high resolution. Then, processing at low resolution is used so that processing at high resolution may be delayed from drawing input.

[0003] However, the demand for image quality has further increased, and it has become necessary to perform parallel processing on the high resolution image side for drawing input. As an example of parallel processing, the inventor
The ones shown in FIGS. In the example of FIG. 5, a drawing position is specified for an image on a monitor by a digitizer or the like,
This is received by the sequencer 2 and arranged in a queue or the like.
One patch is divided into, for example, four patches and parallel processing is performed. Each drawing pipeline includes means 4-1 to 4-4 for generating a density distribution signal of the brush used for drawing, and multiplying means 6-1 to 6
-4 are arranged in series, and barrel RAM 8 is used for area RAM.
10 is accessed at high speed, and processing for one patch is performed.

When the processing of one patch is completed, the next patch is similarly divided into four parts and processed. After the processing of one stroke is completed, the high-resolution image stored in the file memory 14 and the input image stored in the area RAM 10 are processed. Are blended by the linear interpolation unit 12. As described above, the principle of drawing is to process a plurality of patch arrays one by one in order. In the processing of the data of one patch, pixel data of one patch is sequentially read out from the area RAM 10 and multiplied by the signal of the density generating means 4 by the multiplying means 6.
Writing back to 10. Since a plurality of patches are overlapped, recursive processing is performed on the same pixel in the area RAM 10.

FIG. 6 shows the division of a patch.
6 are divided into four parts. In FIG. 6, the processing of the patch P1 has been completed, and the processing of the patch P2 has been performed. Then, the patch P2 is divided into regions P2-1 to P2-4 shown in the lower part of the figure, and the processing is completed up to the region 16 in each region, and the region 18 is unprocessed.

FIG. 7 shows processing of a stroke composed of patches P1 to Pn. Assuming that four systems of drawing pipelines are provided, each patch is divided into four parts, and the first area is defined as the first area.
, The second region is processed by the second pipeline, and the third and fourth regions are processed by the third and fourth pipelines. Each pipeline performs processing in units of patches, and data reading from the area RAM and writing of processing results (access cycle in the figure) and mixing operation of input data and data in the area RAM (multiplication cycle) are performed in parallel. Will be

By providing a plurality of drawing pipelines, the speed of the mixed operation during the drawing process is increased. However, the number of accesses to the area RAM 10 has not decreased. For example, if one patch is composed of 10 k pixels, and processing of 10 patches is necessary, the number of accesses to the area RAM is once for reading and writing, and each pixel is accessed twice for each patch. , Total 10k × 10
× 2, which is 200k. When parallelization is performed in this way,
Even if the operation speed can be increased, there is a limit because the number of accesses to the memory does not decrease. In other words, it is necessary not only to speed up the operation part during the drawing process but also to speed up the access to the memory.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to reduce the number of accesses to a memory and facilitate the speeding up of a drawing input process.

[0009]

According to the present invention, an image in the course of creation is stored in a memory and displayed on a monitor, a position on the display image is designated, and drawing data is input in units of a patch composed of a plurality of pixels. Means for determining a processing range consisting of at least one pixel from a drawing range consisting of a plurality of patches, wherein the processing range is determined until the processing in the processing range ends. And a processing means for repeatedly performing processing for a plurality of patches.
That is, in the present invention, instead of processing the drawing range for each patch and completing the processing in the patch and then proceeding to the processing of the next patch, processing of a plurality of patches is performed for each processing range including a small number of pixels. After processing a plurality of patches for one processing range, the next processing range is processed.

Preferably, a plurality of said drawing pipelines are provided, and said drawing range is spatially divided and assigned to each drawing pipeline to a plurality of regions having different positions on said drawing range. Process in parallel.

Preferably, the processing means includes density generating means for generating drawing density data of each pixel in each patch, serially arranged, a multiplying means, and a register. Repeats multiplication of the data stored in the register by the data of the density generating means for a plurality of patches on the data stored in the register.

More preferably, the processing range is set to one pixel, and the register is constituted by an accumulator, and the same pixel is repeatedly processed by the number of patches, thereby simplifying the configuration of the drawing pipeline.

Preferably, a cache memory is provided on the output side of the drawing pipeline to serve as a buffer between the memory storing the image and the drawing pipeline. The cache memory may be a small-scale memory, and does not need a capacity to store the entire assigned divided area.

[0014]

According to the present invention, an image is created in which an image in the course of creation is stored in a memory and displayed on a monitor, a position on the displayed image is designated, and drawing data is input in patch units. The method further comprises: dividing a drawing range including a plurality of patches into a plurality of groups each including a plurality of pixels and having different positions on the drawing range; assigning the plurality of groups to a plurality of drawing pipelines; On the line, at least 1
A processing range composed of pixels is determined, and the processing for the plurality of patches is repeatedly performed on the determined processing range until the processing in the processing range is completed, thereby determining the processing range and determining the processing range. The process is repeated to process the assigned range.

In the present invention, the processing of the next processing range is started after the processing of the drawing range including the plurality of patches for the pixels within the processing range is completed. Therefore, the number of accesses to the memory is, for example, one reading and one writing for each pixel in the drawing range, and the number of accesses to the memory does not increase so much even if the number of patches increases. As a result, according to the present invention, the number of accesses to the memory can be suppressed, and the speed of drawing input can be increased in terms of access.

In order to speed up the calculation in the drawing process, preferably, a plurality of drawing pipelines are provided, and the drawing range is spatially divided into a plurality of regions at different positions on the drawing range and assigned. The operation speed is improved by parallel processing, and the number of accesses to the memory is not processed in units of patches, but in units of processing ranges. Therefore, increase is suppressed, and parallel processing of operations and suppression of the number of accesses reduce high-speed drawing processing. Can be performed.

In particular, a register or an accumulator is provided in each drawing pipeline to store density data of a small number of pixels, and multiplication of the drawing density data by the storage density data of the accumulator and the register is repeated. For example, after processing one pixel for a plurality of patches using an accumulator, the process moves to the next pixel, or after processing a plurality of patches for the pixels of the register, processing for the next pixel is performed. Move on. By doing so, the preparation of the data for multiplication and the multiplication can be performed in parallel, and the multiplication is performed for each pitch (one stage), so that the multiplication can be performed at high speed.

A cache memory (cache) is provided on the output side of each drawing pipeline, and writing to the cache is performed for each pixel, for example, each time processing of one stroke is completed. The total number of times of writing to the cache is on the order of the number of pixels included in the stroke. Even if the number of patches increases, the number of times of writing does not increase, so that the processing is simplified. This cache may be a small memory, and does not need to have a capacity for pixels included in one entire stroke, thereby reducing the hardware cost of the image forming apparatus. More preferably, a high-resolution image memory and a low-resolution image memory are provided, and a plurality of drawing pipelines are used. , And the low-resolution image side performs processing for each patch. In this way, real-time processing can be performed on the low resolution side, and highly accurate processing can be performed on the high resolution side.

[0019]

1 to 4 show an embodiment. FIG. 1 shows the structure of the image creating apparatus. Reference numeral 20 denotes a drawing pipeline, which is provided with a plurality of systems, and in the embodiment, four systems. The drawing pipeline 20 processes a first-in first-out queue 21 and an appropriate number of patch arrays accommodated in the queue 21, for example, one stroke at a time, and a sequencer for deleting the queue from the queue 21 after the processing is completed. 22, density generating means 23 for outputting the complement k of the input density in the drawing input data to each pixel in the patch, multiplying means 24, and accumulator 25
And a pipeline with the cache 26. Then, instead of the accumulator 25, for example, 16 or 64
A register for pixels or less may be used.

The density generating means 23 is, for example, one in which the brush shape of the patch is circular and the density is determined by the distance from the center of the circle (using a one-dimensional density table), or an appropriate two-dimensional brush. The shape is stored in RAM and RA
The density of the data of M, and the density of the data of the stylus of the digitizer as the drawing input means are used. The cache 26 has a capacity of, for example, 1K pixels, and the total of the four caches 26 is smaller than the drawing area corresponding to one stroke.

Of these, the two-dimensional brush shape itself has been widely used in image forming apparatuses. If the brush shape is two-dimensional, the brush data can be read only by obtaining the relative address of the pixel to be processed with respect to an appropriate brush origin such as the brush center. For this reason, in the conventional example, the brush data is read by changing the relative address by one using an address counter and reading the data. In this method, a large number of pixels are sequentially processed, and the next patch is not processed until the processing of all the pixels in the patch is completed.

On the other hand, in the embodiment, even when a two-dimensional brush shape is used, processing is performed not on a patch basis but on a pixel basis, and the same pixel in one stroke is continuously processed. For this reason, the relative address of the pixel with respect to the brush origin is obtained for each patch by calculation every time, and the address calculation itself becomes complicated. But still,
Since the density can be calculated by repeatedly multiplying the data of the accumulator and the like, the drawing process can be sped up. That is, since the data of the accumulator and the register are multiplied by the density data in the next patch of the same pixel, two bus cycles for reading and writing to the memory are unnecessary, and the density can be calculated according to the speed of the multiplying means 24. There is no factor that lowers the processing speed such as memory access. When one-dimensional brush data is used, the radius calculation from the center of the patch to the pixel to be processed is required even in the conventional method, and this is not changed in the embodiment. That is, when one-dimensional brush data is used, the load required for calculating addresses in a patch is the same in the embodiment and the conventional example.

Reference numeral 30 denotes a front-end processor which receives an input from a stylus or the like of a digitizer, and the stylus or the like designates a position on a display image on the monitor 46 through a cursor or the like, thereby changing an input position in a monitor coordinate system. specify. The front-end processor 30 manages menus and the like. The front-end processor 30
The drawing position in the monitor coordinate system is converted into the drawing position in the coordinate system in the stored image, and at the same time, the type of the brush and the color signal are output through menu management. The brush type corresponds to chalk, crayon, oil painting, etc., and the brush size is 1
Corresponds to the size of the patch. The patch is drawn by updating the storage data of the pixels in the patch within the drawing range specified by one drawing position. Then, one stroke is composed of a plurality of patches, and in the embodiment, drawing on a high-resolution image is performed in units of strokes. The patch size is, for example, about 10K pixels of 100 pixels × 100 pixels, and varies depending on the type of brush, and may vary depending on the pen pressure when pen pressure is used.

To supplement the hardware, the queue 21 stores data for specifying a row of a plurality of patches on a first-in first-out basis, including the center coordinates of each patch, and the type and size of the brush. . The sequencer 22 controls from the density generating means 23 to the cache 26. In this processing, for example, one pixel is selected from a row of a plurality of patches constituting one stroke, and the After processing, the next pixel is processed in the same manner. The coordinates of the pixel to be processed, the center coordinates of the brush, the size, and the data of the type are supplied from the sequencer 22 to the density generating means 23, and are written into the cache 26 (immediately before the processing of the next pixel is started), The output from 26 is also instructed from sequencer 22.

The density generating means 23 includes means for generating data relating to the density distribution of the brush, and data relating to the relative position of the pixel being processed with respect to the brush with respect to the center of the brush. Means for generating the relative addresses of the pixels. For example, it is assumed that a two-dimensional table is given as data relating to the brush density distribution, and the effect of pen pressure is ignored for simplicity. Such a table is stored in a separate memory (not shown) for each brush type, for example.
To be temporarily stored. During one stroke,
The brush type is constant, the coordinates of the pixel being processed are specified by the sequencer 22, and the brush position changes for each patch. This is a change in the relative address of the pixel being processed with respect to the brush. Thus, a relative address is obtained for each patch, density data for the pixel being processed is read from the table of brush density data, and supplied to the multiplying means 24.

When the data relating to the brush density distribution is, for example, a one-dimensional table, the center position and the like of the brush are supplied from the sequencer 22 to the density generating means 23 for each patch.
The density is generated by calculating the distance from the center of the brush or the like to the pixel being processed for each patch.

When the size of the brush is changed by the pen pressure, it is burdensome to change the data of the density distribution of the brush for each patch and store it in the density generating means 23. The brush size is changed by adding the pen pressure to the relative address by multiplication or the like. When the density of the brush is changed by the writing pressure, the output density of the density generating means 23 is obtained by multiplying the writing density by the writing pressure without adding the writing pressure. Further, when the density distribution of the brushes is stored in a plurality of tables and interpolation is performed between them by writing pressure, the density is obtained for the plurality of tables and the obtained density is interpolated.

The complement of the density signal in one-stroke drawing is spatially divided into four areas and stored in four caches 26. The density signal indicates the contribution of the color signal Q to the drawing input. And the complement of the density signal is the color signal P of the original image before drawing input stored in the high-resolution memory 32.
Shows the contribution of The color signal Q from the front end processor 30 and the color signal P from the high resolution memory 32
Are linearly interpolated by the linear interpolation processing unit 34 using the complement of the density signal in the cache 26. This interpolation itself is known. The image in the high resolution memory 32 is output to a printer or an external disk (not shown), and the resolution is reduced by the reduction processing unit 36 and input to the low resolution memory 38.

Between the front-end processor 30 and the low-resolution memory 38, a low-resolution density generating means 40 is provided.
The linear interpolation processing unit 42 reduces the number of pixels in one patch to, for example, 1/16 of ×× 入 力, and linearly interpolates the image of the low-resolution memory 38 and the input image in patch units. . The process of drawing input to the high resolution memory 32 is as follows.
The processing of drawing input to the low resolution memory 38 may be delayed. For example, after the drawing input processing to the high resolution memory 32 is completed, the image of the high resolution memory 32 is reduced by the reduction processing unit 36 and overwritten on the low resolution memory 38. I do. 44 is a frame memory, 46 is a monitor, and the frame memory 44 may not be provided.

FIG. 2 shows the spatial division of the stroke. For example, one stroke is composed of nine patches P1 to P9, the patch P1 is the first patch, and the patch P9 is the last patch. The drawing input processing to the high-resolution memory 32 may be delayed from the stroke input.
After designating the patches P1 to P9 for the stroke, the patch P
The total drawing range of 1 to P9 is obtained and divided into four equal parts.
0 to 53, four drawing pipelines 20 for each area
Assign to

FIG. 3 shows the processing in the divided area 50, and the processing is the same for the other divided areas. Data for specifying each patch of the patch row for the divided area 50, for example, the center position of each patch, the type of brush, and the patch size are stored in the queue 21, and the sequencer 22 collectively collects, for example, patches for one stroke. Cut out a sequence of patches to process. Then, the sequencer 22 processes one pixel at a time according to the spatial order in the divided area 50, that is, the scan order. At this stage, the input order of the patches P1 to P9 is meaningless, and the processing of the next patch is not performed after the processing of one patch is completed. After the processing of one pixel is completed, the next pixel is processed.

In FIG. 3, a region 54 is a processed region, a region 55 is an unprocessed region, and scanning is performed, for example, from the upper left to the lower of the divided region 50, and then, for example, the next column to the right by one pixel is processed. And However, the scan order itself is arbitrary. The density generating means 23 calculates the complement ki (i is a patch number) of the input density from the position of each pixel on the brush, and stores k0 as 1, for example, and stores k0 = 1 as an initial value in the accumulator 25. Is multiplied by ki and written back to the accumulator 25. When this process is repeated for the number of patches, the process for one pixel is completed. At this point, the complement value of the density is k1, k2,... Kn, and this value is written to the cache 26, and the next pixel is similarly processed. To process.

The above-described processing is performed in parallel in the four divided areas. For example, the linear interpolation processing unit 34 calculates the color signal P of the original image in the high-resolution memory 32 from the processed pixel or the processed pixel string. , And the color signal Q of the drawing input is linearly interpolated. Then, the cache 26 has a small capacity, the data sent to the cache 26 is processed by the linear interpolation processing unit 34, and the processed portion is immediately allocated to the next pixel. As described above, the total cache capacity of the four drawing pipelines is the area RA in FIG.
Since the capacity is smaller than the capacity of the M10 and a high-speed large-scale memory is not required, hardware costs are reduced.

FIG. 4 shows the operation of the embodiment. When the front end processor receives a drawing input, a drawing process, here a brush subroutine, is started. The drawing input generally involves specifying the positions of a plurality of patches and inputting a color signal of the drawing input common to each patch, and the front-end processor 30 determines that the drawing input is to be processed at a low resolution, for example, by the linear interpolation processing unit 42. To update the image in the low-resolution memory 38 and display it on the monitor 46.
Therefore, a real-time response with a low resolution image to the drawing input is performed. The processing to the low-resolution memory 38 is known, and there is no particular need to perform the processing to the low-resolution memory 38 in a parallel drawing pipeline.

For example, the input of a patch for one stroke is detected from the fact that a new patch is not designated for a predetermined time, and the front-end processor 30 spatially divides the area of one stroke into, for example, four. Are assigned to the drawing pipeline as the divided areas 50 to 53 in FIG. The queue 21 stores the data of each patch on a first-in, first-out basis (step 60), and processes one stroke at a time on a pixel-by-pixel basis according to the scan order in the divided area (step 61). After completion, the data is output to the cache 26 (step 62). Step 6
The processes of 0, 61, and 62 are performed in parallel by four drawing pipelines, and linear interpolation between the color signal P of the corresponding pixel in the high-resolution memory 32 and the color signal Q input by drawing is performed linearly from the pixels for which processing has been completed. This is performed by the interpolation processing unit 34.
Linear interpolation is as follows: Pnew = Pold × k1 · k2... Kn + Q × (1−k1 · k
2 ... kn). In parallel with the above-described processing at a high resolution, for example, processing at a low resolution according to a conventional method is performed.
Will be displayed. Then, on the high resolution side, for example, after processing of one stroke is completed, the reduced image of the high resolution memory 32 is overwritten on the low resolution memory 38. The sequencer 22 deletes the processed patch sequence from the queue 21 and proceeds to the process of the next stroke.

Considering the processing speed of drawing input,
Since four drawing pipelines 20 are provided, the calculation speed is quadrupled. Further, since the data of the accumulator 25 is used repeatedly, the operation can be performed at high speed. That is, if two processes of reading the density signal from the density generating unit 23 and multiplying by the multiplying unit 24 and writing the result to the accumulator 25 are performed in parallel, one operation can be performed at one pitch. 24 has no wasted time.

In accessing the memory, the cache 26
Is written once for each pixel in one stroke, and access to the high-resolution memory 32 is one read for each pixel in the drawing range for one stroke.
Times and one writing. For example, if the patch size is 10
Assuming that the stylus moves by a distance of about the diameter of the patch during one stroke with K pixels, the drawing range in one stroke is about 20K pixels. For this reason, each cache 26 is written 5K times, and the high-resolution memory 32 is read about 20K times and written about 20K times.
Performed K times. The capacity of each cache 26 is, for example, about 1 K pixel, which is sufficient.
6 can be used.

Considering the multiplication speed in the comparative example of FIG.
As shown in FIG. 7 for the second operation pipeline,
The multiplication for the pixel n and the reading of the data of the next pixel n + 1 from the area RAM 10 are performed in parallel (first pitch), and the multiplication result of the pixel n is written back to the area RAM 10 at the next pitch (second pitch). Become. For this reason, two pitches are required for one multiplication, and the multiplication speed is reduced to half compared with the embodiment.

In the parallel processing shown in FIG.
Reading and writing of 10K × 10 100K times are performed on 0, and the number of accesses to the memory is quadrupled as compared with the embodiment. That is, the embodiment is equivalent to using a memory and a bus that are four times as fast as those in FIG. Therefore, if we increase the drawing pipeline,
The drawing input processing can be sped up to a substantially arbitrary speed. Further, in the parallel processing of FIG. 5, an area RAM 10 having a size equal to or larger than the size of the stroke is required, but in the embodiment, only four small caches 26 need be arranged.

As a supplementary explanation of the embodiment, a register having a capacity of 16 pixels or 64 pixels is used in place of the accumulator 25, and the same processing is performed after processing the pixels corresponding to the capacity of the register for one patch and then moving to the next patch. It is. However, the register and the accumulator are expensive memories, and the accumulator 25 is the simplest and preferable.

When an extremely long stroke is input, the sequencer 22 processes the stroke by dividing it into the number of patches that can be processed (for example, 10 patches), or when the next stroke is input during the processing of one stroke. The sequencer 22 processes a new stroke after finishing the processing of the previous stroke. Alternatively, a one-stroke patch array may be divided into, for example, two, and the divided patch arrays may be regarded as one stroke for processing.

Although the processing of the plane image has been exemplified in the embodiment,
The present invention may be applied to the processing of a 3D image. In this case, a texture image or the like of the 3D image is stored in a high-resolution memory and is processed. Alternatively, the high-resolution memory 32 may be prepared for a number of planes, and processing may be performed on an image of a designated plane.

[Brief description of the drawings]

FIG. 1 is a main block diagram of an image creating apparatus according to an embodiment.

FIG. 2 is a diagram showing allocation of a patch sequence to a drawing pipeline in an embodiment.

FIG. 3 is a diagram showing processing for each pixel in the embodiment.

FIG. 4 is a flowchart illustrating an algorithm of a brush process in the embodiment.

FIG. 5 is a block diagram of a main part of a conventional image forming apparatus.

FIG. 6 is a diagram showing parallel processing in a conventional example.

FIG. 7 is a diagram showing patch processing and access to an area RAM in a drawing pipeline in a conventional example.

[Explanation of symbols]

 2,22 Sequencer 4,23 Concentration generating means 6,24 Multiplying means 8 Barrel shifter 12 Linear interpolation unit 10 Area RAM 14 File memory 16 Processing end area 18 Unprocessed area 20 Drawing pipeline 21 Queue 25 Accumulator 26 Cache 30 Front end processor 32 High-resolution memory 34, 42 Linear interpolation processing unit 36 Reduction processing unit 38 Low-resolution memory 40 Low-density density generating means 44 Frame memory 46 Monitor 50-53 Divided area 54 Processed area 55 Unprocessed area

Claims (6)

(57) [Claims] 1. An image in which an image in the process of being created is stored in a memory and displayed on a monitor, a position on the display image is designated, and drawing data is input in units of a patch composed of a plurality of pixels. A creating device configured to determine a processing range including at least one pixel from a drawing range including a plurality of patches; and a processing unit that determines the processing range for the plurality of patches until the processing in the processing range ends. An image forming apparatus, comprising: a drawing pipeline provided with processing means for repeatedly performing processing. 2. A drawing pipeline, comprising: a plurality of drawing pipelines; each drawing pipeline being spatially divided and assigned to a plurality of regions having different positions on the drawing range. 2. The image forming apparatus according to claim 1, wherein the processing is performed in parallel. 3. The processing means includes density generation means for generating drawing density data of each pixel in each patch, serially arranged, a multiplication means, and a register, wherein the multiplication means 2. The image forming apparatus according to claim 1, wherein the multiplication of the data stored in the register and the data of the density generating means is repeated for a plurality of patches on the data stored in the register. 4. The image forming apparatus according to claim 3, wherein said processing range includes one pixel, and said register is an accumulator. 5. The image creating apparatus according to claim 3, wherein a cache memory is provided on an output side of said drawing pipeline. 6. An image creation method in which an image in the course of creation is stored in a memory and displayed on a monitor, a position on the display image is designated, and drawing data is input in patch units. Is divided into a plurality of groups each including a plurality of pixels and having different positions on the drawing range, and the plurality of groups are assigned to a plurality of drawing pipelines. A processing range consisting of at least one pixel is determined from the set range, the processing for the plurality of patches is repeatedly performed on the determined processing range until the processing in the processing range is completed, and the processing range is determined and determined. An image forming method, wherein the processing of the assigned processing range is repeated to process the assigned range.