JP3042503B2 - ATM switch with statistical information latch function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an ATM switch, and more particularly to an ATM switch having a statistical information latch function.

[0002]

2. Description of the Related Art Conventionally, this type of ATM switch collects statistical information such as a data flow rate and a stagnant state flowing between a plurality of communication ports and edits the data in a time-series manner as log data, thereby causing an abnormal situation. It is usually used as a powerful means of elucidating the cause when it is done. Therefore, it is usually necessary for the software to periodically collect statistical information of the main part of each communication port at the same time and edit the collected statistical information as log data. However, data flows at a high speed inside the ATM switch, and there are many virtual channels that can be multiplexed on one line, so that the load of the statistical information collection processing for traffic monitoring becomes extremely high. Difficult to do.

An attempt to solve this problem is disclosed in Japanese Patent Application Laid-Open No. 7-2123.
No. 65 is disclosed. The purpose of this ATM switch is to provide an ATM switch that can perform statistical information collection processing for traffic monitoring with a lower processing load than before and can minimize the size of a hardware counter. . The feature is that A
It is characterized in that statistical information collecting processing for collecting statistical information for traffic monitoring from TM cells is performed by an interface unit. The interface unit is a component that manages statistical information collection processing for traffic monitoring,
It is characterized by having a hardware counter that counts the statistical information and holds the count value, and a software counter that processes and accumulates the count value by software. As a result, by performing statistical information collection processing for traffic monitoring at the interface unit,
The processing load related to the statistical information of the exchange control processor can be reduced.

[0004]

However, data flows at a high speed inside the ATM switch, and in the method in which software sequentially collects statistical information of the main part, the influence of the time difference for collecting the statistical information of each main part increases. However, there is a disadvantage that the information cannot be the same time information and is not useful as statistical information.

[0005] The above disclosed ATM switch does not describe a time difference for collecting statistical information. Statistics collected in this way are not guaranteed at the same time,
It is hard to say that it is reliable as statistical information.

An object of the present invention is to instruct each unit constituting an ATM switch to output simultaneously collected statistical information, to collect statistical information at the same time, and to collect and edit effective statistical information. To provide an ATM switch.

[0007]

An ATM switch with a statistical information latch function according to the present invention is an ATM switch including a plurality of processing circuits controlled by software and having a function of collecting and reporting statistical information. Statistical latch output means for outputting a statistical information latch signal to a processing circuit collecting statistical information, and statistical information holding means for detecting the statistical information latch signal by the processing circuit and storing the statistical information in a statistical information output buffer And a statistical information output means for receiving a statistical information output instruction from software and outputting the statistical information held in the statistical information output buffer.

[0008]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of an ATM switch according to the present invention. The ATM switch 1 of the present invention has ports 10 to 20 as communication ports. AT is stored in the nonvolatile memory ROM 3 of the ATM switch 1.
Software for controlling the entire M switch 1 is stored,
The software is deployed on the readable / writable memory MM4 and operates on the MM4. The CPU 2 executes the software and controls the ATM switch 1. The maintenance IF unit 5 has a function of displaying the status of the apparatus and receiving an operation instruction from a manual operation switch or a maintenance terminal. The switch processing circuit 40 performs a switching operation of outputting the received ATM cell to the transmission port. Packet conversion processing circuit 410
Has a function of disassembling arbitrary-length data into a plurality of cells and transmitting the received cells, and assembling the plurality of received cells into arbitrary-length data. The software performs call control information and the like with a terminal connected to the port 10 or the port 20. Used to send and receive data. Ports 10 to 20 are circuit signal processing circuits 130, 2 which physically interface with the transmission line.
30; frame processing circuits 120 and 220 for generating and disassembling a data frame and generating and checking a header error detection code (HEC); and header processing circuits 110 and 210 for analyzing a cell header and controlling switching.
The header processing circuit 310 controls the switching by analyzing the cell header of the cell transmitted from the packet conversion processing circuit 410. The statistical latch output means 50 outputs a statistical information latch signal to a plurality of processing circuits having a function of collecting and reporting statistical information at the same time according to instructions from software.

In this embodiment, the processing circuits having the functions of collecting and reporting statistical information include the header processing circuits 110 and 21.
0, 310, frame processing circuits 120, 220, signal processing circuits 130, 230, and packet conversion processing circuit 4.
10 and a switch processing circuit 40, and a statistical latch signal line from the statistical latch output means 50 is connected to each processing circuit. These processing circuits constantly update statistical information. Usually, these processing circuits are often LSIs.

FIG. 2 is a configuration diagram of a header processing circuit 110 which is one of processing circuits having a function of collecting and reporting statistical information in the ATM switch of FIG. Header processing circuit 110
Receives the ATM cell from the frame processing circuit 120, analyzes the header of the ATM cell, and receives and executes a command from the CPU 2 and a header analysis unit that transfers the ATM cell with the switching information to the switch processing circuit 40. It comprises a command processing unit 112, a statistical processing unit 113 for creating statistical information and reporting it to software, and a statistical information output buffer 124 for temporarily storing statistical information.

FIG. 3 is a block diagram of a frame processing circuit 120 which is one of processing circuits having a function of collecting and reporting statistical information in the ATM switch of FIG. Frame processing circuit 1
Reference numeral 20 denotes a frame generation / decomposition unit 121 for decomposing a received data frame to extract an ATM cell, inspecting an HEC, and adding a HEC to an ATM cell to be transmitted to generate a data frame; A command processing unit 122 for receiving and executing the statistical information, a statistical processing unit 123 for generating statistical information and reporting the generated statistical information to software, and a statistical information output buffer 124 for temporarily storing statistical information.

FIG. 4 is a configuration diagram of a signal processing circuit 130 which is one of processing circuits having a function of collecting and reporting statistical information in the ATM switch of FIG. The signal processing circuit 130
The signal conversion unit 131 converts the transmission data received from the frame processing circuit 120 into a signal on a communication line, converts the received data signal, and passes the data signal to the frame processing circuit 120.
And a command processing unit 132 that receives and executes a command from the CPU 2, a statistical processing unit 133 that creates statistical information and reports it to software, and a statistical information output buffer 134 that temporarily stores statistical information.

FIG. 5 is a configuration diagram of a packet conversion signal processing circuit 410 which is one of processing circuits having a function of collecting and reporting statistical information in the ATM switch of FIG. The packet conversion signal processing circuit 410 converts a data packet of an arbitrary length stored in the buffer memory 415 by software into a plurality of A packets.
The data is converted to a TM cell and sent to the header processing circuit 130. The plurality of ATM cells received from the header processing circuit 130 are assembled into a data packet of an arbitrary length to form a buffer memory 4.
15, a packet generation / decomposition unit 411,
Command processing unit 41 that accepts and executes commands from
2, a statistical processing unit 413 that creates and reports statistical information to the software, and a statistical information output buffer 414 that temporarily stores the statistical information. Operating parameters and the like are stored.

FIG. 6 is a configuration diagram of a switch processing circuit 40 which is one of processing circuits having a function of collecting and reporting statistical information in the ATM switch of FIG. Switch processing circuit 40
Is the AT received from the header processing circuits 310 to 330
A switch section 41 for switching an M cell to an appropriate port according to the switching information and outputting the selected port;
Command processing unit 42 that accepts and executes commands from
And a statistical processing unit 43 that creates statistical information and reports it to the software, and a statistical information output buffer 44 that temporarily stores the statistical information.

The overall flow of collecting statistical information will be described with reference to FIG. When the software collects statistics,
First, the statistical latch output means 50 is instructed to output a statistical latch signal. When the latch output is instructed by software, the statistical latch output means 50 outputs a statistical latch signal to all processing circuits having a function of collecting and reporting statistical information.

Header processing circuit 1 receiving statistical latch signal
10, 210, 310 and frame processing circuits 120, 2
20, the signal processing circuits 130 and 230, the packet conversion processing circuit 410, and the statistical processing unit of the switch processing circuit 40 respectively output the statistical information at that time to a statistical information output buffer and accumulate the statistical information. The software sequentially issues a statistical information collection instruction to each of the processing circuits described above, reads the statistical information of each processing circuit, and edits the statistical information as statistical information of the entire ATM switch. Although there is a time difference in the statistical information collection instruction from the software to each processing circuit, each processing circuit outputs the statistical information at the time of receiving the statistical latch signal output simultaneously to all the processing circuits. This means that the statistical information of each processing circuit at the same time has been collected.

The operation of the processing circuit having the functions of collecting and reporting statistical information will be described with reference to FIG. The statistical latch signal output from the statistical latch output means 50 is processed by the statistical processing unit 1
23 detects. The statistical processing unit 123 that has detected the statistical latch signal outputs the statistical information at that time to the statistical information output buffer 124 and accumulates it. The statistical processing unit 123 continuously updates the statistical information internally. Thereafter, when a statistical information collection instruction is issued from the software, the statistical processing unit 123 outputs the information stored in the statistical information output buffer 124 and responds to the software.

Similarly, other processing circuits having a function of collecting and reporting statistical information similarly detect a statistical latch signal, accumulate the statistical information at that time in a statistical information output buffer, and furthermore, generate a statistical information in response to a statistical information collection instruction. It has the function of reporting from the information output buffer.

[0019]

As described above, the software instructs the statistical latch output means 50 to output the statistical latch, and simultaneously instructs all the processing circuits having the function of collecting and reporting the statistical information to accumulate the statistical information. Thus, even if there is a time difference in the statistical information collection instruction to each processing circuit, statistical information at the same time can be collected. Therefore, ATM can be used at high speed
It is possible to collect and edit effective statistical information even in an ATM switch through which cells flow.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an ATM switch with a statistical information latch function of the present invention.

FIG. 2 is a configuration diagram of a header processing circuit having a function of collecting and reporting statistical information.

FIG. 3 is a configuration diagram of a frame processing circuit having a function of collecting and reporting statistical information.

FIG. 4 is a configuration diagram of a signal processing circuit having a function of collecting and reporting statistical information.

FIG. 5 is a configuration diagram of a packet conversion processing circuit having a function of collecting and reporting statistical information.

FIG. 6 is a configuration diagram of a switch processing circuit having a function of collecting and reporting statistical information.

[Explanation of symbols]

1 ATM switch 2 CPU 3 Non-volatile memory (ROM) 4 Read / write memory (MM) 5 Maintenance IF unit 10, 20 port 40 Switch processing circuit 41 Switch processing unit 42, 112, 122, 132, 412 Command processing unit 43, 113, 123, 133, 413 Statistical processing unit 44, 114, 124, 134, 414 Statistical information buffer 50 Statistical latch output unit 110, 210, 310 Header processing circuit 111 Header analysis unit 120, 220 Frame processing circuit 121 Frame generation / decomposition unit 130, 230 signal processing circuit 131 signal conversion section 410 packet conversion processing circuit 411 packet generation / decomposition section 415 buffer memory 416 control memory

Claims (10)

(57) [Claims] 1. An ATM switch having a function of processing statistical information, wherein each unit constituting the ATM switch and constantly collecting statistical information is supplied to a processing unit of each unit by an instruction from software. A statistical latch output unit that outputs a statistical information latch signal; a processing unit of each unit that detects a statistical information latch signal and stores statistical information in a statistical information output buffer; and a processing unit of each unit. And a statistical information output means for receiving a statistical information output instruction from the software and outputting the statistical information held in the statistical information output buffer. 2. A switch processing circuit for processing exchange of ATM cells, a header processing circuit for analyzing cell headers of ATM cells and controlling switching, encoding / decoding of data frames and header error detection. A frame processing circuit that performs code generation inspection; a signal processing circuit that converts transmission data received from the frame processing circuit into a communication signal, converts a received communication signal into reception data, and passes it to the frame processing circuit; Is divided into a plurality of ATM cells and transmitted,
Assemble the received ATM cells into data of arbitrary length,
2. The ATM switch with a statistical information latch function according to claim 1, further comprising: a packet conversion processing circuit that performs transmission and reception with a terminal. 3. A switch unit for switching an ATM cell received from a header processing circuit to a communication line according to switching information; a command processing unit for receiving a command from a CPU and executing the command; 3. The ATM switch with a statistical information latch function according to claim 1, further comprising: a statistical processing unit that generates statistical information and reports the statistical information to software; and a statistical information output buffer that temporarily stores the statistical information. 4. A header analysis section, wherein the header processing circuit receives the received ATM cell from the frame processing circuit, analyzes the header of the ATM cell, adds switching information, and passes the information to the switch processing circuit, and a command from the CPU. The statistical information latch function according to claim 1 or 2, further comprising: a command processing unit that receives the command and executes a command; a statistical processing unit that creates statistical information and reports the statistical information to software; and a statistical information output buffer that temporarily stores the statistical information. ATM switch. 5. The ATM processing unit according to claim 1, wherein said frame processing circuit decomposes the received data frame to extract an ATM cell, checks a header error detection code, and transmits the ATM cell.
A frame generation / decomposition unit that generates a data frame by adding a header error detection code to a cell; a command processing unit that receives a command from the CPU and executes the command; and a statistical process that generates statistical information and reports the information to software. 3. The ATM switch according to claim 1, further comprising a statistical information output buffer for temporarily storing statistical information. 6. A signal conversion unit, wherein the signal processing circuit converts transmission data received from the frame processing circuit into a signal on a communication line, converts a received signal into data, and passes the data to the frame processing circuit; 3. The statistical information according to claim 1, further comprising: a command processing unit that receives a command from the server and executes the command; a statistical processing unit that creates statistical information and reports the generated statistical information to software; and a statistical information output buffer that temporarily stores the statistical information. ATM switch with latch function. 7. The packet conversion processing circuit converts a data packet of an arbitrary length stored in the buffer memory and the software into a plurality of ATM cells by the buffer memory, sends the ATM packet to the header processing circuit, and receives the data packet from the header processing circuit. Multiple ATMs
A packet generation and disassembly unit that assembles into data packets of an arbitrary length from cells and stores them in a buffer memory, a command processing unit that receives commands from the CPU and executes the commands, and a statistical processing unit that creates statistical information and reports it to software 3. The ATM switch according to claim 1, further comprising: a statistical information output buffer for temporarily storing statistical information. 8. The ATM switch according to claim 1, wherein the processing unit of each unit is configured as one LSI for each unit. 9. The ATM switch according to claim 1, wherein a processing unit of each unit is included in an LSI of each unit. 10. The AT with a statistical information latch function according to claim 1, wherein the processing units of the respective units are collectively configured as one LSI.
M switch.