JP3037213B2 - Distortion compensation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a feedback type distortion compensating method, and relates to a method for generating a baseband signal by demodulating a modulated wave once and applying a feedback to a transmission baseband signal to obtain a non-linearity of an amplifier. The present invention relates to a method for improving the generated nonlinear distortion.

[0002]

2. Description of the Related Art When a quadrature modulated wave is amplified to a required transmission power, a negative feedback type compensation system is generally used to compensate for non-linear distortion caused by non-linearity of the amplifier. For example, the method in which a high-frequency signal is directly returned to the input of a power amplifier and a negative feedback is applied thereto has a problem that a phase delay occurs in the returned high-frequency signal itself and it is difficult to oscillate or compensate over a wide band. A distortion compensation circuit as shown is used.

[0003] This circuit is called a Cartesian loop linearizer. This Cartesian loop linearizer is a type of modulation feedback in which a quadrature-modulated high-frequency signal is once demodulated and converted into a baseband signal, and a feedback is applied. When performing quadrature modulation,
Decompose the demodulated data into an in-phase signal component and a quadrature signal component,
This is a method of feeding it back to the input of the quadrature modulator.

Hereinafter, description will be made with reference to FIG. In FIG. 4, 1 is an input terminal to which a bit sequence of transmission data is input, 2 is an output terminal to which a modulated wave is transmitted, and 3 is a signal terminal to which a signal synchronized with a slot of the transmission data is input. Reference numeral 4 denotes a function of generating a symbol signal from a bit sequence of transmission data, in-phase data I101, quadrature data Q1
02 is a converter composed of a filter function for shaping the waveform of a symbol signal in order to generate and output 02.

[0005] Reference numeral 5 denotes a compensation circuit called a Cartesian loop for compensating for non-linear distortion generated by a power amplifier to be described later, and is configured as follows. 19 is an oscillator for generating a carrier wave. 11 is a difference signal I111, a difference signal Q11
2 is a quadrature modulator that modulates the carrier from the oscillator 19. Reference numeral 12 denotes a preamplifier having a means for controlling the loop gain to be constant, and reference numeral 13 denotes a power amplifier for amplifying a modulated wave until a required transmission output is output to the output terminal 2.

Reference numeral 14 denotes a coupler for extracting a part of the modulated wave output from the power amplifier 13, and reference numeral 15 denotes an attenuator for attenuating the modulated wave extracted by the coupler 14. 16 is
This is a quadrature demodulator for demodulating a modulated wave attenuated to an appropriate level by the attenuator 15. The demodulated signal I131 and the demodulated signal Q13
Generate 2.

[0007] The phase controller 18 outputs a comparison difference signal I12.
1. It has a function of controlling the carrier phase of the output from the transmitter 19 by the comparison difference signal Q122. Reference numeral 17 denotes demodulated data I131 and demodulated data signal Q which are outputs of the quadrature demodulator 16.
132, a phase comparison function of comparing the signal phases of the in-phase data I101 and the quadrature data Q102 output from the converter 4 and outputting the respective comparison difference signals I121 and Q122, and the synchronization signal from the signal terminal 3. This is a phase comparator having a function of holding the immediately preceding comparison difference signal.

Reference numeral 20 denotes a switch for opening and closing the demodulated data I131 and the demodulated data Q132 in response to a synchronization signal from the signal terminal 3. Reference numeral 10 denotes a demodulated data I131 and a demodulated data Q132 output from the quadrature demodulator 18 and a converter. This is a subtractor for subtracting the four outputs of the in-phase data I101 and the quadrature data Q102. The loop is controlled so that the difference signals I111 and Q112, which are the outputs of the subtracters, are minimized.

Next, the operation will be described. The modulation scheme may be any digital modulation scheme that can perform quadrature modulation. Here, the π / 4 shift Q
A description will be given using PSK as an example.

FIG. 5 shows an example of the signal format of the transmission data input to the input terminal 1. In the figure, P is a preamble part for a linearizer, and D is a data part. The serial bit sequence of the transmission data from the input terminal 1 is input to the converter 4. The converter 4 generates 2-bit parallel data from the input serial bit sequence by serial / parallel conversion for every 2 bits, and converts the data into in-phase component and quadrature component symbol data according to the differential encoding rule.

Each symbol data of the in-phase component and the quadrature component is filtered by a filter having a certain roll-off rate α (for example, α
= 0.5) and then in-phase data I10
1. Output to the compensation circuit 5 as orthogonal data Q102.

Next, the operation of the compensation circuit 5 will be described in detail. The in-phase data I 101 and the quadrature data Q 102 with the band limited are input to the subtractor and the phase comparator 17.
The subtracter 10 subtracts the demodulated data I131 and the demodulated data Q132 adjusted to the level corresponding to the negative feedback amount from the in-phase data I101 and the quadrature data 102, and outputs the subtraction result to the quadrature modulator 11. The quadrature modulator 11 quadrature-modulates the carrier from the oscillator 19 with a very weak signal as a subtraction result, and outputs the result to the preamplifier 12.

The preamplifier 12 is an amplifier having a function of controlling the amplifier gain so that the loop gain is kept constant by a synchronization signal from the signal terminal 3. The function of controlling the loop gain to be constant will be described later.

The output of the modulated wave from the preamplifier 12 is amplified to a required transmission power by a power amplifier 13 and output to an output terminal 2.
Output to A part of the modulated wave output from the power amplifier 13 is taken out by the coupler 14 and attenuated to an appropriate level by the attenuator 15, and then the modulated wave is demodulated by the quadrature demodulator 18.
A signal separated into demodulated data I131 and demodulated data Q132 is generated.

After the generated demodulated data I131 and Q132 are adjusted to an appropriate level corresponding to the required amount of negative feedback, they are input to the subtractor 10 via the switch 20, and the in-phase data 101 and the quadrature data are output. It is subtracted from the data 102. Thus, a negative feedback loop is formed.

In order for the Cartesian loop linearizer to operate stably, the demodulated data I 101 and the quadrature data Q 102 input to the subtracter 10 are
131, control to precisely match the phase of the demodulated data Q132 is very important.

Next, the phase adjustment will be described in detail.
As shown in FIG. 5A, the bit sequence of the transmission data is
It has a slot configuration, and a preamble bit P for linearizer dedicated to phase adjustment is prepared in advance at the beginning of each slot. A case where the signal sequence after the preamble bit P is subjected to symbol signal processing by the converter 4 becomes, for example, all “1” in the in-phase data I101 and all “0” in the quadrature data Q102 will be described.

A signal synchronized with the linearizer preamble time is input to the signal terminal 3 for each slot of transmission data (FIG. 5B). The phase detection is performed for each linearizer preamble transmission time of the in-phase data I101.
The switch 20 is opened by the synchronizing signal (FIG. 5B) input to the signal terminal 3 to open the loop, and then the demodulated data I131 for the in-phase data I101
Is detected from the time difference between the zero cross points of the mutual data.

The detected comparison difference signal I121 controls the phase controller 18 to change the phase of the demodulated data I131, is compared with the transmission data I101 again, and outputs the comparison difference signal I121. With the above-mentioned round operation,
The phase control operation is continuously performed during the time when the linearizer preamble is being transmitted.

At the time of the phase detection operation, it is necessary to keep the loop loop gain constant in order to temporarily open the loop. This is realized by controlling the gain of the preamplifier 12 by the synchronization signal at the signal terminal 3. doing.

When transmitting the transmission data D (FIG. 5A), the comparison difference signal I121 of the phase comparator 17 is held as a synchronization signal from the signal terminal 3. Thus, the demodulated data I13
By fixing the phase of 1 to a correct value and closing the loop, the correct phase state is maintained in the slot, and a modulated wave with improved distortion is output.

As described above, the above control of the linearizer preamble P and the data D in the transmission data is repeated by the synchronization signal from the signal terminal 3, thereby achieving a stable distortion improvement characteristic.

[0023]

In the conventional Cartesian loop linearizer, the control for once opening the loop and the phase control are performed in the process of matching the mutual phases of the transmission data and the demodulated data using the preamble dedicated to the linearizer. Since it is necessary to control the demodulation data to close the loop when transmitting the transmission data, and to perform gain control to keep the loop gain change by opening / closing the loop, the circuit configuration and control method are very complicated. And has an unstable element.

Further, a linearizer preamble part dedicated to phase matching used for matching the mutual phases of transmission data and demodulation data is inserted into a data slot to be transmitted having a predetermined number of bits. There is a problem that the number of available effective bits decreases and the throughput of transmission data decreases.

A first object of the present invention is to detect a phase between a linearizer preamble signal dedicated to phase detection of transmission data and a linearizer preamble signal obtained by demodulating a modulated wave. Then, once the loop is opened, the phase detection operation is performed, and at the timing of transmitting the transmission data, the immediately preceding phase detection result is frozen to close the loop, and the loop gain that changes by opening and closing the loop is controlled. It is an object of the present invention to provide a distortion compensating circuit which simplifies a very complicated control method such as controlling to be constant.

The second object is to perform phase control continuously by sequentially detecting the time difference between the zero crossing of both linearizer preamble signals for each bit of the preamble signal, so that the preamble signal has noise. An object of the present invention is to provide a distortion compensating circuit which improves a point that an error occurs in phase detection when a superposition occurs and a malfunction is likely to occur.

A third object of the present invention is to provide a distortion compensating circuit for improving a decrease in throughput of transmission data to be transmitted because a preamble signal for a linearizer dedicated to phase detection is set in transmission data. It is in.

[0028]

The distortion compensating circuit of the present invention takes out a part of the modulated wave including the nonlinear distortion of the power amplifier from the output of the power amplifier, attenuates it to an appropriate level, and demodulates it. A quadrature demodulator that outputs demodulated data separated and generated into in-phase and quadrature components, a subtractor that subtracts transmission data of the in-phase and quadrature components and the in-phase and quadrature demodulated data to extract a difference signal, and a transmission carrier that uses the difference signal. A quadrature modulator that quadrature modulates, a negative feedback circuit configured by a power amplifier that amplifies the quadrature modulated wave, a phase controller that controls a carrier phase supplied to the quadrature demodulator, and the transmission data. The phase difference of the demodulated data is detected, and if the detected phase detection value cannot satisfy a certain threshold, the detected value is invalidated and discarded. Assuming that the value is valid, a phase control value having a certain step width is output once, the pre-stored initial phase preset value and the phase control value are added and subtracted, and the stored preset value is updated and the demodulation is performed. A phase detector that outputs a phase difference signal to the phase controller in order to change the phase of the data.

When the amplifier starts operating, the distortion compensation circuit of the present invention controls the phase of the demodulated signal to a predetermined value so that the loop operates stably from the beginning, and the power supply voltage and the temperature change cause the loop to operate stably. Even if the distortion characteristic changes, the step follow-up control using the preamble signal of several bits indicating the start of the transmission data eliminates the need to prepare a preamble signal dedicated to the linearizer. The throughput can be improved, and the circuit configuration can be simplified and the distortion compensation operation can be stabilized.

[0030]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a distortion compensating circuit according to the present invention, FIG. 2 is a block diagram showing a phase detector, and FIG. 3 is a diagram showing waveforms of respective parts of the block. . In FIG. 1, the description of the blocks having the same numbers as the conventional ones is omitted. 6 is a distortion compensation circuit of the present invention. 21 is a phase detector, which outputs a phase difference signal I141,
The phase difference signal Q142 is output. A preamplifier 22 amplifies the quadrature modulated signal to a required level. The configuration of the phase detector 21 will be described with reference to FIG.

The phase detector 21 transmits the transmission data I101,
Transmission data Q102, demodulated signal I131, demodulated signal Q1
A detection unit 30 that detects a phase difference between the two by using the input 32
And a threshold detection unit 31 that outputs a phase control signal of a certain step width once, and a demodulation signal phase is determined in advance only when the phase difference from the detection unit 30 is within a preset range. A ROM 33 for holding an initial phase offset value so as to obtain a phase output, and a threshold detector 3
One output updates the initial phase offset value, and outputs the updated output to the phase difference signal I 141 and the phase difference signal Q.
RAM section 32 which outputs to phase controller 18 as 142
And a control unit 34 for controlling the detection unit 30 and the RAM unit 32 with a synchronization signal from the signal terminal 3.

Next, the operation will be described. Here, the method of applying negative feedback to the transmission data with the demodulated signal is the same as in the conventional example, and is omitted, and the main phase detection method of the present invention will be described in detail.

Regarding phase detection, a method of detecting the phase between the in-phase I components will be described here. Since the orthogonal Q components are similarly controlled, a description thereof will be omitted. From the signal terminal 3, a synchronization signal synchronized with the transmission data transmission timing is input.
When a modulated wave is transmitted by the operation of the amplifier, the initial offset value of the storage unit 33 is output from the RAM unit 32 to the phase controller 18 as the phase difference signal I141 by the first synchronization signal, and the output of the quadrature demodulator 16 is output. By controlling the signal phase of the demodulated signal I131 to be the same as that of the transmission data I101, it is possible to transmit a modulated wave having a small distortion component immediately after transmission. However, since the signal phase of the demodulated signal I131 shifts due to a change in the power supply voltage or the temperature, and the loop becomes unstable, the follow-up control is required. In the tracking control according to the present invention, as shown in FIG.
This is performed using a preamble of several bits indicating the start position of data as shown in FIG. That is, FIG.
, A detection window b synchronized with the preamble position of the transmission data is set. The detection window has a time tp at which a zero cross of the signal can be detected, and several symbol times are sufficient. In the phase difference detection, the demodulated signal I1 for the transmission data I101 is detected within the time when the detection window is open.
The leading and lagging phases of the signal 31 are detected based on the time difference between the signals that first cross zero, and are sent to the threshold value detecting section 31. Phase detection is performed only once in one transmission data slot. In the threshold value detector 31, for example, the phase difference is 5 °
If the detected phase difference is within 20 ° from
Output a step, for example, a 1 ° phase control signal. The minimum phase difference of, for example, 5 ° sets a dead zone when the phase control converges, and the maximum phase difference of, for example, 20 °.
° is set to prevent malfunctions such as when noise is superimposed on a signal. The validity of the phase difference is determined for each transmission data slot, and a phase control signal for each step is supplied to the RAM unit 32 each time. RAM section 32
First stores the offset value in the storage unit 33, and when the amplifier is activated and transmission is started, the offset value stored by the control signal 1 (FIG. 3B) from the control unit 34 is stored in the phase difference. Output to the phase control unit 18 as a signal I141,
By changing the phase of the local signal supplied to the quadrature demodulator 16, the phase of the demodulated signal I131 from the quadrature demodulator 16 is controlled. Demodulated signal I1 due to power supply voltage or temperature change
When the phase of 31 changes, the phase difference is detected by the detection unit 30 as described above, and after the validity of the detected phase difference is confirmed by the threshold value detection unit 31, one step, for example, 1 ° phase control is executed. Output to the RAM unit 32. RAM3
2 updates the offset value by one step and outputs it to the phase controller 18 to control the phase of the demodulated signal I131. As described above, by repeatedly performing step control for each slot of transmission data until the minimum phase difference becomes, for example, 5 ° or less as the phase control cycle, stable Cartesian loop linearizer control is realized while the loop is always kept closed. be able to.

In this example, a preamble signal of several bits indicating the start of transmission data is used for phase detection. However, it is not necessary to adhere to this, and the zero-crossing of both signals can be performed within the time of the detection window for phase detection. Since it is sufficient that the point can be recognized, similar detection may be performed at an arbitrary position in the transmission data.

[0036]

As described above, according to the present invention, there is no need to provide a dedicated linearizer preamble signal for phase detection in transmission data, so that the throughput of transmission data can be greatly improved. That is, when the amplifier operates and starts transmission, means for presetting the demodulated signal phase to a preset value, detecting the phase difference between the transmitted data and the demodulated signal, and setting a detection window on the transmitted data for several symbol times. This is because it can be realized by performing, for each slot, a detecting means for measuring a mutual time difference in which both signals are zero-crossed for the first time within the time of the detection window.

The present invention has an effect that the loop operates very stably. It has a threshold in the phase detector to determine the validity of the detected phase difference,
If an unexpected phase difference is detected due to superimposition of noise on the signal, a means for invalidating the phase difference detected in the slot and not performing phase control, and a means for performing the phase control even if the validity is confirmed. This is because it can be realized by using a means for limiting the phase control step size that can be performed at a time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a distortion compensation circuit according to the present invention.

FIG. 2 is a block diagram showing a phase detector.

FIG. 3 is a diagram showing waveforms of respective parts of a block.

FIG. 4 is a block diagram showing a conventional circuit.

FIG. 5 is a diagram showing waveforms at various parts of a conventional circuit.

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 output terminal 3 signal terminal 4 converter 5, 6 distortion compensating circuit 10 subtractor 11 quadrature modulator 12, 22 preamplifier 13 power amplifier 14 coupler 15 attenuator 16 quadrature demodulator 17 phase comparator 18 Phase controller 19 Oscillator 20 Switch 21 Phase detector 30 Detection unit 31 Threshold detection unit 32 RAM unit 33 ROM unit 34 Control unit 101 In-phase signal I 102 Quadrature signal Q 111 Difference signal I 112 Difference signal Q 121, 141 Phase difference signal I 122, 142 Phase difference signal Q 131 Demodulated signal I 132 Demodulated signal Q

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-78967 (JP, A) JP-A-9-116474 (JP, A) JP-A-6-252962 (JP, A) JP-A-4- 4614 (JP, A) JP-A-6-30059 (JP, A) JP-A-6-237272 (JP, A) Tomita Kakura, "How to control phase rotation in a Cartesian loop", IEICE Autumn Meeting 1994 Proceedings B-319 (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/20 H04L 27/36

Claims (6)

(57) [Claims] 1. A part of a modulated wave including nonlinear distortion of a power amplifier is taken out from an output of the power amplifier, attenuated to an appropriate level, and demodulated to output demodulated data separated and generated into in-phase and quadrature components. A quadrature demodulator, a subtractor that subtracts in-phase and quadrature component transmission data and the in-phase and quadrature demodulation data to extract a difference signal, a quadrature modulator that orthogonally modulates a transmission carrier with the difference signal, and the quadrature modulation. A negative feedback circuit configured by a power amplifier that amplifies a wave, a phase controller that controls a carrier wave phase supplied to the quadrature demodulator, and detects a phase difference between the transmission data and the demodulated data. If the detected phase difference is not within the range between the minimum phase difference that sets the dead zone when phase control converges and the maximum phase difference that prevents malfunction, the detected phase difference is invalid. If the detected phase difference is within the range between the minimum phase difference and the maximum phase difference, the detected phase difference is made valid, and a phase control value having a certain step width is output once and stored in advance. Adding and subtracting the initial phase preset value and the phase control value that have been stored, updating the stored preset value, and outputting a phase difference signal to the phase controller to vary the phase of the demodulated data. A distortion compensation circuit, comprising: a detector; 2. A method for detecting a phase difference between the transmission data and the demodulated data by opening a detection window synchronized with a position of the preamble of transmission data including a preamble of several bits and performing the detection within the time of the detection window. The distortion compensation circuit according to claim 1, wherein: 3. The method according to claim 1, wherein the minimum phase difference is 5 ° and the maximum phase difference is 20 °.
3. The distortion compensation circuit according to 1. 4. A part of a modulated wave including non-linear distortion of a power amplifier is taken out from an output of the power amplifier, attenuated to an appropriate level, and demodulated to output demodulated data separated and generated into in-phase and quadrature components. A quadrature demodulator, a subtractor that subtracts in-phase and quadrature component transmission data and the in-phase and quadrature demodulation data to extract a difference signal, a quadrature modulator that orthogonally modulates a transmission carrier with the difference signal, and the quadrature modulation. A negative feedback circuit configured by a power amplifier that amplifies a wave; a phase controller that controls a carrier wave phase supplied to the quadrature demodulator; and a detection unit that detects a phase difference between the transmission data and the demodulated data. When the phase detection value detected by the detection unit cannot satisfy a certain threshold, the detection value is invalidated and discarded, and only when the threshold is satisfied, the detection value is set to valid. A threshold value detection unit that outputs a phase control signal having a certain step width once, a ROM unit that stores an initial phase preset value of the demodulated signal, and an initial phase preset value from the ROM unit. By performing addition and subtraction with the phase control value of the threshold value detection unit output, and updating the stored preset value, to vary the phase of the demodulated data,
A phase control unit that outputs a phase difference signal to a phase controller that controls a carrier phase supplied to the demodulator, and a control unit that controls the RAM unit and the detection unit with an external synchronization signal. A distortion compensation circuit, comprising: a detector; 5. The distortion compensation circuit according to claim 4, wherein said transmission data includes a preamble signal of several bits indicating a start of the transmission data. 6. The distortion compensation circuit according to claim 4, further comprising a preamplifier between the quadrature modulator and the power amplifier for controlling a loop gain to be constant.