JP3036486B2 - Failure analysis method for integrated circuit and failed integrated circuit assembly - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit failure analysis method and a failed integrated circuit assembly.

[0002]

2. Description of the Related Art In a conventional failure analysis technique for an integrated circuit such as an LSI, a suspicious fault spot narrowed down mainly by a tester or the like from the surface of an LSI chip is measured by an EB tester, a probe by a prober, and an emission. The failure location is identified by microscopic observation.

[0003]

In the prior art, it is becoming difficult to specify a failure location. Therefore, failure analysis from the back of the chip (emission, O
It is becoming necessary to perform a combination of BIC, OBIRCH analysis, and other analysis for detecting light emission. The reason for this is that, due to the multi-layered LSI, the analysis of only the chip surface hinders the upper layer wiring, so that the suspected fault location cannot be measured and observed.

A second problem of the prior art is that it is difficult to perform a failure analysis of an LSI once assembled in a package by combining an analysis from the back surface of the chip with an analysis from the front surface. In particular, it is difficult to perform backside analysis.

[0005] The reason is that when the LSI is mounted face-up, the analysis can be performed from the front surface only by opening the package, but the back surface analysis cannot be performed. In order to perform backside analysis, it is necessary to remove the chip from the package, but if it is removed from the package,
Power and signals required for analysis cannot be applied to the chip. In addition, when the LSI is mounted face down, it is difficult to polish the back surface of the chip without damaging the leads. At this time, if the leads are cut, analysis may not be performed. In addition, in order to perform analysis from the surface, it is necessary to reassemble face-up into another package.

SUMMARY OF THE INVENTION An object of the present invention is to provide a failure analysis method capable of easily performing backside analysis and analysis from the front side as needed, particularly for a faulty LSI once assembled in a package.

[0007]

According to the failure analysis method of the present invention, after removing an LSI from a package, a pattern necessary for applying a power supply, a ground, and a signal required for the analysis of the LSI is formed. Using a TAB tape provided with a pad through the through-hole, the pad on the chip side and the lead on the tape side are connected to form TCP.

A socket is formed for applying a signal to the TCP, and a pogo pin attached to the socket is brought into contact with a TCP pad.

[0009] When performing a back surface analysis, the chip is mounted face down to a socket to apply a power supply voltage and a signal. When an EB tester or the like is analyzed from the front side, the chip is mounted face up to the socket. Attach,
Analysis is performed by applying a power supply voltage or signal.

[0010] The LSI assembled in the package is removed, reassembled in TCP, mounted in a socket, and a power supply voltage and a signal required for back surface analysis can be applied to the LSI. By changing the value, it is possible to easily use the back side analysis and the front side analysis.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view when a faulty LSI is assembled into a TCP of the present invention, FIG. 2 is a cross-sectional view when a TCP is mounted on a socket when analyzing a back surface, and FIG. It is sectional drawing at the time of attaching to.

In FIG. 1, an LSI chip 1 is a faulty LSI chip obtained by opening the integrated circuit package (QFP, PGA, etc.) 16 shown in FIG. 4, and its back surface is mirror-polished so that back surface analysis can be performed. ing. TAB
On the (Tape Automated Bonding) tape 3, a power supply wiring pattern, a ground (ground) wiring pattern, and a signal wiring pattern necessary for analysis of the LSI chip 1 are formed. Further, pads 5 connected to both sides of the TAB tape 3 via through-holes 6 are provided. The ILB pad 2 and the tip of the lead 4 on the TAB tape 3 are joined by positioning and heating the lead 4 and the ILB pad 2 while applying pressure with a bonding tool.

In the assembly having such a configuration, the LSI
Backside analysis of chip 1 (emission observation, OBIC method,
In the case of performing the OBIRCH method or the like, first, as shown in FIG. 2, the pads 5 of the TAB tape 3 and the pogo pins (terminals which can be moved up and down by spring pressure) 8 are brought into contact with the LSI chip 1 face down. Then, place it on the socket 7 and hold it down with the cover 9.

On the other hand, an analysis (E
B tester, prober using a prober, etc.), as shown in FIG.
The pad 5 of the AB tape 3 is placed on the socket 7 so that the pad 5 and the pogo pin 8 are in contact with each other.

Next, the above-described embodiment will be described more specifically.

If the package 16 is PGA,
The PGA has a structure in which an LSI chip 1 is mounted face down with TAB and covered with a cap 12 made of AlN (aluminum nitride) to perform die bonding and sealing. For the die bonding material, for example, Ag (silver)
Epoxy adhesive is used. The LSI chip 1 is removed as follows. The Kovar ring 13 around the cap 12 is cut with a mini-turter or the like. Place the cap on the hot plate heated to 350 ° C. for 10 minutes, lift the substrate, and place the LSI chip 1 in the cap 12.
Remove from The TAB lead 14 is cut and the LSI chip 1 is taken out. After the Ag epoxy adhesive remaining on the back surface of the LSI chip 1 is removed, the back surface is polished using an abrasive. The LSI chip 1 is immersed in fuming nitric acid at room temperature to remove the mold. The lead remaining on the ILB pad 2 is removed to make the LSI chip 1 alone.

The material of each wiring pattern of the TAB tape 3 is formed by processing a copper foil and plating it with gold. The through hole 6 is formed by copper plating. LS
The bonding between the I chip 1 and the TAB tape 3 is performed by placing the LSI chip 1 on a heated bonding stage,
The position of the pad 2 and the tip of the lead 4 of the TAB tape 3 are aligned, and an ultrasonic wave and a load are applied to the bonding tool to join the lead 4 and the ILB pad 2 together.

[0019]

The effect of the present invention is that the analysis from the front side and the analysis from the back side of the faulty LSI chip can be performed in the same package, so that the analysis from the front side and the analysis from the back side can be easily used properly. It is to become.

The reason is that the faulty LSI chip is removed from the package and reassembled into a TCP having the pads 5 on both sides, so that the power supply voltage and the power supply required for the analysis can be obtained regardless of whether the front side or the back side of the LSI chip is on the upper side. This is because a signal can be applied from the pad 5.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view when a failed LSI is assembled into a TCP by the assembling method of the present invention.

FIG. 2 is a cross-sectional view when a TCP is mounted on a socket when performing back surface analysis.

FIG. 3 is a cross-sectional view when a TCP for performing a surface analysis is placed on a socket.

FIG. 4 is a sectional view of a PGA on which a failed LSI is mounted.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 LSI chip 2 ILB pad 3 TAB tape 4 lead 5 pad 6 through through hole 7 socket 8 pogo pin 9 cover 10 LSI chip back surface 11 LSI chip surface 12 cap 13 Kovarring 14 TAB lead 15 substrate 16 PGA

Claims (4)

(57) [Claims] 1. A step of removing a faulty integrated circuit from a package, a step of forming an assembly in which the integrated circuit is mounted on a TAB tape provided on both sides with pads connected by penetrating through holes, and a step of forming the assembly. A step of mounting the assembly face-down or face-up on a socket provided with a terminal capable of moving up and down by a spring pressure for bringing the pad into contact with the pad, and a step of performing analysis from the front surface or the back surface of the integrated circuit. A failure analysis method for an integrated circuit, comprising: 2. The method according to claim 1, wherein the analysis from the surface is performed by a probe using an EB tester or a prober. 3. The failure analysis method for an integrated circuit according to claim 1, wherein the analysis from the back surface is performed by emission observation, OBIC method, or OBIRCH method. 4. A failed integrated circuit, a TAB tape to which the integrated circuit is attached, a plurality of first pads formed on one surface of the tape, and a plurality of first pads formed on the other surface of the tape. A plurality of second pads in one-to-one correspondence with a plurality of first pads; a through hole connecting each of the plurality of first pads to a corresponding one of the plurality of second pads; A faulty integrated circuit assembly, comprising: a wiring pattern formed on a tape for electrically connecting the plurality of first pads to the integrated circuit.