JP3033544B2 - Logic circuit verification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI design method, and more particularly to a logic verification method for an LSI having a redundant logic circuit.

[0002]

2. Description of the Related Art In a logic verification of an LSI, particularly in an LSI designed using standard cells, a redundant logic circuit is replaced with a normal logic circuit in advance in order to improve the yield and to easily modify the logic at low cost. Is used separately. For example, Japanese Patent Application Laid-Open No. 4-10
No. 033 discloses that a redundant register is prepared in advance in the design of a standard cell multiprocessor, and if some registers of the processor fail, the effect of the failure is avoided by using the redundant registers to reduce the yield. There has been proposed a configuration that suppresses this.

For example, Japanese Patent Laid-Open Publication No. Hei 2-71613 discloses a method of switching between an AND function or an OR function and a positive output or a negative output with two inputs and one output of an LSI. As a spare gate that can flexibly cope with logic modification by effectively using pins, a logic LSI configured using a scan method, an empty gate of the LSI, a spare gate using an empty pin, and a function of the spare gate are described. A multi-function spare gate system has been proposed which includes a latch for switching and a means for writing data to the latch by a scan input. In this method, a logic circuit that combines a redundant circuit and a scan path is incorporated in a design, so that a logical operation can be easily corrected even when a failure occurs.

As described above, in the design of the standard cell, there is no flexibility in changing the logic as compared with the gate array, and when a logic change occurs, it has to be re-created from the base and the cost increase is ignored. Although it is not possible, by incorporating a redundant circuit in advance, it is easy to modify the logic and the change cost is reduced.

[0005]

As described above, in an LSI design of a standard cell, a redundant circuit, for example, a functional element such as an AND gate or an OR gate, a register (F / F) element, or the like is operated in a normal operation. A method of providing in advance in an area that has no influence is used.
However, the functional elements constituting the redundant circuit have the same function in the process of performing gate resizing processing such as optimization processing of a logic circuit and processing for improving delay, and further, processing such as power consumption countermeasures. In some cases, an element having a different transistor size or driving ability, which is advantageous in design, may be changed.

[0006] For this reason, for example, even if an attempt is made to change or correct the logic using a redundant logic circuit, it may no longer be an element that can be used for the change, and a situation in which the target cannot be changed or corrected may occur. .

Accordingly, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to eliminate or change a redundant circuit prepared in advance for logic change in an LSI design processing process. It is an object of the present invention to provide a logic circuit verification method for performing verification so as not to be performed.

[0008]

In order to achieve the above object, a logic optimization means for optimizing a logic of a sub-block netlist constituting a hierarchy in hierarchically designing an LSI using standard cells, First comparing means for verifying whether or not the specified logic element exists in a sub-block net list after optimization processing based on a name uniquely assigned to the element as a target not to be subjected to logic optimization; A netlist cross-up unit that creates a chip netlist by assembling a list, and while adding delays and power consumption to the chip netlist, adding or changing elements without changing the logical operation Layout means for laying out, and a second method for verifying that the element replacement is not performed on the netlist after the layout. Having a comparing means.

[0009]

Embodiments of the present invention will be described below. According to the logic circuit verification method of the present invention, in a hierarchical design of an LSI using standard cells, a logic element to be excluded from change / correction is specified in advance as location information including the name and position information of the circuit element, and the hierarchy is defined. In the logic optimization means for optimizing the logic of the sub-block netlist to be configured, the logic element specified by the location information is excluded from the optimization processing target, and the optimization processing is performed by the logic optimization means. Means for verifying the presence of the specified logic element by referring to the location information with respect to the sub-block netlist after the execution. Further, in the layout arrangement / wiring means for arranging / wiring the chip netlist created from the sub-block netlist by the cross-up means, the logic element specified by the location information may have a delay or power consumption. Is excluded from the target of element change / replacement processing in consideration of the above, and it is verified whether or not the change / replacement of the specified logic element is performed by referring to the location information with respect to the netlist after layout. There is a means to do.

According to the embodiment of the present invention, the pre-installed redundant circuit performs logic optimization, delay in layout layout and wiring steps, gate resizing and power conversion due to power consumption, etc., which are performed in the LSI design process. In the processing of (1), the modification / change can be suppressed, and it can be easily verified that the redundancy circuit has not been modified / changed, so that it can be effectively used for the modification of the logic using the redundancy circuit. .

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to describe the above-described embodiment of the present invention in more detail, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram for explaining an embodiment of the present invention, and is a logic circuit diagram showing an example of a sub-block netlist having an LSI to be hierarchically designed. Referring to FIG. 1, function 1, function 4, and function 5
D element, function 2 is flip-flop (F / F), function 3
Is a NOR element, dummy 1 is an OR element, dummy 2 is NAN
D element.

Each of the dummy elements 1 and 2 is an element incorporated in advance as a redundant circuit, and has no connection to other logic circuits and is an isolated circuit so as not to affect normal logic operation. However, when a logic change occurs, the logic is used to correct the logic within a range that can be corrected using the dummy element. Here, the correction of the logic includes disconnection and reconnection by laser processing or the like.

FIG. 2 is a diagram showing a processing flow of an embodiment of the present invention. Referring to FIG. 2, the sub-block netlist 100 is, for example, a netlist as shown in FIG. 1, and the chip netlist 130 is created by merging a plurality of netlists such as the samab block netlist 100. You.

The operation of one embodiment of the present invention will be described with reference to the sub-block netlist shown in FIG. 1 and FIG.

The optimization process in the logic optimization 200 corresponds to a process of reconfiguring an equivalent logic or deleting a redundant circuit. That is, since the dummy elements 1 and 2 in FIG. 1 are isolated elements without connection to other logic circuits, they are treated as circuits to be deleted in the logic optimization 200, and after the logic optimization processing. In the sub-block netlist, the dummy elements 1 and 2 are deleted.

In this embodiment, a location assigned to the dummy element is designated in the location designation 110 such that the dummy elements 1 and 2 are excluded from the logic to be subjected to the logic optimization processing in advance. Are excluded from the target of the optimization processing.

The location designation 110 lists, for the elements that cannot be modified or changed, identification information previously assigned uniquely to all the elements, for example, name and position information (referred to as “location information”). Keep it.

The comparing means 220 outputs the sub-block netlist 120 optimized by the logic optimization 200.
, A check is made as to whether the dummy element has been deleted using the information of the location designation 110.

That is, the comparing means 220 adds the location designation 11 to the sub-block netlist 120.
Whether or not the location information listed in “0” is defined is checked one by one to check whether or not there is an element that cannot be corrected or changed. As a result, if all the elements listed in the location designation 110 are present in the sub-block netlist 120 (not deleted by the logic optimization 200), if OK (OK), they are listed in the location designation 110. If none of the elements exist, a report of NG (impossible)
Output as log 1 (140).

The cross-up means (XUP) 210 creates the chip net list 130 by assembling the sub-block net list 120 at a higher level.

Further, the layout arrangement / wiring 230
The layout is performed on the chip netlist 130 in consideration of delay and power consumption. For example, when arranging elements such as function 1,..., Function 5, delay is taken into consideration, and if the line length between elements is long, a relay element is inserted to suppress deterioration of delay. . In addition,
Replacement with an element that is advantageous for delay and power consumption, for example, for parts where the delay is not strict with respect to design specifications, lower the element power (low power consumption) in consideration of power consumption, or conversely, Critical paths are placed and routed while taking countermeasures against delay such as increasing the power.

The processing of the layout arrangement / wiring 230 is not limited to simply arranging elements, and also performs element replacement without changing the logical operation. For this reason, the dummy arrangements 1 and 2 are also subjected to the layout arrangement / wiring processing.
, The specified element is excluded from the replacement processing target.

In the comparing means 250, the chip net list 150 after the layout processing and the location information 1
10, the same check as the comparison means 220 is performed using the log 2 (170). That is, if all the elements listed in the location designation 110 are present in the chip netlist 150, the result is OK (OK). If at least one of the elements listed in the location designation 110 does not exist, the result is NG (impossible). ) Report, log 2
Output as (170)

After confirming the result of the log 2 (170), if there is no problem, the EB (electron beam) processing 24
0 is used to create a mask 160.

[0025]

As described above, according to the present invention, L
In the process of logic optimization, delay in layout layout and wiring process, gate resizing and power conversion due to power consumption, etc., which are performed in the logic design process of SI, modification and change of the redundant circuit are suppressed. It is possible to easily verify that no correction or change has been made.

[Brief description of the drawings]

FIG. 1 is a logic circuit diagram for explaining an embodiment of the present invention.

FIG. 2 is a diagram showing a processing flow of an embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 subblock netlist 110 location designation (location information) 120 subblock netlist 130 chip netlist 140 log 1 150 chip netlist 160 mask 170 log 2 200 logic optimization 210 XUP 220 comparison means 1 230 layout arrangement -Wiring 240 EB processing 250 Comparison means 2

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁷ Identification code FI H01L 21/82 C

Claims (3)

(57) [Claims] 1. A logic circuit verification method in an LSI hierarchical design using standard cells, comprising: logic optimization means for optimizing the logic of a sub-block netlist constituting a hierarchy; For the logic element designated as outside, based on the unique name given to the logic element, a sub-block netlist after performing logic optimization processing verifies the existence of the designated logic element. 1, a netlist / cross-up means for assembling the sub-block netlist to create a chip netlist; and performing a logical operation on the chip netlist in consideration of delay and power consumption. The layout arrangement / wiring means for laying out while adding or changing elements without making any changes Based on the unique name assigned to the device, the logic circuit verification method characterized by comprising second comparing means for verifying whether the substitution of the logic elements specified is performed, a. 2. In a hierarchical design method for an LSI using standard cells, a logical element to be excluded from change / correction is specified in advance as location information including the name and position information of the logical element, and A logic element specified by the location information is excluded from optimization processing targets by a logic optimizing means for optimizing the logic of the block netlist, and after the optimization processing is performed by the logic optimizing means. Means for verifying the presence of the specified logical element by referring to the location information with respect to the sub-block netlist, and for a chip netlist created from the sub-block netlist by cross-up means. In the layout arrangement / wiring means for arrangement / wiring, the location information is also used. The logic element specified in the information is excluded from the element change / replacement processing in consideration of delay and power consumption, and the specified logic element is referred to the layout netlist by referring to the location information. A means for verifying whether or not a change or replacement has been made to the logic circuit. 3. An LSI hierarchical design method using standard cells, comprising: (a) logic optimization means for optimizing the logic of a sub-block netlist constituting a hierarchy, wherein
Logic optimizing means for excluding a logical element specified by location information consisting of the name and position information of the logical element from a logical element to be excluded from the optimization processing; (b) the logical optimizing means Means for verifying the presence of the specified logic element with reference to the location information with respect to the sub-block netlist after the optimization processing has been performed; A layout arrangement / wiring means for arranging / wiring the created chip netlist, wherein a logic element specified by the location information is subjected to an element change / replacement process in consideration of delay and power consumption. (D) the layout of the netlist after layout, Means for verifying whether or not the specified logic element has been changed / replaced with reference to the information; and recording a program for causing each of the above means (a) to (d) to function on a computer. recoding media.