JP3033481B2 - Phase comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase comparator,
In particular, the present invention relates to a phase comparator used for synchronous detection demodulation and the like.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing an example of a conventional phase comparator. This conventional phase comparator comprises a Gilbert cell type four-quadrant multiplication circuit and a low-pass filter. The four-quadrant multiplication circuit is composed of active elements such as NPN-type bipolar transistors. Here, NPN-type transistors Q11 and Q12 whose emitters are connected in common, and NPN-type transistors Q13 and Q14 whose emitters are connected in common are respectively provided. An upper-stage emitter-grounded differential amplifier circuit is formed, and each emitter is connected to a NP connected to a constant current source 7.
N-type transistors Q15 and Q16 form a lower-stage grounded-differential amplifier circuit, and a two-stage cascade-type differential amplifier circuit in which the upper and lower differential amplifier circuits are vertically connected in two stages. doing.

The collectors of transistors Q11 and Q13 forming the above-mentioned upper-stage grounded-differential amplifier are connected to each other and to a power supply voltage terminal 8 via a load resistor R3. Similarly, transistors Q12 and Q14 forming an upper-stage common-emitter type differential amplifier circuit
Are connected to each other and to the power supply voltage terminal 8. The constant current source 7 allows the current I of the four-quadrant multiplication circuit to flow.

The input terminals 21, 22, 2 of a four quadrant multiplying circuit
3 and 24, the input terminal 21 receives a reference signal vi1 for phase comparison and an appropriate potential V1.
, A suitable potential V1 same as that of the input terminal 21 is input, a signal vi2 for phase comparison and a proper potential V2 are input to the input terminal 23, and an appropriate potential V2 same as that of the input terminal 23 is input to the input terminal 24. Is entered. The output terminal 25 of the four-quadrant multiplication circuit outputs a signal v obtained by converting the sum of the collector currents of the transistors Q11 and Q13 into a voltage by the load resistor R3.
0 is obtained as an output signal. The output signal v0 taken out of the output terminal 25 has a high-frequency component removed by a low-pass filter 26, and the DC voltage component V
Output as a.

Next, the operation of the four-quadrant multiplication circuit will be described.

Now, a reference signal vi1 = E1sinωt for phase comparison is input to an input terminal 21.
Assuming that a signal vi2 = E2sin (ωt + φ) having a relative phase difference φ with respect to the reference signal vi1 is input to the reference signal 3 (where E1 and E2 are amplitude components of the input signal and ω is an angular frequency), the output terminal 25 Outputs v0 which is the product of vi1 and vi2 expressed by the following equation.

[0007]

(Equation 1) Here, in the above equation, K is the conversion amplification factor of the four-quadrant multiplication circuit, and −1 ≦ cosφ ≦ 1. As can be seen from the equation (1), the amplitude of the output signal v0 is (K · E1 / E2).
/ 2, which is proportional to the cosine angle of the relative phase difference φ between the signal of the frequency component twice as much as the input frequency and the input signal.
2) Consists of a DC component of / 2 @ cosφ. This output signal v0 is input to the low-pass filter 26, where the twice frequency component is removed, and the DC component Va (= （(K · E1 · E)
2) / 2 Only cos φ) is output as the offset voltage. Therefore, this conventional phase comparator is used for synchronous detection demodulation or the like by controlling the voltage controlled oscillator using the action of generating an offset voltage proportional to the relative phase difference φ.

Next, the voltage distribution between the power supply voltage and the reference voltage (ground) of the four-quadrant multiplying circuit constituting the conventional phase comparator will be described. As shown in FIG.
0, V _CE1 , V _CE2 and V _EE . v0 is the output voltage at the output terminal 25, which is the maximum potential difference at which the output signal is generated, that is, the load resistance R3 and the current I of the four-quadrant multiplication circuit.
And (R3 · I). Also, V
_CE1 is between the collector and emitter of the transistors Q11, Q12, Q13, Q14 forming the upper grounded-emitter differential amplifier circuit voltage, V _CE2 is of the transistors Q15, Q16 forming the lower grounded-emitter differential amplifier circuit The collector-emitter voltage, V _EE, is a voltage required to construct the constant current source 7.

In order for the four-quadrant multiplying circuit to perform a normal phase comparison operation at a high frequency, it is necessary that the DC characteristics of each transistor constituting the transistor be an operating point in an unsaturated region. That is, the collector-emitter voltages V _CE1 and V _CE2 of each transistor require a minimum voltage of about 0.6 V to 0.8 V. Further, in order for the four-quadrant multiplication circuit to perform a desired phase comparison operation, it is desirable that the maximum potential difference v0 for generating an output signal is large. In order to supply a stable current to the four-quadrant multiplication circuit, V _EE is also required. Larger is desirable.

[0010]

However, in the conventional four-quadrant multiplying circuit constituting the phase comparator, each transistor Q11 forming an upper-stage grounded-emitter differential amplifier circuit is used.
Each transistor Q1 forming the collector-emitter voltage V _CE1 and lower grounded-emitter differential amplifier circuit ~Q14
5. The minimum voltage between the collector-emitter voltage V _{CE2 of} Q16 and 0.6 V to 0.8 V, respectively, is required.
Since V _EE was necessary required to configure the maximum potential difference component v0 and the constant current source 7 that generates an output signal thereto, it has been very difficult to reduce the voltage of the power supply voltage. At present, a phase comparator which actually achieves a low voltage and obtains desired characteristics and is practically used has a power supply voltage of about 3 V at most and a power supply voltage lower than the power supply voltage becomes difficult.
There are few practical examples.

The present invention has been made in view of the above points, and an object of the present invention is to provide a phase comparator capable of operating at a low voltage by setting the number of transistors to one between a power supply voltage and a reference potential. Aim.

[0012]

According to the present invention, in order to achieve the above object, the emitters are commonly used as a first constant current source.
The first and second transistors connected to each other,
The phase comparison reference signal is input to the base of the transistor
And a reference voltage is applied to the base of the second transistor.
And a first emitter-grounded differential amplifier circuit
The third and fourth common terminals are commonly connected to a second constant current source.
Consisting of a transistor, the base of the third transistor
A signal for phase comparison is input, and the fourth transistor
A second grounded emitter differential in which a reference voltage is applied to the source
Amplifying circuit and respective collectors of the first and third transistors
Or each collector of the second and fourth transistors.
One end is connected, and the other end is connected to the load resistance connected to the power terminal.
And a common connection between the load resistance and the collector of the transistor.
In this configuration, an output signal is extracted from a continuation point.

According to the present invention, two signals input to the first and second grounded-emitter differential amplifier circuits are respectively differentially amplified with the same reference voltage, and then the load resistance and the transistor are changed.
Since the output is synthesized from the common connection point with the collector of the
A signal having an amplitude corresponding to the phase difference between the above two signals can be taken out from the common connection point with .

Here, the load resistance and the transistor
By the provision of the rectifying means for outputting a DC signal proportional to the amplitude of the output signal taken from the common connection point of the collector, it is possible to obtain a level of the DC signal corresponding to the amplitude.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit diagram of an embodiment of the phase comparator according to the present invention. As shown in the figure, NPN transistors Q1 and Q2 constitute a first common-emitter type differential amplifier circuit,
3 and Q4 constitute a second common-emitter differential amplifier circuit. The collectors of the transistors Q1 and Q3 are connected to a power supply voltage terminal 8 via a load resistor R1. On the other hand, the respective collectors of the transistor Q2 and the transistor Q3 are connected to the power supply voltage terminal 8, respectively.

The common emitter of the first common-emitter differential amplifier is connected to a constant current source 7 and the common emitter of the second common-emitter differential amplifier is connected to a constant current source 9. Each is connected to the ground terminal 10 via the corresponding terminal. Further, the transistors Q1 and Q3 and the load resistance R
1 is connected to the output terminal 5. Thus, the collector currents of the transistors Q1 and Q3 are added, and the added current is converted into a voltage by the load resistor R1 and output to the output terminal 5 as the output signal v0.

The bases of the transistors Q1, Q2, Q3 and Q4 are connected to input terminals 1, 2, 3 and 4, respectively. The input terminal 1 has a reference signal vi1 for phase comparison and an appropriate reference voltage. V _R is applied and input terminal 3
A signal vi2 performing the phase comparison on the same appropriate reference voltage V _R is applied to the input terminal 1, the same suitable reference voltage V _R and the input terminal 1 is supplied to the input terminal 2 and 4. In addition,
The output terminal 5 of this phase comparator is connected to the anode of a rectifying diode 11 that constitutes a diode rectifier shown in FIG.

Next, the operation of the embodiment shown in FIG.
This will be described with reference to FIGS. Now, a phase comparison reference signal vi1 represented by the following equation vi1 = Esinωt (2) and having a waveform shown in FIG. 3A is input to the input terminal 1 of the phase comparator, and It is assumed that a signal vi2 expressed by the equation vi2 = Esin (ωt−90 °) = − Ecosωt (3) and performing a phase comparison of the waveform shown in FIG. 3B is input.

In this case, the collector current I _{C1 of the} transistor Q1 to which the phase comparison reference signal vi1 is input to the base.
And the voltage drop due to the load resistor R1, the collector potential v _C1 of the transistor Q1 becomes a potential obtained by inverting and amplifying the input signal vi1, and is expressed by the following equation.

V _C1 = −AE sin ωt (4) In the equation (4) and each of the following equations, A is the amplification factor of the common-emitter type differential amplifier circuit. Similarly, the collector potential V _C3 of the transistor Q3, which is caused by the voltage drop due to the collector current I _{C3 of the} transistor Q3 and the load resistor R1 to which the signal vi2 for phase comparison is input to the base, inverts the base input signal vi2 of the transistor Q3. This is the amplified potential and is represented by the following equation.

V _C3 = AEcosωt (5) Then, the voltage of the sum of these collector potentials v _C1 and v _C3 is output to the output terminal 5 as the output signal v0. Therefore,
The output signal v0 is expressed by the following equation from the equations (4) and (5).

V0 = v_C1+ V_C3= AE (-sinωt + cosωt) = √2AEcos (ωt + 45 °) (6) The above collector potential v_C1And v_C3And output signal v 0 is FIG.
(E) respectively.

Next, the same phase comparison reference signal vi1 as described above is input to the input terminal 1. The input terminal 3 receives the following equation of the relative phase difference 90 ° + θ with respect to the phase comparison reference signal vi1. vi2 ′ = Esin (ωt− (90 ° + θ)) = − Ecos (ωt−θ) (7) If the signal vi2 ′ shown in FIG. 3C is input, the collector of the transistor Q3 Current I _C3
And the voltage drop due to the load resistor R1, the collector potential v _C3 ′ of the transistor Q3 becomes a potential obtained by inverting and amplifying the input signal vi2 ′.

V _C3 ′ = AEcos (ωt−θ) (8) Therefore, as described above, the voltage of the sum of the collector potential v _C3 ′ and the collector potential v _C1 is output to the output terminal 5 as the output signal v0 ′. Therefore, the output signal v0 ′ becomes (4)
The following equation is obtained from the equation and the equation (8).

[0025]

(Equation 2)Therefore, as can be seen from equation (9), the phase comparison reference signal
(90 ° + θ) between vi1 and the input signal vi2 ′
When there is a phase difference, the amplitude of the phase comparison reference signal vi1 is changed.
The output signal v0 whose width is multiplied by √ (2-2 sin θ) A is
Is output. Collector potential v at this time_C1And v_C3'When
Output signal v 0 'is shown in FIG. 3 (F).

Next, the same phase comparison reference signal vi1 as described above is input to the input terminal 1. The input terminal 3 has a relative phase difference of 90 ° -θ with respect to the phase comparison reference signal vi1. Assuming that the expression vi2 ″ = Esin (ωt− (90 ° −θ)) = − Ecos (ωt + θ) (10) and the signal vi2 ″ shown in FIG. 3D is input, the transistor Q3 Collector current I
The collector potential v _C3 ″ of the transistor Q 3 becomes a potential obtained by inverting and amplifying the input signal vi 2 ″ due to the voltage drop due to _{C 3} and the load resistance R 1, and is expressed by the following equation from the equation (10).

V _C3 ″ = AEcos (ωt + θ) (11) Therefore, as described above, the voltage of the sum of the collector potential v _C3 ″ and the collector potential v _C1 is output to the output terminal 5 as an output signal v 0 ″. Therefore, the output signal v0 ″ is expressed by the following equation from the equations (4) and (11).

[0028]

(Equation 3)Therefore, as can be seen from equation (12), the phase comparison reference signal
Between signal vi1 and input signal vi2 ″ (90 ° −θ)
, The phase comparison reference signal vi1
Signal v whose amplitude is multiplied by √ (2 + 2 sin θ) A
0 ″ is output. Collector potential v at this time_C1as well as
v_C3″ And the output signal v 0 ″ is shown in FIG.
Is done.

As described above, according to this embodiment, the input phase comparison reference signal vi1 and the input signal vi2 (vi
2 ′, vi2 ″, etc.), the amplitude of the output signal v0 changes according to the relative phase difference θ. Accordingly, the two input signals vi1 and vi2 are converted into a DC component by, for example, a diode rectifier.
, An offset voltage proportional to the relative phase difference can be generated.

FIG. 2A is a circuit diagram of a typical example of the diode rectifier, and FIG. 2B is a waveform diagram of each part. As shown in FIG. 2A, the diode rectifier comprises a rectifying diode 11 whose output terminal 5 is connected to the anode.
And a capacitor 12 having a capacitance C connected between the cathode of the rectifying diode 11 and the ground terminal. A common connection point between the cathode of the rectifying diode 11 and the capacitor 12 is connected to the output terminal 13. I have. This diode rectifier outputs a rectified voltage Va from an output terminal 13 to a load 14 having an impedance Z.

Now, when the output signal v0 is inputted from the terminal 5, this signal v0 becomes the reference output voltage Vc of the phase comparator.
The positive peak portion of cI · R1 (power supply voltage is set to Vcc) is half-wave rectified by the rectifying diode 11 and charges the capacitor 12. Thereby, the terminal voltage of the capacitor 12 increases with the rise of the input signal v0, and when the input signal v0 starts to decrease after reaching the maximum amplitude, the rectifying diode 11 is reverse-biased and the capacitor 12 starts discharging. . Then, the terminal voltage of the capacitor 12 decreases at a discharge time constant determined by the capacitance value C of the capacitor 12 and the impedance Z of the load.

Thereafter, the positive peak portion of the input signal v0 input via the rectifying diode 11 is
, The capacitor 12 is charged again by the input signal v0. Therefore, by setting the capacitance value C to a value having a discharge time constant that is sufficiently longer than the cycle of the input signal v0, the load shown in FIG. 2A as shown in FIG. The output voltage for driving 14 becomes an output voltage Va near the maximum amplitude of the input signal v0, and outputs an output voltage proportional to the relative phase difference from the phase comparator.

It should be noted that the present invention is not limited to the above-described embodiment. For example, the diode rectifier may be a full-wave rectifier circuit. The signal vi is input to the input terminals 2 and 4 of FIG.
1, may be input to vi2 (in this case, inputs the reference voltage V _R to the input terminal 1 and 3).

[0034]

As described above, according to the present invention,
The two signals input to the first and second grounded-emitter differential amplifier circuits are respectively differentially amplified with the same reference voltage, and then combined and output by the adder circuit. Since the signal having the amplitude corresponding to the phase difference of the signal is taken out, the output signal of the phase comparator can be obtained by the one-stage grounded emitter differential amplifier circuit connected between the power supply voltage and the reference voltage (ground). Therefore, compared to a conventional phase comparator having a cascade connection configuration in which two-stage grounded-differential amplifier circuits such as a four-quadrant multiplication circuit are vertically stacked, the voltage required between the collector and the emitter of the transistors to be formed is required. The voltage can be reduced by one stage as compared with the prior art, and therefore, there is an effect that operation can be performed at a low voltage up to about 2 V of the power supply voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of a circuit to which an output signal of the phase comparator of FIG.

FIG. 3 is a time chart for explaining the operation of FIG. 1;

FIG. 4 is a circuit diagram of an example of a conventional phase comparator.

[Explanation of symbols]

1, 2, 3, 4 Phase comparator input terminal 5 Phase comparator output terminal 7, 9 Constant current source 8 Power supply voltage terminal 10 Ground terminal 11 Rectifier diode 12 Capacitor 13 Output voltage terminal 14 Load R1 Load resistance Q1 to Q4 NPN type transistor V _R reference voltage

Claims (2)

(57) [Claims] 1. A first constant current source whose emitters are common to each other.
The first and second transistors connected to
The phase comparison reference signal is input to the base of one transistor.
And a reference voltage is applied to the base of the second transistor.
And a first grounded-type differential amplifier circuit having a common emitter connected to a second constant current source.
A third transistor comprising a third transistor and a fourth transistor.
The signal for phase comparison is input to the base of the
A second electrode in which the reference voltage is applied to the base of the transistor.
A grounded-mitter-type differential amplifier circuit, and each collector of the first and third transistors, or
One end is connected to each collector of the second and fourth transistors.
Are continued, have a load resistor and the other end of which is connected to a power supply terminal
The load resistance and the collector of the transistor
A phase comparator for extracting an output signal from a connection point . 2. The method according to claim 1, wherein said load resistor and said transistor are connected together.
2. A phase comparator according to claim 1, further comprising rectifying means for outputting a DC signal proportional to the amplitude of an output signal taken out from a common connection point with the rectifier.