JP3033091B2 - Automatic translation method from digital circuit data to logic simulation description language - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for translating digital circuit data into a logic simulation model description language.

[Conventional technology]

Conventionally, when translating digital circuit data into a logic simulation description language, a logical function of the digital circuit is used as a black box to extract only connection relations and translate into a specific language format.

[Problems to be solved by the invention]

With the conventional method described above, even if you look at the translated description,
There is a drawback that it is difficult to understand what kind of logic is configured, and the work efficiency of logic simulation is poor.

[Means for solving the problem]

An automatic translation system according to the present invention is an automatic translation method for generating a logic simulation description language from graphic data of a digital circuit into a logic simulation description language using a computer, wherein the digital circuit graphic data is stored on a magnetic disk. And a logical function name having no memory or / and a logical function name having a memory, and logical connection information including a line name and a signal name unique to each logical function name. If there is no logical function name, the logical command name and the line name included in the logical connection information are used as key words, and an edit command table that defines a method of translating into a simulation description language for each logical function name is magnetically generated. In the case of a logical function name that has been created on a disk and has a memory, it has a memory in addition to the logical connection information. Using an intermediate variable for replacing a logical function name with a unique name, an edit command table defining a method of translating into a simulation description language for each of the logical function names is created on a magnetic disk. The logical connection information is sequentially read out, and the signal names are sequentially translated into a logic simulation description language corresponding to the line names or intermediate variables in the edit command table from the edit command table corresponding to the logical function names, and are translated to a magnetic disk. It is characterized by outputting.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a processing flowchart showing one embodiment of the automatic translation method of the present invention. The edit command table 201, the circuit data 202, and the logic simulation description language 203 are stored as files. A program that specifically realizes this processing flow as a function is written by a compiler such as FORTRAN.

FIG. 2 is a block diagram showing an automatic translation system configuration when this program is realized on a normal computer. The three files 201, 202, 203 of FIG. 1 are stored on the magnetic disk 4. The circuit data is created by, for example, a CAE (Computer Aided Engineering) workstation implemented on a personal computer. The editing command table is obtained by inputting data from the keyboard 2 to the host computer 3. Other functions of the keyboard 2 include inputting a translation program and giving an execution instruction to the host computer 3. The program operates by being loaded on the main memory of the host computer 3.

Next, the operation of the present invention will be described with reference to FIG. First, in step 101, an edit command table (to be described later) is created for all logical functions to be used in the digital circuit, and stored in the edit command table file 202. It is desirable that the edit command table file 202 be created in advance. Next, in step 102, from the circuit data file 201 (circuit data will be described later),
Read one of the logic functions of the digital circuit. In step 103, it is checked whether or not there is any unprocessed data among the circuit data, that is, whether or not the circuit data has ended. If the circuit data has been read rather than the end, in step 104, an edit command table corresponding to the read logical function is read from the file 202. Next, in step 105, the read circuit data is translated into a logic simulation description language (to be described later) in accordance with the edit command table, and the result is stored in the logic simulation description language file 203 to be used as basic information of the logic simulation.

FIG. 3 is a circuit diagram showing an example of a digital circuit obtained by inputting at the CAE workstation of the personal computer 1 of FIG. 10 is a decoder, 11 is input data to the line name A #, the signal name is "PRB0 (0-2)", and has a size of 3 bits. 12 is a control line to the line name EI, the signal name is "A006 [Y]", 13 is the output data from the line name Y #, and the signal name is "DEC0 (0-7)" and the size is 8 bits. The host computer 3 has the digital circuit data file in the magnetic disk file 4 in the format shown in FIG. This example shows only a portion corresponding to the decoder 10 (indicated by rows A and B on the data).
.. Indicate the coordinate values on the circuit diagram, A005 indicates the part number, “DEC #” indicates the logical function name, and “A0”- “Y7” is a line name unique to the logic function, and “PRB0 (0)” to “DEC0 (7)” are signal names indicating that the logic functions have the same potential. L indicates an input signal to the logic function, and S indicates an output signal. This circuit data is previously collected for each logic function.

FIG. 5 is a diagram showing an example of the format of an edit command table for translating digital circuit data into a logic simulation description language. FIG. 6 is a diagram showing examples of symbols input into the format of FIG. 5 and their meanings. In each column of the format shown in FIG. 5, as shown in FIG. 6, the number of lines indicating the definition of the logical function name, function type, and intermediate variable required as a table, an edit command The number of rows in which to store is stored, and other necessary definition statements for each row are input, and configured to function as a table.

FIG. 7 is a diagram showing an example of an edit command table of the decoder part for translating the circuit diagram data of the decoder part shown in FIG. 4 into a logic simulation description language. "DEC #" in the SCODE column as the logical function name, "SMAC" in the FTYPE column as the function type, and RNO1 column as the number of defined lines in the intermediate language (because there is no definition in this example)
“0” is input to the RNO2 column as “4” lines as the number of lines to store the edit command. After the next line, RNO2 in the first line
Since the "4" line has been input in the column of, the edit command is stored over four lines. That is, "1" is shown as a line feed mark on the second line, "2" is displayed as a column position on the right side, "TERMINAL" is displayed as text 1, "6" is displayed as a column position, and logical functions are performed as LP1N. Unique line name (output of decoder in this example) "Y #"
Is further stored as text. Specific commands are input and stored after the next line. “A #” and “Y #” represent “A0 to A2” and “Y0 to Y7” in FIG. “EI” is the same as “EI” in FIG.

FIG. 8 is a diagram showing an example of translation into a logic simulation description language, and shows the result of translating the digital circuit data of FIG. 4 in accordance with the edit command table of FIG. Note that the language used here is one of the Behavior Description types.

FIG. 9 is a circuit diagram showing an example of a sequence controller as a second example of translation. When this sequence controller is translated according to the edit command table shown in FIG. 10, a translation result as shown in FIG. 11 is obtained. . #REG, #SP, #RAM, and #INC, which are intermediate variables, are replaced with unique signal names S011, S012, S013, and S014, respectively. For simplicity of explanation, the line names and signal names unique to the logic function are the same.

〔The invention's effect〕

As described above, according to the present invention, the individual logic functions can be expressed in the logic simulation description language, so that the efficiency of the logic simulation is high. In addition, since the editing command table is used, the translation program is simplified, so that the execution speed is high.

○ Since intermediate variables can be used, logical functions with multiple stages of memory inside can be easily understood and easily translated.

○ Maintenance and operation are easy because logic functions can be added and replaced freely.

The effect is enormous.

[Brief description of the drawings]

FIG. 1 is a processing flow diagram showing one embodiment of the present invention, FIG. 2 is a system block diagram for implementing the present invention, FIG. 3 is a circuit diagram showing an example of a first digital circuit translated by the present invention,
FIG. 4 is a diagram showing circuit data of the decoder part of FIG. 3,
FIG. 5 is a diagram showing a format of an edit command table, FIG. 6 is a diagram showing examples of symbols input into the format of FIG. 5 and their meanings, and FIG. 7 is a circuit diagram shown in FIG. FIG. 8 shows an example of an editing command table for translating data, FIG. 8 shows a result of translating the data shown in FIG. 4, and FIG. 9 shows an example of a second digital circuit for translating according to the present invention. FIG. 10 is a circuit diagram, FIG. 10 is a diagram showing an example of an edit command table corresponding to the circuit diagram of FIG. 9, and FIG. 11 is a diagram showing a translation result. 1 denotes a personal computer, 2 denotes a keyboard, 3 denotes a host computer, 4... Magnetic disk files, 101 to 105 denote processing steps, and 201 to 203 denote files.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-9761 (JP, A) JP-A-63-115270 (JP, A) JP-A-1-309185 (JP, A) Iwamatsu Matsumoto, 4 others, "Functional Diagram Input System", Proc. Of the IPSJ National Convention, IPSJ, September 1984, Vol. 29, No. 3, p. 1639-1640 (58) Fields surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. A method of automatically translating a logic simulation description language from graphics data of a digital circuit into a logic simulation description language using a computer, wherein the graphics data of the digital circuit is stored on a magnetic disk, And a logical function name having no memory and / or a logical function name having a memory, and logical connection information including a line name and a signal name unique to each logical function name. In the case of a name, the logical function name and the line name included in the logical connection information are used as key words, and an edit command table defining a translation method into a simulation description language for each logical function name is created on the magnetic disk. In the case of a logical function name having a memory, the logical function name having a memory in addition to the logical connection information Using an intermediate variable for replacing with a unique name, an edit command table defining a method of translating into a simulation description language for each of the logical function names is created on a magnetic disk, and the logical connection information is obtained from the graphic data of the digital circuit. Sequentially reading out, from the edit command table corresponding to the logical function name, sequentially translating the signal names into a logic simulation description language in correspondence with the line names or intermediate variables in the edit command table, and outputting to the magnetic disk. An automatic translation method from featured digital circuit data to a logic simulation description language.