JP3024598B2 - Layout verification method and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout verification method and a recording medium, and more particularly to a stable operation of a semiconductor integrated circuit.
The present invention relates to a layout verification method and a recording medium for assisting a designer in finding uneven power and ground wirings in a layout in order to achieve high reliability.

[0002]

2. Description of the Related Art Heretofore, there has been known a layout verification method for assisting a designer in finding an unevenness in power supply and ground wiring in a layout (for example, see Japanese Patent Laid-Open Publication No. Hei.
206644). This conventional layout verification method verifies a layout according to a procedure as shown in FIG. That is, an element extraction rule 1 that defines a combination of specific layout pattern information acting as a circuit element from the layout pattern information 111 including all circuit elements and wirings
12, the presence of a circuit element is detected as shown in step 113, the type of element such as an N-channel MOS transistor is recognized, parameters such as channel length L and channel width W, parasitic resistance of the element and wiring, Characteristics such as parasitic capacitance are measured, and connection information is extracted (this is called LPE).

[0005] Subsequently, extraction results 114 of voltage, current characteristics, connection information, etc. of each element are obtained based on simulation conditions 115 necessary for simulating circuit operation such as power supply voltage, temperature, input signal, output load conditions, and the like. Is used to calculate the voltage of each node, the current flowing through each element, and its temporal change, and simulates the circuit operation (step 116). Next, based on the simulation result 117 obtained by the simulation, an operation of extracting nodes connected to the power supply and the ground, and performing a rank classification according to the degree of the drop from the power supply voltage and the rise from the ground voltage of each node is performed. Perform (step 118)
The calculation result is displayed on the layout on the display unit in correspondence with different colors for each rank (step 119). This display allows the designer to identify a defective portion of the power supply or ground wiring.

[0004]

In designing large-scale integrated circuits, it is necessary to supply sufficient power over a large chip area. If there is a circuit that is connected only with a very thin wiring or a detour wiring, the resistance from the power supply pad is large, so that the power supply drop increases, causing a malfunction or increasing the current density, leading to a decrease in reliability due to electromigration. Conventionally, an LVS verification tool is used to check the connection of the circuit pair layout. However, with the LVS verification tool, even if the wiring is thin,
If they were connected, no error would occur, so it was not possible to verify without mistake that all wiring was performed evenly.

For this reason, a layout verification method as shown in FIG. 11 has conventionally been proposed. However, in practice, a designer only verifies a part of the layout manually using a circuit simulator. Had occurred.

That is, the problem of the conventional layout verification method is that the operation is large-scale and complicated, and the 64-Mbit DR
It cannot be applied to large-scale integrated circuits such as AM.

The reason is that all elements including parasitic elements, wiring resistance including a large number of branches connected to terminal elements, and wiring capacitance are omitted and are separately extracted without degeneration, resulting in very large-scale circuit data. This is because 64 megabit DR
The AM has more than 67 million cell transistors, capacitors, and peripheral circuits for controlling them. During the simulation,
If a calculation of one element requires a storage capacity of 0.5 kilobytes, 10 million elements already require 5 gigabytes. This exceeds the storage capacity of the computer normally used for the design.

Although the processing capacity of a computer increases year by year, the scale of a semiconductor integrated circuit to be designed also increases, so that this relationship does not change unless the algorithm is significantly changed. Large-scale circuit operation simulation requires a large amount of data storage area in the device, and requires enormous calculation processing related to the nonlinearity of the transistor. It was not practical because it lasted more than a day.

Among large-scale integrated circuits, especially in the case of a semiconductor memory device, memory cells for storing information are regularly arranged, and a decoder, a sense amplifier, and peripheral circuits are arranged around the memory cells. The memory cell array occupies most of the chip area, and data must be referenced and written uniformly in all chip areas. Since the arrangement of the memory cell array is regular, the power consumption becomes substantially equal. For this reason, it is important to arrange the power supply wiring evenly in a loop shape and a mesh shape. If the power supply wiring is biased or a part of the loop is broken, there will be a place where the resistance of the wiring to the power supply pad is large, which will hinder the writing and reading of data to and from the cell array close to the place. This causes a decrease in reliability such as electromigration.

[0010] The present invention has been made in view of the above points,
It is an object of the present invention to provide a layout verification method and a recording medium for quickly verifying that a power supply, a ground, and other main signal lines in a large-scale integrated circuit are evenly laid out on a chip.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for generating power from layout pattern information based on layout pattern information and layer information of a semiconductor integrated circuit.
In addition to extracting the wiring element resistance corresponding to the wiring connected to the power supply pad, omitting the lowest wiring,
Omitting the branch wiring that leaves the upper power supply wiring to be connected,
Wiring obtained by performing equipotential tracking after wiring omission processing
Element resistance obtained by calculating the resistance from the layout pattern
Degeneration processing performed on resistance data and wiring element resistance
After or after the extraction, the combined resistance values from the pad to each point are calculated based on the extracted wiring element resistances, and the combined resistance values are ranked and displayed on the layout. It was made.

In the present invention, only the wiring element resistance is extracted from the layout pattern information.
Data to be processed can be greatly reduced as compared with the conventional case. Only
However, in the present invention, before or after extracting the wiring element resistance,
Performs branch wiring omission processing and series and parallel resistance degeneration processing
Each point while relaxing the absolute accuracy
Omission and degeneration processing while maintaining the relative conditions of
Data to be processed can be reduced. Furthermore, the present invention provides
When calculating resistance, simplification using the minimum cumulative resistance value
By doing so, the range to satisfy the purpose of checking the uniformity of wiring
Simplified and faster.

[0013]

[0014]

Further, according to the present invention, the combined resistance values are classified into ranks, and color-coded display corresponding to each rank is performed, and the combined resistance values are displayed on a layout in ascending order of the combined resistance value. According to the present invention, since the display is performed in the order of the low resistance value, the problem portion having the high resistance value is not overwritten, but is reliably displayed, and an arbitrary area can be viewed by the enlargement, reduction, layer selection, and search functions.

Further, according to the present invention, when calculating the combined resistance, all the paths from the pad to the node to be calculated based on the extracted wiring element resistance are formed by a minimum one tree-like connection connecting all the nodes. A tree is divided into a co-tree consisting of element resistances that do not belong to the tree.Independent closed circuits with one co-tree added to the tree are obtained for all co-trees, and Kirchhoff's voltage equation is calculated for all those independent closed circuits. The combined resistance is obtained from individual element voltages obtained upright.

According to the present invention, the combined resistance of all the paths from the pad to the node to be calculated can be calculated, so that a highly accurate calculation result can be obtained only by linear operation.

As described above, according to the present invention, the speed is increased by reducing the amount of data to be calculated and the amount of calculation. In order to increase the speed, the emphasis is on preserving the difference in the relative wiring state of each point on the chip. Absolute accuracy is relaxed while maintaining the relative conditions of each point. Therefore, the non-uniformity of the power supply wiring of the large-scale integrated circuit, which cannot be handled conventionally, can be calculated at high speed and displayed on the layout.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a flowchart of one embodiment of a layout verification method according to the present invention. First, layout pattern information 11 including a layout including all circuit elements and wirings (a layout including only wiring patterns may be used), a layer designation, a layer resistance value, and a pad (PAD)
A process for taking in the designation information 12 and extracting only necessary wiring such as power supply and ground from the pattern is performed (step 13). At this time, the information specified by the designer may be only the wiring layer specification, the unit resistance value for each layer, and the connection pad information 12 serving as a reference for calculating the resistance value.
No information on size measurement is required. If the power supply wiring layer is independent beforehand, it can be used as it is.
When extracting from the entire data, elements such as transistors are deleted, and uninteresting wiring data such as internal wiring is deleted by equal potential tracking. Alternatively, the path may be extracted by performing equipotential tracking from the pad of interest and copying the path to another storage area.

Next, omission and degeneration are performed (step 1).
4), reduce the amount of data. Next, calculation is performed to obtain the partial resistance of each element at each point from the layer resistance value in the information 12 (step 15). Note that the omission and degeneration processing of step 14 may be performed after this resistance calculation.

Next, based on the element resistance extraction result 16 calculated in step 15, a combined resistance calculation for obtaining a resistance value from the pad to each point is performed (step 17), and the combined resistance calculation result 18 is stored in the memory. I do. The calculation of the combined resistance in step 17 can be simplified and accelerated as long as the purpose of checking the uniformity of the wiring is satisfied.

Next, ranking of the combined resistance calculation results 18 is performed (step 19). Attributes that can be determined by the designer, such as color, blinking, and hatching, are assigned to each point, and the ranks are classified according to the resistance value range. The range can be set by the user, and can be used depending on the application, such as emphasizing a terminal wiring having a high resistance value or emphasizing a main wiring having a low resistance value.

Finally, the calculation result is reflected on the layout and displayed on the screen of the display unit (step 20). The display can be enlarged or reduced to see any area. By drawing in order from the portion having the lowest resistance value, even when the image is reduced, the portion having the higher resistance value can be reliably displayed without being overwritten.

The processing shown in FIG. 1 is performed by loading a computer program recorded on a recording medium into a computer and causing the computer to execute the program.

Next, an example of layout display will be described with reference to FIG. FIG. 2A is a layout display in the case of a defect, that is, an uneven power supply wiring. Power connection pad 2
The wiring 2-1-2 connected closest to -1-1 has low resistance and is displayed in blue. The next closest wiring 2-1-3 is displayed in green, the third closest wiring 2-1-4 is displayed in yellow, and the wiring 2-1-5 connected through the farthest path is displayed in red. Looking at this, the wiring 2-1-5 is separated from the power supply connection pad 2-
Since the resistance value is high despite being close to 1-1, it can be determined that the power supply connection pad 2-1-1 and the wiring 2-1-5 should be connected to each other.

FIG. 2B is a layout display in the case where the power supply lines are normal, that is, the power supply lines are even. Power supply connection pad 2-2
The wirings 2-2-2 and 2-2-5 near -1 have low resistance,
Displayed in blue. Next, the connected wirings 2-2-3, 2
-2-4 is displayed in green. From this, it can be determined that the wires are evenly distributed because there are no high-resistance wires displayed in yellow and red, and there are no wires that are remarkably different in color while being close in distance.

Next, detailed processing contents until obtaining the element resistance extraction result 16 by the wiring element resistance calculation of FIG. 1 will be described with reference to the flowchart of FIG. Note that FIG.
The same parts as those in FIG. 1 are denoted by the same reference numerals. First,
Using the layer information 12, only necessary data layers are extracted from the layout pattern information 11. An ordinary layout is created by dividing the same wiring layer into different data layers depending on the purpose, or by dividing the same data layer into many polygonal and width-shaped wirings. Therefore, an OR process is performed (step 31), and layouts belonging to the same wiring layer are synthesized.

Next, branch wiring is omitted (step 3).
2). As shown by 41 in FIG. 4A, the wiring belonging to the lowest order, for example, a thin wiring directly connected to each element in the memory cell array is a repetition of a basic block, and a sufficient check is made at the memory cell array design stage. Is performed, it can be determined that it is not necessary to individually check again. The correct connection can be verified with a conventional layout-versus-circuit-verification tool.

In order to reduce the number of calculation objects, the lowermost wiring (lower branch wiring) 41 is excluded, and upper power supply wirings connected to the branch wirings, that is, the middle wiring 42 and the uppermost wiring 43.
Is performed. Normally, the upper wirings 42 and 43 are laid out slightly thicker than the lowermost wiring 41, so that it is sufficient to perform processing for leaving only wiring having a thickness equal to or larger than the reference. Since the data has already been ORed, resizing can be performed. By making the whole thinner once and making it thicker by the same amount, thin wires can be erased and only thick wires can be left. As a result of the branch wiring omitting process in step 32, the wiring has the lowermost wiring 41 omitted as shown in FIG. 4B.

Next, equipotential tracking is performed (step 3).
3). This processing is for tracing along the wiring from the designated pad to take out all the wiring connected to the pad and to remove other data such as internal circuit wiring. Tracking extends to another wiring layer connected through contacts and through holes, in addition to the wiring layer to which the pad belongs.

Subsequently, after inputting the extracted wiring layout pattern (step 34), trapezoidal division processing is performed (step 35). The division is performed by dividing the resistive element figure cut out in the direction perpendicular to the current flowing from the pad to the wiring and the branch figure obtained by cutting out the branch point of the wiring. In a resistive element figure, a part connected to another wiring layer by a contact or a through hole is divided into figures.

Next, a resistance calculation is performed (step 36).
As shown in FIG. 5, when the layer resistance 5-1 on the opposite side of the square of the wiring having a certain thickness is R, the wiring resistance R2 of the rectangular wiring 5-2 having the length L and the width W is R × L / W. The resistance R3 of the parallelogram wiring 5-3 having the height L and the width W is calculated as R × L / W, and the resistance R4 of the trapezoid wiring 5-4 having the bases W1 and W2 is calculated as R × L / (( W1 + W2) / 2)
Is calculated as

Many contacts and through holes are often arranged side by side to reduce resistance. When calculating the resistance, one resistor is used for speeding up the processing. Further, the resistance value is appropriately selected such that a resistance value is set to 1 / the number of contacts of one resistance, a representative value is set, or 0 is set for simplicity.

Subsequently, the obtained resistances at both ends of each resistance element figure and the resistance from the center to the side of each branch figure are stored as element resistance original data 37, and then reduced if necessary to reduce the amount of calculation. (Step 38). FIG. 6A shows an example of a series connection in which resistors are continuous without branching. In this case, a plurality of resistors are combined into one and degenerated to obtain the resistor shown in FIG. 6B. FIG. 6C shows an example of a parallel connection in which a plurality of resistors having no branch exist near the start point and the end point of each other. FIG. As shown in D), the resistance can be unified.

With the above processing, the element resistance extraction result 16 corresponding to the layout is obtained. Compared with the original layout data, the extraction result 16 can be greatly reduced because the branch wiring is removed, only the wiring resistance of interest is extracted, and further degeneration is performed.

When the element resistance extraction result 16 is obtained in this way, in this embodiment, as described with reference to FIG.
Next, a combined resistance is calculated (step 17). FIG. 7 shows an example of calculating the combined resistance using the minimum cumulative resistance value. First, as shown in FIG. 7A, a resistance value between the central nodes is calculated based on the resistance value from the center to the end of each wiring element.

As a result, as shown in FIG. 7B, a resistance value between nodes is calculated. Next, a cumulative resistance value from the pad is obtained. In this case, tracing is performed by the maze method in which the conductance is weighted in order from a node close to the pad, and a point having a larger conductance, that is, a smaller resistance is taken at a point where another path merges. For example, FIG.
In the case of point A shown in (C), the total resistance value of the path from the left in the figure is 48, and the total resistance value of the path from the bottom is 50.
Therefore, the minimum cumulative resistance value is 48. Although this is different from the true resistance value, even large-scale data can be calculated at a high speed, which is very effective for verifying wiring uniformity.

Next, as shown in FIG. 1, ranking of the calculation results is performed (step 19). In this processing, each node is sorted in the order of the combined resistance from the pad, and the range from the pad with the resistance 0 to the node with the maximum resistance is divided into a plurality of ranks. Colors are assigned according to the resistors so that designers can easily determine, for example, assigning blue, green, and yellow in order from the lowest resistance, and setting the node with the largest resistance to red.

Although it is possible to perform the ranking very finely, there is a limit to the number of colors that the designer can judge, so that the setting can be changed as necessary. All colors of resistors with a certain resistance or less are displayed in blue, and only high-resistance parts that are problematic are displayed in different colors. Can be set to indicate whether the low resistance is maintained.

Finally, the calculation result is reflected on the layout,
Display on the screen (step 20). The display is performed for each data layer, wiring such as power supply and ground, and a combination display thereof is also possible.

The display can be enlarged or reduced by an instruction of a pointing device such as a mouse to see an arbitrary area. Usually, since the data amount of the layout exceeds the resolution of the screen, there is a risk that, when drawing arbitrarily, the same pixel is overwritten with another color and the problem part is hidden. In order to prevent this, drawing is performed in order from the portion having the lowest resistance value, so that even when the image is reduced, the portion having the high resistance value can be reliably displayed without being overwritten. Sorting is fast because it is already done at the time of ranking.

When there is a long wiring without branching, the entire wiring is displayed in one color even though the resistance is actually different at both ends, and the color suddenly changes at the connection with the next wiring. A problem such as a large change occurs. When dealing with data including such wiring, the function of displaying gradation between adjacent nodes can be specified by the designer. This enables a step-by-step display close to the actual resistance distribution.

Further, the resistance value, the combined resistance value, and the coordinates of the wiring element specified by the instruction of the designer can be displayed on the screen. In addition, a designer can search and display a range of information included in the database, such as a text name, a coordinate value, and a resistance value range.

Next, a second embodiment of the present invention will be described with reference to the drawings. This second embodiment is similar to the first embodiment in the handling of steps 11 to 16 and steps 18 to 20 in FIG. 1, but is characterized by the combined resistance calculation in step 17.

FIG. 8A shows an example of a layout in which the composite resistance calculation is performed in a mesh from the power supply connection pad 81 to the calculation target node 82. FIG. This layout is the result of the wiring element resistance calculation,
It can be represented by twelve resistors R1 to R12. FIG. 8 (B) defines the above-mentioned wiring element resistance in terms of the node name and the direction of the resistance element. Here, in order to accurately calculate the combined resistance between the node 1 and the node 9, it is necessary to consider all paths. Specifically, a current between nodes is assumed, and a Kirchhoff's current equation KCL for each node and a Kirchhoff's voltage equation KVL for each resistor may be combined and solved. One specific example is shown below.

It is assumed that current I is supplied to pad 81 and current I flows out of node 82 to be calculated. The direction of the resistance element may be arbitrarily determined, but is unified throughout the subsequent calculations. The current flowing in the direction corresponding to the resistance element is represented by plus, and the current flowing in the opposite direction is represented by minus.

Next, the resistance element is divided into a tree (Tree) and a co-tree (CoTree). The tree is shown in Fig. 8 (C)
As shown in (1), it is expressed as a single tree-like connection having a minimum number of branches connecting all nodes, that is, a resistance element. There can be multiple trees, and any may be used. The number of branches constituting the tree is the number of nodes minus one. A resistance element that does not belong to the tree is referred to as a cotree. The cotree is as shown in FIG.

Next, an expression is made at each node from Kirchhoff's current law (KCL).

From the branch current = inflow current−outflow current, branch current−inflow current + outflow current = 0, where current Ix = (1 / Rx) × Vx = GxVx. Here, R: resistance value, V: voltage, G: conductance = 1 / R.

The KCL for the nodes 1 to 9 is as follows.

[0052]

(Equation 1) When the current elements are arranged in the order of a tree and a co-tree, and are represented by a matrix, they can be expressed as shown in Expression 10 in FIG. The expression may be the number of trees, that is, eight, and any expression can be deleted. When the relational expression of I = GV is applied by removing the element of the expression (9) from the expression (10), the expression (11) of FIG. 9 is obtained.

Next, an independent closed circuit is obtained, and a Kirchhoff voltage equation (KVL) is created. Adding one cotree to the tree creates one closed circuit. FIG. 8E shows an example of an independent closed circuit. When one of the co-trees shown in FIG. 8D is added to the tree shown in FIG. 8C, the resistors R1 and R2 shown in FIG.
A closed circuit consisting of R4, R6 and R3 is created.

Taking the counterclockwise direction positive for this closed circuit,
Make KVL. Assuming that the voltages generated at the resistors R1, R4, R6, and R3 are V1, V4, V6, and V3, respectively, V4 = -V1 + V from V1 + V4-V6-V3 = 0.
3 + V6. Similarly, when the respective co-trees are added, the following equation holds when KVL is obtained for a possible closed circuit. In the following, for example, R5〃 indicates that the added cotree is R5.

[0055]

(Equation 2) When the above Vx (where x = 1, 2,..., 12) is represented by a matrix, it is represented by equation (12) in FIG. Further, when this equation (12) is substituted into equation (11), equation (13) in FIG.
Is obtained. When this is arranged, the equation (14) in FIG. 10 is obtained. Equation (14) is a simultaneous equation of eight unknowns and eight equations, and can be solved by applying a sweep-out method (Gauss-Jordan method). For example, when Rx = 1Ω and I = 1A, the result is as shown in Expression (15), and individual element voltages are obtained.

Finally, the respective element voltages from the pad to the node of interest are summed to obtain a combined resistance. Since the combined resistance = the total voltage / current from the pad to the node of interest, if the current is 1 A, the combined resistance R is R = V3 + V8 + V11 + V12 = 1.5 (Ω).

In the second embodiment, since the combined resistance of all the paths included in the processing target data connected from the pad to the node of interest is calculated, the result of the calculation is more accurate than in the first embodiment. Is obtained. Although the amount of calculation increases,
In contrast to the conventional example of calculating the nonlinearity of transistor characteristics,
Since only a linear operation is required, the calculation can be performed at a very high speed in a short time.

[0058]

As described above, according to the present invention,
By extracting only the wiring of interest from the layout data, and by deleting the technique wiring, the data to be processed is reduced, so that the unevenness of the power supply, ground, and other major signal wiring in the layout of the semiconductor integrated circuit is far greater than before. Verification can be performed with less data storage area. Thus, the present invention can be applied to a large-scale integrated circuit such as a 64-Mbit DRAM.

According to the present invention, high-speed processing can be performed without calculating nonlinearity of elements such as transistors by calculating only wiring resistance, and data to be processed is reduced by reducing the resistance. In addition, since the resistance calculation is simplified and the calculation is performed at high speed, the wiring non-uniformity can be verified with much less calculation processing than before, so that a highly reliable layout can be achieved without delay in the design schedule. Will be possible.

Further, according to the present invention, a circuit simulator, which has been conventionally required, is not required, so that many designers can use the circuit simulator simultaneously at a low cost, and the design period can be shortened.

Further, according to the present invention, by drawing in order from a portion having a low resistance value, a problem portion having a high resistance value can be surely displayed without being overwritten. The ability to see arbitrary areas, and the ability to obtain detailed information by displaying long wiring gradations and database information, allow designers to find problems accurately by optimizing the display of the result layout. This makes it possible to perform wiring evenly over the entire area on the chip, prevent operation failure, and achieve a highly reliable layout.

Further, according to the present invention, an independent closed circuit obtained by adding one cotree to a tree is obtained for all the cotrees, and individual elements obtained by establishing Kirchhoff's voltage equation for all the independent closed circuits are obtained. By calculating the combined resistance from the voltage, the combined resistance of all the paths from the pad to the calculation target node can be calculated, so that a highly accurate calculation result can be obtained only by the linear operation. Calculation for layout verification can be performed with high accuracy.

[Brief description of the drawings]

FIG. 1 is a flowchart showing the operation of an embodiment of the present invention.

FIG. 2 is an example of a layout display using the embodiment of FIG. 1;

FIG. 3 is a flowchart showing details up to an element resistance extraction process in FIG. 1;

FIG. 4 is a diagram illustrating a branch wiring omitting process of FIG. 3;

FIG. 5 is a diagram for explaining a resistance calculation method in FIG. 3;

FIG. 6 is a diagram illustrating the wiring resistance degeneration processing of FIG. 3;

FIG. 7 is a diagram for explaining a combined resistance calculation method in FIG. 1;

FIG. 8 is a diagram illustrating a combined resistance calculation method according to the second embodiment of this invention.

FIG. 9 is a diagram illustrating a calculation formula used in a second embodiment of the present invention.

FIG. 10 is a diagram illustrating another calculation formula used in the second embodiment of the present invention.

FIG. 11 is a flowchart showing an example of the related art.

[Explanation of symbols]

2-1-1, 2-2-1 Power supply connection pad 2-1-2, 2-1-3, 2-1-4, 2-1-5, 2
-2-2, 2-2-3, 2-2-4, 2-2-5 Power supply wiring 11 Layout pattern information 12 Layer information 14 Omission and degeneration processing 15 Wiring element resistance calculation processing 16 Element resistance extraction result 17 Composite resistance Calculation processing 18 Calculation result 19 Resistance ranking processing 20 Layout display processing

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50

Claims (5)

(57) [Claims] 1. A wiring element resistance corresponding to a wiring connected to a power supply pad is extracted from the layout pattern information based on layout pattern information and layer information of a semiconductor integrated circuit, and a lowermost wiring is omitted. And branch
Omitting branch wiring that leaves the upper power supply wiring connected to the line
After performing the equipotential tracking after the branch wiring omission processing.
From the calculated wiring layout pattern
Degeneration processing performed on element source resistance data
After sequentially performing before or after the extraction of the wiring element resistance,
A layout verification method comprising calculating a combined resistance value from a pad to each point based on the extracted wiring element resistance, classifying the combined resistance value, and displaying the rank on a layout. 2. The layout verification method according to claim 1, wherein, when calculating the combined resistance, simplification is performed using a minimum cumulative resistance value. 3. The display according to claim 1, wherein the combined resistance values are classified into ranks, and color-coded display corresponding to each rank is performed, and displayed on the layout in ascending order of the combined resistance values. Layout verification method. 4. A tree, which is a minimum tree-like connection connecting all the nodes from a pad to a node to be calculated based on the extracted wiring element resistance when calculating the combined resistance. And a co-tree consisting of element resistances that do not belong to the tree, obtain independent closed circuits obtained by adding one co-tree to the tree for all co-trees, and obtain Kirchhoff's voltage equation for all the independent closed circuits. 2. The layout verification method according to claim 1, wherein the combined resistance is obtained from individual element voltages obtained by setting the following. 5. A process for extracting a wiring element resistance corresponding to a wiring connected to a power supply pad from the layout pattern information based on the layout pattern information and layer information of the semiconductor integrated circuit ; Omitted, upper power supply wiring connected to branch wiring
Performed before or after the omission processing of the branch wiring that leaves
Obtained by performing equipotential tracking after the branch wiring omitting process.
Resulting et a principal from the wiring layout pattern to resist calculations
A reduction process performed on the original resistance data, a process of calculating the combined resistance value to each point from the pad on the basis of the wiring element resistances which the extracted, on the layout after ranking the combined resistance programming La for executing the processing for displaying on a computer
A recording medium recording the beam.