JP3017071B2 - Received signal processing device for array antenna - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a reception signal processing device for an array antenna.

[0002]

2. Description of the Related Art An active phased array antenna capable of easily controlling a main beam direction at a mobile receiving radio station has been researched and developed for various communication systems, especially mobile communication systems. With the advancement of digital signal processing technology, beamforming antennas have been researched and developed as one of array antennas having various functions (for example, Ito et al., "Prototype of DBF antenna", IEICE technical report) , SANE88
-54, January 27, 1989 (hereinafter referred to as Reference 1). ). The beamforming antennas can be classified into two types of antennas depending on whether signal processing is performed in analog or digital.

In a beam forming antenna using analog signal processing, a plurality of phase shifters connected to an array antenna composed of a plurality of antenna elements arranged in parallel are changed to output an analog signal output from each antenna element. By combining at the high frequency circuit stage or the intermediate frequency stage, the main beam direction of the array antenna can be directed to a predetermined direction θk. For example, in the case of an array antenna having a plurality of N antenna elements linearly juxtaposed at equal intervals d, the phase set value φn of each phase shifter
(N = 1, 2,..., N) is represented by the following equation 1.

[0004]

[Formula 1] φn = n · Δφk

## EQU2 ## Here, λ is the wavelength of the received signal.

[0005] Here, the signal output of each antenna element is Sn
Then, the combined output signal SC is expressed by the following equation (3).

(Equation 3)

On the other hand, a beamforming antenna using digital signal processing (hereinafter, referred to as a DBF antenna).
In, a receiver including an A / D converter is connected to each antenna element, and based on an output signal Sn (n = 0, 1, 2,..., N−1) from each A / D converter. The beamforming is performed by executing complex multiplication and addition of the received signal by one digital signal processor (hereinafter, referred to as DSP) using the above equation (3).

[0007] Further, a beam combining method in the DBF antenna is disclosed in the above-mentioned Document 1, and a method using a discrete Fourier transform and a method using a fast Fourier transform are disclosed as the beam combining method.

The beam combining method according to the former method will be described below. A plurality of N antenna elements are linearly x
_1, x _2, ..., are juxtaposed to each position x _N, a received complex signal upon reception of the radio wave radiated from the angle theta as viewed from the array antenna in the i-th antenna element S (theta,
Assuming that i), the beamforming method in the DBF antenna extracts a component from a predetermined angle θk method based on a received signal sampled on a spatial axis. Define the antenna beam as indicating the spatial distribution of the received power,
If the direction of the maximum value is called the main beam direction, that is, the antenna beam B having the main beam direction as θk
k (θ) is S * (θk, i) (i = 0, 1, 2,...,
N-1) can be defined by the following equation 4 as a matched filter signal output Bk (θ) using a reference function.
Here, * represents a complex conjugate.

[0009]

(Equation 4)

At this time, the signal-to-noise power ratio (SNR) of the antenna beam Bk (θ) becomes maximum. Here, the amplitude of the arriving radio wave is A ₀ , the phase is φ ₀ , the amplitude pattern of each antenna element is Ai (θ, i), the phase pattern is φi (θ, i), and the gain of each receiver is A
Assuming ₂ (i), the signal output S (θ, i) of the receiver is expressed by the following equation (5).

[0011]

S (θ, i) = A ₀ A ₁ (θ, i) A ₂ (i) exp [j
{φ ₀ + φ ₁ (θ, i) + φ ₂ (i) + (2πx _i sin
θ) / λ｝]

Therefore, the antenna beam Bk (θ) is expressed by the following equation (6).

(Equation 6)

As is apparent from the above equation 6, since the electric field vector of each element in the θk direction has the same phase, the antenna beam Bk (θ) can maximize the output SNR in the θk direction. The side lobe characteristics are determined by the gain A ₁ (θ, i) of each antenna element and the gain A ₂ (i) (i =
0, 1, 2,..., N−1), and desired characteristics are not always obtained. Therefore, to suppress the side lobes, the weighting factor W
(I) Weighting is performed by multiplying (i = 0, 1, 2,..., N−1). The weighting factor W (i) is generally
For example, it comprises a window function W (i) such as a Hamming function, a Hamming Taylor function, a Dolph Chebyshev function, and a gain correction term of an antenna element and a receiver. It is represented by 7.

[0014]

W (i) = w (i) / [√ {Eθ [| S (θ, i)
│ ² ]}] ・ │S (θk, i) │]

Here, Eθ [] represents an average value of θ. The antenna pattern Bk (θ) at this time is expressed by the following equation 8.

[0016]

(Equation 8)

Further, the following equation 9 can be obtained from the above equation 8.

[0018]

(Equation 9)

As is apparent from the above equation (9), generally, in order to form an antenna beam having an arbitrary angle θk as the main beam direction, the number of antenna elements per beam N
Are required, and N ² complex product-sum operations are required to form N multi-beams.

Next, a description will be given of a case of the latter fast Fourier transform method in which arithmetic processing is simpler. Here, a plurality of N antenna elements of the array antenna are linearly juxtaposed at equal intervals d, and the phase pattern φi (θ, i) (i = 0, 1, 2, 3,..., N −
Assume that 1) is independent of the angle θ of the main beam direction of the array antenna, that is, assume that the phase pattern φi (i) = φi (θ, i) of each antenna element. At this time, if it is assumed that the gain is corrected using the following equation (10) prior to beam formation, the antenna beam Bk (θ)
By combining the signal outputs of each receiver,
It is represented by 1.

[0021]

Sf (θ, i) = S (θ, i) · w (i) /
^{_{[√ {Eθ [A 1 2}} (θ, i)]}] · exp [-j {φ 0 + φ 1
(I) + φ ₂ (i)｝]

[Equation 11]

Here, when the number of multi-beams is matched with the number of antenna elements, the main beam direction θk of each antenna element is set by the following equation (12).

[0023]

## EQU12 ## θk = sin ⁻¹ (λk / Nd), k = −N / 2, −N / 2 + 1,..., 0,.

At this time, the antenna beam Bk (θ) is
By matching the position of the antenna element,
It is represented by

[0025]

(Equation 13) k = -N / 2, ..., 0, ..., N / 2-1

As is apparent from the above equation (13), the antenna beam Bk (θ) has the corrected signal output Sf of the receiver.
It is a discrete Fourier transform of (θ, i), and a fast Fourier transform (hereinafter, referred to as FFT) algorithm can be used. That is, the number of complex product-sum operations required for forming N multi-beams can be reduced to Nlog ₂ N instead of N ² . After the formation of the N multi-beams, for example, a signal having the maximum value among them can be selected and used as a received signal. As an example of a reception signal processing device for a DBF antenna that performs the above-described beam combining, the above document 1 discloses an example using a minicomputer. When the arithmetic processing is executed, even if the latter beam combining method using the FFT operation is used, a large number of arithmetic processings are required, and there is a problem that signal processing is relatively slow. Furthermore, when the number of antenna elements increases, signal processing becomes extremely slow.

[0027]

In a conventional signal processing apparatus, a plurality of boards equipped with a general-purpose digital signal processor are used, and a plurality of digital signals are processed off-line under the control of an external control device. Processing was being performed. As described above, in the conventional example, since the processing is performed by a general-purpose digital signal processor, an external control device that controls each processor is required, and the processing time is relatively long. It could not be reduced in size.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to perform a received signal processing at a higher speed than in the conventional example, to have a simple circuit configuration, and to be suitable for an array antenna. It is to provide a signal processing device.

[0029]

According to a first aspect of the present invention, there is provided a reception signal processing apparatus for an array antenna, wherein each antenna element of the array antenna comprises a plurality of antenna elements arranged in close proximity in a predetermined arrangement shape. In the array antenna reception signal processing device, the reception signal processing device includes a conversion unit (5) for converting a plurality of reception signals respectively received in the above into two orthogonal baseband data orthogonal to each other using a common local oscillation signal. A maximum ratio combining circuit (203) that performs maximum ratio combining and outputs as a standardized received signal based on each of the two orthogonal baseband data converted by the converting means (5); 203) a predetermined reference antenna element based on each of the two orthogonal baseband data converted by the conversion means (5). Calculating a plurality of first data, each of which is a complex conjugate product of the first reception signal received by the first reception signal and the second reception signal received by each antenna element including the reference antenna element. Calculation means (301,
311, 321, 331) and a plurality of second data (304, 314, 324, 324) for calculating a plurality of second data which are products of the respective second received signals and the respective first data.
334) and a third calculating means (306) for calculating third data by adding the plurality of second data.
And fourth operation means (305, 31) for calculating a plurality of fourth data by squaring each of the first data.
5, 325, 335), a fifth calculating means (307) for calculating fifth data by adding the plurality of fourth data, and a value obtained by dividing 1 by the square root of the fifth data. Is calculated by multiplying the sixth data by the third data to calculate the seventh data as a result of the multiplication and outputting the maximum ratio-synthesized and standardized reception signal (308) The maximum ratio combination processing circuit (203) previously stores a table composed of sixth data, which is a value obtained by dividing 1 by the square root of the fifth data, for various fifth data. The first storage means (13
6) and second storage means (161, 16) for temporarily storing the first data output from the accumulator (133).
2) and third storage means (134-1,...) For temporarily storing third data output from the accumulator (133).
134-2) and fourth storage means (13) for temporarily storing the fifth data output from the accumulator (133).
4-3), a first multiplexer (125) for selectively switching and outputting one of the orthogonal baseband data of each of the second received signals, and two of the first received signals. A second multiplexer (12) for selectively switching and outputting one of the orthogonal baseband data;
6), the data output from the first multiplexer (125) and the second storage means (161, 162)
And the third storage means (1
34-1 and 134-2) to selectively switch and output the third data output from the third multiplexer (127), the data output from the second multiplexer (126) and the third multiplexer (127). 2 storage means (161, 1
62) and selectively outputs the sixth data output from the fourth storage means (134-3) via the first storage means (136) from the fourth storage means (134-3). A fourth multiplexer (128) that performs
And a multiplier (131) for multiplying the data output from the multiplexer (127) with the data output from the fourth multiplexer (128), and output from the multiplier (131) at a predetermined timing. A plurality of data are cumulatively added, and the third data or the fifth data as a result of the cumulative addition is respectively stored in the third storage means (134-1, 1, 1).
34-2) or the second storage means (161, 161) without outputting to the fourth storage means (134-3) or accumulating the first data output from the multiplier (131). Cumulative adder (133) for outputting to 162)
And the first arithmetic means (301, 311, 321, 3
31) and the second arithmetic means (304, 314, 32)
4,334) and the fourth arithmetic means (305, 315,
325, 335) and the sixth arithmetic means (308) are executed by the multiplier (131),
The addition processing in the third calculating means (306) and the fifth calculating means (307) is performed by the accumulator (13).
Control means (180) for executing the respective arithmetic processing in a time-division multiplexed manner as described in (3), and controlling the multiplier (131) to output a received signal that is maximum ratio-combined and standardized. ).

Further, the received signal processing device for an array antenna according to the second aspect of the present invention is the received signal processing device for an array antenna according to the first aspect, wherein the maximum ratio combining circuit (2
03) further includes low-pass filtering means (302, 312, 322, 332) for low-pass filtering the first data and outputting the first data.
The maximum ratio combining processing circuit (203) is configured to convert the first data after low-pass filtering by the low-pass filtering means (302, 312, 322, 332) into the second arithmetic means (30).
4, 314, 324, 334) or the fourth arithmetic means (305, 315, 325, 335) to calculate the second data or the fourth data, respectively.

Further, the reception signal processing device for an array antenna according to the third aspect of the present invention is the reception signal processing device for an array antenna according to the first or second aspect, further comprising: A beam selection circuit (201) for selecting a plurality of large predetermined antenna elements and outputting respective channel number data corresponding to each of the selected antenna elements;
Based on the channel number data output from 1),
A phase shift process for shifting the phase of each baseband data of each received signal corresponding to the channel number data to the center of the array antenna to output each baseband signal after the phase shift. A phase circuit (202), and the maximum ratio combining processing circuit includes the phase shift circuit (2).
02), the processing is performed based on a plurality of phase-shifted respective baseband data output from step (02).

Further, the reception signal processing device for an array antenna according to the fourth aspect is the reception signal processing device for an array antenna according to the first, second or third aspect, further comprising: It is determined whether or not each power data of each corresponding received signal is less than a predetermined threshold, and each power data corresponding to each of the plurality of channel number data is less than a predetermined threshold. A comparison circuit (20) that outputs each state data indicating whether
4) a reset circuit for resetting, based on the state data, the first data corresponding to the channel number data for which the power data corresponding to the channel number data is determined to be less than the threshold value to zero. (300).

[0033]

[0034]

[0035]

[0036]

Embodiments of the present invention will be described below with reference to the drawings. <Embodiment> FIG. 1 is a block diagram of an array antenna reception signal processing apparatus according to an embodiment of the present invention.
The reception signal processing device for an array antenna according to this embodiment includes:
Array antennas 16 arranged side by side in a two-dimensional matrix shape having two axes at equal intervals and orthogonal to each other
Quasi-quadrature detection circuit and transversal type FIR (finite impulse response) low-frequency pass filter corresponding to the antenna elements 1-1 to 1-16 (collectively denoted by the reference numeral 1). For performing a circuit operation including a multi-beam combining circuit using a two-dimensional FFT operation
P5-1 to 5-16 and a demodulator 7 are provided, and a beam selection circuit 201, a phase shift circuit 202, and an MRC processing circuit are provided between the 16 DSPs 5-1 to 5-16 and the demodulator 7. 203 and a comparison circuit 204. In this embodiment, the MRC processing circuit 203 outputs two orthogonal phase shift data S _n (n = 0,
1, 2, 3 and the same hereinafter. 2)
MRC processing is performed by executing the following processing based on two orthogonal I-channel data Re (S _n ) and Q-channel data Im (S _n ), and is configured by a digital circuit. . (1) and phase data S ₀ of the reference, the reference of a * complex conjugate product S ₀ · S _n of each phase shift data S _n containing phase data S ₀ (n = 0, 1, 2, 3) Calculate. Here, the complex conjugate product of the complex number A and the complex number B refers to the product of the complex conjugate B * of the complex number A and the complex number B. (2) Each complex conjugate product S ₀ · S _n * is low-pass filtered by an infinite impulse response low-pass filter (hereinafter referred to as IIR low-pass filter) 302, 312, 322, 332. Here, each complex conjugate product F (S ₀
S _n *) are each referred to as a second weighting factor F (a ₀ W _n ). (3) Each second weighting factor F (a ₀ W _n ) and each phase shift data S
_n, and multiply-result data S _n · F (a ₀ W _n ) are cumulatively added and output. Here, the MRC processing refers to a maximum ratio combined signal processing (Maximal Ratio) for making the phases of the inputs in-phase and performing the combining at a rate corresponding to the input power.
Combining).

Next, the configuration of the present embodiment will be described in detail. As shown in FIG. 1, a down converter 2-1, a bandpass filter 3-1, an A / D converter 4-1, and a DSP 5-1 connected in cascade are connected to the antenna element 1-1. , The antenna element 1-2 includes a down converter 2-2 and a band-pass filter 3 connected in cascade with each other.
-2, the A / D converter 4-2, and the DSP 5-2 are connected. Similarly, the same elements are connected to the antenna elements 1-3 to 1-15, and further, the antenna element 1-16 is connected to the antenna elements 1-16. , Downconverters 2-16 connected in cascade with each other
, A band pass filter 3-16, an A / D converter 4-61, and a DSP 5-16. Here, the down converters 2-1 to 2-16 (collectively denoted by reference numeral 2).
Are constituted by the same circuit as each other, and the band-pass filter
1 to 3-16 (collectively denoted by the reference numeral 3) are constituted by circuits similar to each other, and are A / D converters 4-1 to 4-1.
Reference numerals 6 (collectively denoted by reference numeral 4) are composed of circuits similar to each other, and DSPs 5-1 to 5-16 (collectively denoted by reference numeral 5) are operated data and operation methods as described later in detail. , Except that they are different from each other. Therefore, only one representative operation of each circuit will be described.

A high-frequency signal, such as a microwave signal, of a radio wave received by the antenna element 1 is input to a down converter 2, which converts the input high-frequency signal into an intermediate frequency signal having a predetermined intermediate frequency. (Hereinafter, referred to as an IF signal), and passes through a band-pass filter 3 for removing unnecessary harmonic components.
/ D converter 4. The A / D converter 4 performs A / D conversion of the input IF analog signal into an IF digital signal at a sampling frequency of 128 kHz, for example, so that the DSP 5
Output to

Next, the DSP 5 is configured as described later in detail, and performs multi-quadrature detection on the input IF digital signal using quasi-orthogonal detection, transversal FIR low-frequency pass filtering, and two-dimensional FFT operation. An operation including beam combining and a sum of squares operation is performed, and a digital signal of the operation result is output to the phase shift circuit 202. Here, 16 D
As shown in FIG. 3, the SPs 5-1 to 5-16 are connected via data buses 101 to 104 wired in the X-axis direction and data buses 105 to 108 wired in the Y-axis direction orthogonal to the Y-axis direction. Connected in a grid shape. Data bus 1
01 is connected to the DSPs 5-1 to 5-4, the data bus 102 is connected to the DSPs 5-5 to 5-8, the data bus 103 is connected to the DSPs 5-9 to 5-12, and the data bus 104 is the DSP 5-13. To 5-16. On the other hand, the data bus 105 is a
5-9 and 5-13, and the data bus 106 is connected to the DS
P5-2, 5-6, 5-10, 5-14, and the data bus 107 is connected to the DSPs 5-3, 5-7, 5-11, 5
-15, and the data bus 108 is connected to the DSP 5-4,
5-8, 5-12, and 5-16.

FIG. 2 shows the DSPs 5-1 to 5-16 of FIG.
FIG. 4 is a block diagram showing the function of (1). As shown in FIG.
The IF digital signal input from the / D converter 4 is converted into I channels (I
ch) and the Q channel (Qch) are distributed to two IF digital signals synchronized with each other. On the other hand, the local oscillator 20 generates a local oscillation digital signal having a predetermined local oscillation frequency of, for example, 32 kHz,
The signal is output to the multiplier 12 as a first local oscillation digital signal, and is also output to the multiplier 22 via the π / 2 phase shifter 21 for shifting the phase of the input digital signal by π / 2. Therefore, the multiplier 22 supplies the local oscillation digital signal with π
The local oscillation digital signal shifted by / 2 is input as a second local oscillation digital signal. Here, the local oscillator 20 and the π / 2 phase shifter 21 correspond to each of the DSPs 5-1 to 5-1.
6 is provided, but only one is provided in the device.

The I-channel IF digital signal output from the synchronous distributor 11 is multiplied by the first local oscillation digital signal by the multiplier 12, and the digital signal resulting from the multiplication is equal to or higher than the Nyquist frequency of 16 kHz, for example. Transversal FI to eliminate unnecessary waves
The signal is input to a sum-of-squares circuit 15 via an FIR low-pass filter 13 that performs an R-type low-pass filtering process and a fast Fourier transformer 14 that performs an FFT operation for the multibeam combining. On the other hand, the IF digital signal for Q channel output from the synchronous distributor 11 is
2 is multiplied by the second local oscillation digital signal, and the digital signal obtained as a result of the multiplication is a FIR low-pass filter that performs a low-pass filtering process of a transversal FIR system in order to remove an unnecessary wave having a frequency equal to or higher than the Nyquist frequency. The signal is input to the sum-of-squares circuit 15 via a band-pass filter 23 and a fast Fourier transformer 24 that performs an FFT operation for the multi-beam synthesis. The transversal FI
The R low-pass filters 13 and 23 are constituted by, for example, 50% roll-off filters. The square-sum circuit 15 squares the digital signals input from the fast Fourier transformers 14 and 24, and then calculates the sum of the digital signals, that is, executes the sum-of-squares operation to execute a power data digital signal representing a signal power level. And outputs it to the beam selection circuit 201.

Although not shown in FIG. 2, the I-channel spatial data digital signal output from the fast Fourier transformer 14 and the Q-channel spatial data digital signal output from the fast Fourier transformer 24 are combined. Are output to the phase shift circuit 202 for phase shift processing.

FIG. 4 shows the DSPs 5-1 to 5-16 of FIG.
FIG. 3 is a block diagram showing the circuit of FIG. As shown in FIG.
The IF digital signal output from the / D converter 4 is temporarily stored in the input register 31 and then input to the A input terminal of the input multiplexer 34. An I-channel FIFO (First-In First-Out) memory 61a or a Q-channel FIFO (First-In Fir
(st-Out) The digital signal after quasi-orthogonal detection read from the memory 61b is input to the B input terminal of the input multiplexer 34 via the FIR output register 62.

The data lines B1 and B2 are connected to the data buses 101 to 1 in the X-axis direction as shown in FIG.
The data lines B3 and B4 are connected to any one of the data buses 105 to 108 in the Y-axis direction according to each DSP, as shown in FIG. Connected. The four data lines B1 to B4 are connected to the A input terminal, the B input terminal, the C input terminal, and the D input terminal of the FFT multiplexer 64, respectively. The digital signal selected by the FFT multiplexer 64 is input to the C input terminal of the input multiplexer 34 via the FFT output register 65. The spatial data digital signal output from the two dividers 56a or 56b, which will be described in detail later, is input to the D input terminal of the input multiplexer 34 and the C input terminal of the data multiplexer 35 via the spatial data output register 63.

Further, a ROM (not shown) which is provided in a controller (not shown) which is constituted by the MPU and executes the control of the whole received signal processing apparatus, stores FIR data for FIR low-pass filtering. Not shown,
It is called FIRROM. ) Is input to the A input terminal of the data multiplexer 35. The FFT weight data digital signal output from the FFT weight ROM 33 that stores the data of the FFT weighting coefficients is input to the B input terminal of the data multiplexer 35. Further, a weight data digital signal output from the beam forming weight ROM 32 for storing weighting coefficients for two-dimensional multi-beam forming is input to the D input terminal of the data multiplexer 35.

The digital signal selected by the input multiplexer 34 is applied to the multiplexer and accumulator 3.
6, the data multiplexer 35
Is input to the B input terminal of the multiplexer and accumulator 36. The multiplexer and accumulator 36 is composed of a multiplexer and an accumulator, multiplies the digital signal input to its A input terminal by the digital signal input to its B input terminal, and then, through a register 37, Output to the accumulator-in terminal of the accumulator 36 and the following registers 51a, 51b, 52a, 52b, 53a, 53b, 5
Output to input terminals 4a, 54b, 55. Here, the digital signal input to the accumulator-in terminal of the multiplexer and accumulator 36 is cumulatively added by the accumulator in the multiplexer and accumulator 36, and the accumulator is output once for each FIR low-pass filtering process. Is reset after the data is read out at the end of each FFT operation and every operation of the square-sum circuit 15. The multiplexer and the accumulator 36 may use a circuit in which the multiplexer and the accumulator are integrated, or may use a circuit in which the multiplexer and the accumulator are configured as separate circuits.

(A) Post-detection register 51a: The digital signal after the quasi-orthogonal detection of the I channel is temporarily stored and then stored in the FIFO memory 61a. (B) Post-detection register 51b: The digital signal after the quasi-orthogonal detection of the Q channel is temporarily stored and then stored in the FIFO memory 61b. (C) FIR register 52a: After temporarily storing the digital signal after the FIR low-pass filtering of the I channel, outputs the digital signal to the data line B1. (D) FIR register 52b: After temporarily storing the digital signal after the FIR low-pass filtering of the Q channel, outputs the digital signal to the data line B2. (E) FFT primary register 53a: After temporarily storing a digital signal of a calculation result of a first FFT calculation of a real part described in detail later, outputs the digital signal to a data line B3. (F) FFT primary register 53b: temporarily stores a digital signal of a result of the first FFT operation of an imaginary part described later, and outputs the digital signal to the data line B4. (G) Spatial data register 54a: After temporarily storing a spatial data digital signal which is the result of the second FFT operation of the real part described in detail later, spatial data output register 63 and phase shifter via distributor 56a. Output to the circuit 202. (H) Spatial data register 54b: After temporarily storing a spatial data digital signal, which is the result of the second FFT operation of the imaginary part described later, the spatial data output register 63 and the phase shifter via the distributor 56b. Output to the circuit 202. (I) Power data register 55: The power data register 55 temporarily stores the power data digital signal output from the sum-of-squares circuit 15, and then outputs the digital signal to the beam selection circuit 201 and the comparison circuit 204.

The registers 51a, 51b, 52
A 3-state buffer amplifier is provided at the last stage of a, 52b, 53a, 53b. This is because registers 51a and 5
Regarding 1b, when reading data from the FIFO memories 61a and 61b, the three-stage buffer amplifier at the last stage is set to the open state, and the data line B from another DSP is set.
This is to bring the three-stage buffer amplifier at the final stage into an open state when outputting data to 1 to B4.

Next, a two-dimensional fast Fourier transform method used in this embodiment will be described below. This is an extension of the one-dimensional fast Fourier transform method described in the background section. Here, as described above,
A plurality of N (N = 16 in this embodiment) antenna elements 1 of the array antenna are juxtaposed in a two-dimensional matrix at equal intervals d, and the input signal of each antenna element is Skm (θ) (k = 0, 1, ..., N-1; m = 0, 1,
.., N−1), the result of the first-dimensional Fourier transform is expressed as in Expression 14. Here, k is a coordinate in the first-dimensional Fourier transform, and m is a coordinate in the second-dimensional Fourier transform. Synthetic beam output Bkm (k = 0,
1,..., N−1; m = 0, 1,..., N−1) are the results of the Fourier transform in the second dimension. Is done.

[0050]

[Equation 14] k = 0,1,2,3, ..., N-1; m = 0,1,2,2
3, ..., N-1

[0051]

(Equation 15) k = 0,1,2,3, ..., N-1; m = 0,1,2,2
3, ..., N-1

Here, the relationship between the direction θkm of the multi-beam and the beam obtained by the Fourier transform is expressed by the following equation (16). In Equation 16, the multi-beam direction θkm is expressed in the form of (x, y), where x is an angle with respect to the Z axis in the XZ plane, and y is with respect to the Z axis in the YZ plane. Angle.

[0053]

Equation 16 θkm = (sin ⁻¹ {sin (−2π · k / N)}, si
n ⁻¹ {sin (−2π · m / N)}) k = 0, 1, 2, 3,..., N−1; m = 0, 1, 2,
3, ..., N-1

As is apparent from the above equations (14) and (15), the antenna beam Bkm is equal to the signal output Skm of the receiver.
, The FFT algorithm can be used. That is, the number of complex operations required for N multi-beam forming can be reduced to Nlog ₂ N times instead of N ² times. After the N multi-beam forming, for example, by selecting the signal of the maximum value among these,
It can be used as a received signal. Note that the antenna beam Bkm of Expression 15 corresponds to the signals of the spatial data registers 54a and 54b in FIG. 4 of the present embodiment.

FIGS. 5 to 9 are first timing charts showing the operation of each of the DSPs 5-1 to 5-16 in FIG. 1. First, the operation of the DSP 5-1 will be described with reference to the timing charts. In the timing chart, “state” is a serial number given for the sake of convenience according to the clock, “function” is a processing function executed by the DSP, and “input MUX” is an input selected by the input multiplexer 34. "DATA MUX" indicates an input terminal selected by the data multiplexer 35, and "FFTMUX" indicates an input terminal selected by the FFT multiplexer 64. Here, “X” represents indefinite. Further, “output enable” indicates a register whose output is enabled, and “input latch trigger” indicates a register whose input is latched. The switching signals of the input terminals of the input multiplexer 34, the data multiplexer 35, and the FFT multiplexer 64 are shown in FIG.
The output enable signal to each register and the input latch trigger signal shown in FIG. 1 are generated by the controller (not shown) or a timing signal generation circuit (not shown) controlled by the controller.

As shown in FIG. 5, in state 1,
The input multiplexer 34 is switched to the A input terminal, and the data multiplexer 35 is switched to the D input terminal. At this time, the reception data signal output from the A / D converter 4-1 is input to the A input terminal of the multiplexer and accumulator 36 via the A input terminal of the input register 31 and the input multiplexer 34, while the beam forming is performed. A digital signal read from the weight ROM 32 is supplied to a multiplexer / accumulator 36 via a D input terminal of a data multiplexer 35.
Is input to the B input terminal. Then, the multiplexer and accumulator 36 multiplies the two input digital signals to make all IF digital signals in-phase,
That is, every time sampling is performed, the phases φij of all IF digital signals are 0 °, 90 °, 180 °, and 270 °.
And performs a process for generating an IF digital signal after quasi-orthogonal detection. Then, at the end of state 1, the input latch trigger signal to the post-detection register 51a rises, and the data digital signal of the multiplication result is stored in the post-detection register 51a via the register 37 and then stored in the FIFO memory 61a. Note that the F
The I / O memory 61a stores nine quasi-orthogonal detected I-channel data digital signals up to nine clocks before the present time for the next process of transversal FIR low-pass filtering. .

Next, in states 2 to 10,
Transversal FIR low-pass filtering is performed. First, in state 2, the input multiplexer 34 is switched to the B input terminal, and the data multiplexer 35 is switched to the A input terminal. At this time, the I-channel data digital signal read from the FIFO memory 61a after the quasi-orthogonal detection 9 clocks before the present time is supplied to the multiplexer and accumulator 36 via the FIR output register 62 and the B input terminal of the input multiplexer 34. Input to the A input terminal. on the other hand,
The FIR data digital signal read from the FIRROM is input to the multiplexer and accumulator 36 through the A input terminal of the data multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. Since the accumulator has been reset immediately before this, the data digital signal of the multiplication result is added to 0 to add Store it in the accumulator.

Next, in state 3, similarly to state 2, the input multiplexer 34 is switched to the B input terminal, and the data multiplexer 35 is switched to A.
Switch to input terminal. At this time, the data digital signal of the I channel read from the FIFO memory 61a after the quasi-orthogonal detection eight clocks before the present time is the FIR
The signal is input to the A input terminal of the multiplexer / accumulator 36 via the output register 62 and the B input terminal of the input multiplexer 34. On the other hand, the FIR data digital signal read from the FIRROM is input to the multiplexer and the input terminal B of the accumulator 36 via the input terminal A of the data multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. Thereby, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the input data digital signal of the multiplication result is in the state 2
Is added to the data digital signal resulting from the multiplication, and is stored in the accumulator.

Similarly, in states 4 to 10, F
A process for IR low-pass filtering is executed, and as shown in FIG.
a, the I-channel data digital signal after the quasi-orthogonal detection stored in the register 51a in the state 9 at this timing.
The data is written to the O memory 61a. Further, as shown in FIG.
FIR which is the result of the final product-sum operation of low-pass filtering
The data digital signal of the I channel after the low-pass filtering is input from the multiplexer and accumulator 36 to the FIR register 52a via the register 37, and is temporarily stored.

Further, in states 11 to 20,
As in the above states 1 to 10, the Q channel IF
Quasi-quadrature detection and FIR low-pass filtering are performed on the digital received signal. Then, as shown in FIG.
At this timing, the data digital signal of the Q channel after the quasi-quadrature detection stored in the register 51b in the state 19 at this timing is
The data is written to the O memory 61b. Further, as shown in FIG.
Since the output enable signal to 2a and 52b rises, the FI stored in the registers 52a and 52b respectively.
The data digital signals of the I channel and the Q channel after the R low-pass filtering are input to the A input terminal and the B input terminal of the FFT multiplexer 64 via the data lines B1 and B2, respectively. Here, from the middle timing of the state 20 to the middle timing of the state 21, as shown in FIG. 7, the FFT multiplexer 64 selects the A input terminal, so the FIR low-pass filtering The data digital signal of the subsequent I channel is FF
The signal is input to the C input terminal of the input multiplexer 34 via the T multiplexer 64 and the FFT output register 65.

Next, a first FFT operation including four product-sum operations from states 21 to 24 is executed, and a second FFT operation including four product-sum operations from states 25 to 28 is executed. The first and second FFT operations are shown in Tables 1 to 4 below.

[0062]

[Table 1]

[0063]

[Table 2]

[0064]

[Table 3]

[0065]

[Table 4]

In Table 1, "original data DR" is a data digital signal after FIR low-pass filtering stored in the FIR register 52a or 52b in the arithmetic DSP in the right column, that is, for example, FIR of DSP5-1
The register 52a stores the original data I (0) of the I channel and the FIR register 5 of the DSP 5-1.
2b stores the original data Q (0) of the Q channel,
The FIR register 52a of the DSP 5-2 stores the original data I (1) of the I channel,
2 FIR register 52b stores the original data Q (1) of the Q channel.
The same applies to “Data X” is data for the first FFT operation, and is the original data DR.
The data X is stored in the register 52a or 5 of the same DSP.
2b is input to the A input terminal or the B input terminal of the FFT multiplexer 64 via the data line B1 or B2, or the data buses 101 to 1 are input from another DSP.
08 via one of the data lines B1 or B2.
The data is input to the A input terminal or the B input terminal of the FT multiplexer 64 and then input to the C input terminal of the input multiplexer 34 via the FFT output register 65. The “multiplication coefficient Wx” is a multiplication coefficient for the first FFT operation, and is data read from the FFT weight ROM 33 and input to the B input terminal of the data multiplexer 35. The “result data D1” is data of a result of a so-called product-sum operation obtained by repeating a product operation of the data X and the multiplication coefficient Wx four times and taking the sum thereof, that is, result data of the first FFT operation. . For example, in the calculation example of the top four stages in Table 1 (hereinafter referred to as the first calculation example), I (0) × 1, I (1) × 1, and I (0) × 1
Four times the product of (2) × 1 and I (3) × 1 are executed,
The sum of these four products becomes I '(0), and the data D1 is stored in the FFT primary register 53a or 53b, and is used for a second FFT operation described below. The first FFT operation is similarly performed as shown in Tables 1 to 4 below.

"Data Y" is data for the second FFT operation, and is the register 53a or 53
b, and, if necessary, the FFT multiplexer 64 of the same DSP via the data line B3 or B4.
Is input to the C input terminal or D input terminal of the FFT multiplexer 64 of another DSP via the data line B3 or B4,
Thereafter, the signal is input to the C input terminal of the input multiplexer 34 via the FFT output register 65. "Multiplication coefficient W
y "is a multiplication coefficient for the second FFT operation,
The data is read from the FT weight ROM 33 and then input to the B input terminal of the data multiplexer 35. "Result data D2" is obtained by multiplying data Y by multiplication coefficient Wy.
, Which is the result of a so-called product-sum operation, ie, the second FFT
This is the result data of the operation. For example, in the first calculation example shown in the top four rows of Table 1, I ′ (0) × 1 and I ′ (1)
Four times the product of × 1, I ′ (2) × 1, and I ′ (3) × 1 are executed, and the sum of these four products becomes I ″ (0). The second FFT operation is performed in a similar manner. After the result data D2 is stored in the spatial data register 54a or 54b, it is used in a process corresponding to the next function of the square sum circuit 15.

The first FFT operation is an FFT operation in the horizontal direction (X-axis direction) in FIG. 3, and the second FFT operation is an FFT operation in the vertical direction (Y-axis direction) in FIG. Note that F shown in Tables 1 to 4
The FT operation is performed by the following equation 1 corresponding to the above equations 14 and 15.
7 and Expression 18.

[0069]

[Equation 17] k = 0,1,2,3

(Equation 18) m = 0,1,2,3

Here, the number of antenna elements in the X-axis direction and
Since the number of antenna elements in the Y-axis direction is four, N in Equations 14 and 15 is 4, and as is clear from Equations 17 and 18, the left half of the FFT operation shown in Tables 1 to 4 Indicates that the FFT is for the left-right direction (X-axis direction) and the right half is for the up-down direction (Y-axis direction).

The FFT1 to FFT4 in FIG.
First FFT for channel IF digital receive signal
In operation 24, I-channel result data D1 is calculated in state 24, FFT5 to FF8 are first FFT operations for a Q-channel IF digital reception signal, and Q-channel result data D1 is calculated in state 28. Is done. Also, FFT9 to FF12 in FIG.
Is the second FFT operation for the I-channel IF digital reception signal, and the I-channel result data D2 is calculated in state 29, and the FFT13 to FFT16 are
Second FF for Q-channel IF digital reception signal
In the state 36, the result data D2 of the Q channel is calculated. 7 and 8 show DSP5-
1 is a timing chart, so that I-channel FFT processing and Q-channel FFT processing can be distinguished, but other DSPs cannot be distinguished as shown in Tables 1 to 4.

The operation of the DSP 5-1 will be described with reference to FIG. 7. In the state 21, the input multiplexer 34 is switched to the C input terminal, while the data multiplexer 35 is switched to the B input terminal. At this time, the data X is transmitted from the FFT multiplexer 64 to F
C of the FT output register 65 and the input multiplexer 34
Multiplexer and accumulator 3 via input terminal
6 is input to the A input terminal while the FFT weight R
The data digital signal of the multiplication coefficient Wx read from the OM 33 is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35. The multiplexer and accumulator 36 multiplies the two input digital signals,
The signal is output to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. Since the accumulator has been reset immediately before this, the data digital signal of the multiplication result is added to 0 to add Store it in the accumulator. The calculation of FFT1 in the state 21 is a calculation of I (0) × 1 in the first calculation example.

Next, in the state 22, similarly to the state 21, the input multiplexer 34 is switched to the C input terminal and the data multiplexer 35 is switched.
Is switched to the B input terminal. At this time, the data X is input from the FFT multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, while being read from the FFT weight ROM 33. The data digital signal of the multiplication coefficient Wx is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35.
Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. Thereby, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the input data digital signal of the multiplication result is
The result of the multiplication in the state 21 is added to the data digital signal and stored in the accumulator.
The calculation of FFT2 in the state 21 is a calculation of I (1) × 1 + I (0) in the first calculation example.

In the same manner, the processing for the first FFT operation is executed in states 23 and 24. here,
The calculation of FFT3 in state 23 is the calculation of I (2) × 1 + I (1) + I (0) in the first calculation example, and the calculation of FFT3 in state 24 is I (3) in the first calculation example. × 1 + I (2) + I (1) + I
(0) = I ′ (0), and the calculation result of the state 24 is the result data D1 in Tables 1 to 4.

Then, as shown in FIG.
The input latch trigger signal to the register 53a rises at the timing of the end of the operation, so that the data digital signal of the result data D1, which is the result of the first FFT operation, is transmitted from the multiplexer and accumulator 36 to the register 37.
Is input to the FFT primary register 53a and temporarily stored. Further, at the intermediate timing of the state 24 before this operation, as shown in FIG.
a, the output enable signal to 52b rises,
The data digital signals of the I channel and the Q channel after the FIR low-pass filtering stored in the registers 52a and 52b, respectively, are transmitted through the data lines B1 and B2, respectively.
The signal is input to the A input terminal and the B input terminal of the FT multiplexer 64. Here, from the middle timing of the state 24 to the middle timing of the state 21, as shown in FIG. 7, the FFT multiplexer 64 selects the B input terminal, so that the FIR low-pass filtering output to the data line B2 is performed. The subsequent Q channel data digital signal is input to the C input terminal of the input multiplexer 34 via the FFT multiplexer 64 and the FFT output register 65.

Further, in the state 25, the input multiplexer 34 is switched to the C input terminal, while
The data multiplexer 35 is switched to the B input terminal. At this time, the data X is, as described above, FFT
While input from the multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, the data digital signal of the multiplication coefficient Wx read from the FFT weight ROM 33 is The signal is input to the B input terminal of the multiplexer / accumulator 36 via the B input terminal of the multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals by way of a register 37, and the accumulator and the accumulator of the multiplexer and accumulator 36
Output to IN terminal. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. Since the accumulator has been reset immediately before this, the data digital signal of the multiplication result is added to 0 to add Store it in the accumulator. FF in the state 25
The calculation of T5 is a calculation of Q (0) × 1 in the first calculation example.

Next, in the state 26, similarly to the state 25, the input multiplexer 34 is switched to the C input terminal and the data multiplexer 35 is switched.
Is switched to the B input terminal. At this time, the data X is input from the FFT multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, while being read from the FFT weight ROM 33. The data digital signal of the multiplication coefficient Wx is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35.
Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. Thereby, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the input data digital signal of the multiplication result is
The result of the multiplication in the state 25 is added to the data digital signal and stored in the accumulator.
The calculation of the FFT 6 in the state 26 is a calculation of Q (1) × 1 + Q (0) in the first calculation example.

In the same manner, the processing for the first FFT operation is executed in states 27 and 28. here,
The calculation of the FFT 7 in the state 27 is the calculation of Q (2) × 1 + Q (1) + Q (0) in the first calculation example, and the calculation of the FFT 8 in the state 28 is Q (3) in the first calculation example. × 1 + Q (2) + Q (1) + Q
(0) = Q ′ (0), and the calculation result of the state 28 is the result data D1 in Tables 1 to 4.

Then, as shown in FIG.
At the timing of the end, the input touch trigger signal to the register 53b rises, so that the data digital signal of the result data D1, which is the result of the first FFT operation, is transmitted from the multiplexer and accumulator 36 to the register 37.
Is input to the FFT primary register 53a and temporarily stored. Further, at a timing intermediate to the state 27 before this operation, as shown in FIG.
a, the output enable signal to 53b rises,
The first F stored in the registers 53a and 53b, respectively.
The two data digital signals after the FT operation are respectively supplied to the CFT of the FFT multiplexer 64 via the data lines B3 and B4.
Input to the input terminal and the B input terminal. Here, from the middle timing of the state 28 to the middle timing of the state 29, as shown in FIG. 7, since the FFT multiplexer 64 selects the C input terminal, after the first FFT operation output to the data line B3, The data digital signal of
The signal is input to the C input terminal of the input multiplexer 34 via the FFT multiplexer 64 and the FFT output register 65 for the next second FFT operation.

Next, in state 29 of FIG.
The input multiplexer 34 is switched to the C input terminal, while the data multiplexer 35 is switched to the B input terminal. At this time, the data Y is input from the FFT multiplexer 64 via the FFT output register 65 and the C input terminal of the input multiplexer 34 to the A input terminal of the multiplexer and accumulator 36,
Multiplication coefficient W read from FT weight ROM 33
The data digital signal of y is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. Since the accumulator has been reset immediately before this, the data digital signal of the multiplication result is added to 0 to add Store it in the accumulator. The calculation of the FFT 9 in the state 29 is a calculation of I ′ (0) × 1 in the first calculation example.

Next, in state 30, similarly to state 29, the input multiplexer 34 is switched to the C input terminal and the data multiplexer 35 is switched.
Is switched to the B input terminal. At this time, the data Y is input from the FFT multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, while being read from the FFT weight ROM 33. A data digital signal of the multiplication coefficient Wy is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35.
Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. Thereby, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the input data digital signal of the multiplication result is
The result of the multiplication in the state 29 is added to the data digital signal and stored in the accumulator.
The calculation of the FFT 10 in the state 30 is a calculation of I ′ (4) × 1 + I ′ (0) in the first calculation example.

In the same manner, the processing for the second FFT operation is executed in states 31 and 32. here,
In the first calculation example, the calculation of the FFT 11 in the state 31 is I ′ (8) × 1 + I ′ (4) + I ′ (0), and the calculation of the FFT 12 in the state 32 is
In the first calculation example, I ′ (12) + I ′ (8) + I ′
(4) + I ′ (0) calculation, and the calculation result of the state 32 is the result data D2 in Tables 1 to 4.

Then, as shown in FIG.
At the end of the operation, the input latch trigger signal to the register 54a rises, and the data digital signal of the result data D2, which is the result of the second FFT operation, is transmitted from the multiplexer and accumulator 36 to the register 37.
And is temporarily stored in the spatial data register 54a. Further, at the middle timing of the state 32 before this operation, as shown in FIG.
a, the output enable signal to 53b rises,
The first F stored in the registers 53a and 53b, respectively.
The two data digital signals after the FT operation are respectively supplied to the CFT of the FFT multiplexer 64 via the data lines B3 and B4.
It is input to the input terminal and the D input terminal. Here, from the middle timing of the state 32 to the middle timing of the state 33, as shown in FIG. 8, the FFT multiplexer 64 selects the D input terminal, so that after the first FFT operation output to the data line B4, The data digital signal of
FFT multiplexer 64 and FFT output register 65
Is input to the C input terminal of the input multiplexer 34 via the.

Further, in the state 33, the input multiplexer 34 is switched to the C input terminal, while
The data multiplexer 35 is switched to the B input terminal. At this time, the data Y is, as described above, FFT
While input from the multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, the data digital signal of the multiplication coefficient Wy read from the FFT weight ROM 33 is The signal is input to the B input terminal of the multiplexer / accumulator 36 via the B input terminal of the multiplexer 35. Then, the multiplexer and accumulator 36 multiplies the two input digital signals by way of a register 37, and the accumulator and the accumulator of the multiplexer and accumulator 36
Output to IN terminal. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. Since the accumulator has been reset immediately before this, the data digital signal of the multiplication result is added to 0 to add Store it in the accumulator. FF in the state 33
The calculation of T13 is a calculation of Q ′ (0) × 1 in the first calculation example.

Next, in the state 34, similarly to the state 33, the input multiplexer 34 is switched to the C input terminal and the data multiplexer 35 is switched.
Is switched to the B input terminal. At this time, the data Y is input from the FFT multiplexer 64 to the A input terminal of the multiplexer and accumulator 36 via the FFT output register 65 and the C input terminal of the input multiplexer 34, while being read from the FFT weight ROM 33. A data digital signal of the multiplication coefficient Wy is input to the B input terminal of the multiplexer and accumulator 36 via the B input terminal of the data multiplexer 35.
Then, the multiplexer and accumulator 36 multiplies the two input digital signals and outputs the result to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. Thereby, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the input data digital signal of the multiplication result is
The result of the multiplication in the state 33 is added to the data digital signal and stored in the accumulator.
In the first calculation example, the calculation of the FFT 14 in the state 34 is a calculation of Q ′ (4) × 1 + Q ′ (0).

In the same manner, in the states 35 and 36, processing for the second FFT operation is executed. here,
The calculation of the FFT 15 in the state 35 is the calculation of Q ′ (8) × 1 + Q ′ (4) + Q ′ (0) in the first calculation example, and the calculation of the FFT 16 in the state 36 is
In the first calculation example, Q ′ (12) × 1 + Q ′ (8) +
This is the calculation of Q ′ (4) + Q ′ (0) = Q ″ (0), and the calculation result of the state 36 is the result data D2 in Tables 1 to 4.

Then, as shown in FIG.
, The input latch trigger signal to the register 54b rises, and the data digital signal of the result data D2, which is the result of the second FFT operation, is transmitted from the multiplexer and accumulator 36 to the register 37.
And is temporarily stored in the spatial data register 54b. As shown in FIG. 8, at the timing intermediate to the state 367 before this operation, the register 54
Since the output enable signal to the signal a rises, the data digital signal of the spatial data after the second FFT operation stored in the register 54a is supplied to the divider 56a and the spatial data output signal for the next processing of the square sum circuit 15. The data is input to the D input terminal of the input multiplexer 34 and the C input terminal of the data multiplexer 35 via the register 63.

Next, in the state 37 of FIG. 9, the process of squaring the spatial data stored in the register 54a is executed, and in the state 38, the process of squaring the spatial data stored in the register 54b is executed. , A process of calculating power data proportional to the power amount (hereinafter referred to as power data) by adding the two squared data is executed.

That is, as shown in FIG.
At 7, the input multiplexer 34 is switched to the D input terminal and the data multiplexer 35 is switched to the C input terminal. At this time, the data digital signal of the spatial data is input to the input multiplexer 34 via the distributor 56a and the spatial data output register 63.
And the C input terminal of the data multiplexer 35, and the data digital signal of the same spatial data is input to both input terminals of the multiplexer and the accumulator 36, so that the multiplexer and the accumulator 36 Are multiplied by the data digital signal of the two spatial data, and output to the accumulator-in terminal of the multiplexer and accumulator 36 via the register 37. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, since the input data digital signal of the multiplication result is reset immediately before this operation, The resulting data digital signal is added to zero and stored in the accumulator. The calculation of the square of the spatial data in the state 37 is the calculation of the square of I ″ (0) in the first calculation example. Since the output enable signal to the register 54b rises at an intermediate timing of the state 37, the data digital signal of the spatial data after the second FFT operation stored in the register 54b is processed by the next square sum circuit 15 Therefore, the signal is input to the D input terminal of the input multiplexer 34 and the C input terminal of the data multiplexer 35 via the distributor 56b and the spatial data output register 63.

Next, as shown in FIG.
, The input multiplexer 34 is switched to the D input terminal and the data multiplexer 35
Switch to input terminal. At this time, the data digital signal of the spatial data is input to the D input terminal of the input multiplexer 34 and the C input terminal of the data multiplexer 35 via the distributor 56a and the spatial data output register 63, and the same spatial Since the data digital signal of data is input to both input terminals of the multiplexer and accumulator 36, the multiplexer and accumulator 36 multiplies the input data digital signal of the same two spatial data by the register 37, and And the accumulator 36 of the accumulator 36
Output to IN terminal. As a result, the data digital signal of the multiplication result is input to the accumulator in the multiplexer and accumulator 36. At this time, the input data digital signal of the multiplication result is in the state 37.
The data digital signal of the multiplication result is added to the squared data of the spatial data calculated in step (1), and is output to the power data register 55 via the register 37. The calculation of the square of the spatial data in the state 38 is a calculation of the square of Q ″ (0) in the first calculation example. Since the input latch trigger rises at the timing of the end of the state 38, the data digital signal of the operation result of the state 38 output from the register 37 is stored in the power data register 55. It should be noted that, from the intermediate timing of the state 38 before this operation, the next state 3
Since the output enable signal of the register 55 rises by the intermediate timing of No. 9, the power data stored in the register 55, that is, the data digital signal of the operation result of the square sum circuit 15 is output to the beam selection circuit 201. The state 40 is provided for buffering the next operation cycle.

The above-described state 1 to state 40
Up to the DSP 5-1 and the other DSP 5-2
5 to 16 execute the same processing as in the states 1 to 40 shown in Tables 1 to 4. This allows 16 power data to be calculated,
The 16 power data are output to the beam selection circuit 201.

FIG. 10 is a block diagram showing the beam selection circuit 201 of FIG. As shown in FIG. 10, the beam selection circuit 201 includes eight first-stage comparators 210-1 to 210-8 and four second-stage comparators 211-1 to 211-1.
11-4 and two third-stage comparators 212-1 through 21-21
2-2, and one fourth-stage comparator 213, which compares the input power data of the two channels to detect a channel having larger power data, and Outputs large power data and its channel number data. DSP5-1 for multi-beam processing
The power data and the channel number data 1 to 16 respectively output from the comparators 210 to 5-16 are input to the comparators 210-1 to 210-8 such that two sets of data are input to one comparator. You. The processing of the comparator is shown in FIG.
By sequentially performing the operations as shown by 0, the maximum power data and the channel number data of the 16 channels are obtained. The beam selection circuit 201 compares the power levels of all the channels, and selects the reception beam having the maximum power level and the reception beams having the second to fourth power levels. When selecting the receive beam having the second power level, the power level of the previously selected beam is set to 0, and the beam selection circuit 2 is again set.
At 01, a comparison process is performed to obtain the channel number of the receive beam having the second power level. Hereinafter, similarly, the reception beams having the third and fourth power levels are selected.

FIG. 11 is a block diagram showing the phase shift circuit 202 of FIG. 1, and FIG. 12 is a plan view showing a beam phase shift process in the phase shift circuit 202 of FIG.

In this embodiment, as the input signal to the phase shift circuit 202, four reception beams having higher power levels counted from the beam having the highest power level are selected. The channel number data of these reception beams are respectively stored in channel number registers 231 through 23.
4 temporarily stored in the input data multiplexer 2
25 are input to each pair of input terminals 0 to 3 and
Spatial data of the real part (data temporarily stored in the spatial data register 54a of FIG. 4) and spatial data of the imaginary part (temporarily stored in the spatial data register 54b of FIG. 4) corresponding to those channel numbers. Data) are input from four of the DSPs 5-1 to 5-16 as I-channel and Q-channel spatial data that are orthogonal to each other, and input data registers 221a, 221b,
222a, 222b, 223a, 223b, 224a,
After being temporarily stored in 224b, it is input to each input terminal 0 to 3 of the channel number multiplexer 235.

Then, the subsequent circuits in FIG. 11 perform the following complex operation to execute the phase shift processing to obtain a phase-shifted signal. Now, the arrangement of multi-beam output signals is shown in FIG. For example, FIG.
Let the channel 1 (shown as CH1 in the figure, hereinafter the same) be the coordinates of x = 1 and y = 1, and the phase shift amount φ _xy of each beam is expressed by the following equation (19). However,
x = 4 and y = 4 are the coordinates of φ _xy where x = 0 and y =
Set to 0. In FIG. 12, only the beam coordinates are significant, and FIGS. 13 and 14 show the physical meaning of the beam phase shift processing in the four-element array antenna. DSP5-
In the FFT operations 1 to 5-16, a vector operation is used to obtain the effect of the FFT. However, as it is, the center of the phase shift comes to the end of the array antenna as shown in FIG. The phase shift center before the phase shift processing is shown in FIG.
As shown in (2), a phase shift process is executed by the phase shift process 202 in order to bring the center position Op of the array antenna.

[0096]

[Equation 19] φ _xy = exp [−j {3π (x−1) / 4}] · exp
[-J {3π (y-1) / 4}]

Here, each beam is defined as Beam _xy = (I _xy ,
Q _xy ), the received data I _xy ′,
Q _xy ′ is expressed by the following _Expression 20 and Expression 21.

[0098]

I _xy ′ = cos (φ _xy ) I _xy −sin (φ _xy ) Q _xy

Q _xy ′ = sin (φ _xy ) I _xy + cos (φ _xy ) Q _xy

In FIG. 11, the input multiplexer 22
5 selects one of the pairs of the input terminals 0 to 3 and outputs one I channel data and one Q channel data to the input terminals 0 and 1 of the IQ multiplexer 226, respectively. Then, the IQ multiplexer 22
6 selects one of the input terminals 0 and 1 and outputs one data to the A input terminal of the product-sum calculator 227. On the other hand, the channel number multiplexer 235
Selects one of the input terminals 0 to 3 and stores one channel number data in the phase shift data ROM.
236. The phase shift data ROM 236 stores, for each channel, real part data (hereinafter referred to as Re) of phase shift data for shifting the data of each channel to the center Op of the array antenna 1 as shown in FIGS. Data and imaginary part data (hereinafter referred to as Im data) are stored in advance, and these data (specifically, cos (φ _xy ) and sin in FIGS. 13 and 14) are stored.
(Φ _xy ) data. ) Are input to the input terminals 0 and 1 of the ReIm multiplexer 237, respectively.
The m multiplexer 237 selects one of the input terminals 0 and 1 and outputs one data (Re data or Im data) to the B input terminal of the product-sum calculator 227. The product-sum calculator 227 calculates the first product of the data input to the A input terminal and the data input to the B input terminal according to the arithmetic expressions of Expressions 20 and 21, and temporarily stores the product. After the data is stored in the internal register, the second product is similarly calculated, and the sum or difference of the first product and the second product is calculated based on the addition / subtraction control signal, and the register is calculated. Via 228, the I channel data I _xy 'and the Q channel data Q _xy ' are temporarily stored in output data registers 229a and 229b, respectively.
After that, it outputs to the MRC processing circuit 203.

In other words, in the configuration of the embodiment shown in FIG. 11, the above equations (20) and (21) are performed on the selected four higher-level received beams to obtain the MRC.
Output to the processing circuit 203. Tables 5 to 8 show timing chart tables showing the operation of the phase shift circuit 202. Here, the state number is increased over time.

[0101]

[Table 5]

[0102]

[Table 6]

[0103]

[Table 7]

[0104]

[Table 8]

In Tables 5 to 8, MUX is a multiplexer, and the number in the column of the multiplexer is an input terminal number to be selected. 1 in the addition / subtraction control signal indicates addition, and 0 indicates subtraction. The output register trigger signal 1 indicates enable, and 0 indicates disable. R (•) indicates a real part, and I (•) indicates an imaginary part. Further, Re beam 1 indicates a phase shifting process of the first I channel data, and Im beam 1 indicates a phase shifting process of the first Q channel data. For example, the processing of the state numbers 1 to 4 is the phase shift processing of the data of the first I channel,
The input terminal receives the spatial data (R (S
Y1). ) Is input and the product-sum operation unit 2
The real part (indicated by R (PS1)) of the phase shift data for the first channel is input to the 27 B input terminal.
The result of these first products is temporarily stored in its internal register as RI (1). Next, the product-sum operation unit 22
7, the spatial data (indicated by I (SY1)) of the first Q channel is input to the A input terminal of the first channel, and the imaginary part of the phase shift data for the first channel is input to the B input terminal of the product-sum operation unit 227. (Indicated by I (PS1)). The sum of the result of the second product and the result RI (1) of the first product is calculated, and the resulting first I-channel data after the phase shift processing is state number 5 Then, the trigger signals of the output data registers 229a and 229b are enabled and output to the MRC processing circuit 203.

Similarly, the data after the phase shift processing of the first to fourth I and Q channels is calculated, and the phase shift data S composed of the data after the phase shift processing of the I and Q channels is calculated. _n (n = 0, 1, 2, 3)
Is output to the MRC processing circuit 203. That is, as output data of the phase shift circuit 202, four reception beams can be obtained from the one with the largest power level whose phase center is shifted to the center Op of the array antenna.

In the phase shift circuit 202 shown in FIG.
Although the multiplexers 225 and 226 are divided into two multiplexers, the present invention is not limited to this. Is also good.

The comparison circuit 204 includes power comparators 241 to 244, as shown in FIG. In the comparison circuit 204, the power comparator 241 compares the first power data input to the A input terminal with the predetermined power threshold data input to the B input terminal to determine the first power data. Is higher than the power threshold data, the first channel state data at the H level is output to the MRC processing circuit 203. If the first power data is lower than the power threshold data, the first channel state data at the L level is output. Is output to the MRC processing circuit 203. The power comparator 242 compares the second power data input to the A input terminal with the power threshold data input to the B input terminal, and determines that the second power data is equal to or larger than the power threshold data. In the case of, the second channel state data at the H level is output to the MRC processing circuit 203. If the second power data is less than the power threshold data, the second channel state data at the L level is subjected to the MRC processing. Output to the circuit 203. Similarly, power comparators 243 and 244 output H-level third and fourth channel state data to MRC processing circuit 203 when the third and fourth power data are equal to or greater than the power threshold data, respectively. , And the third and fourth power data are smaller than the power threshold data, the L-level third and fourth channel state data are converted to the MRC processing circuit 2.
03 is output.

Next, the MRC processing circuit 203 will be described. FIG. 16 is a block diagram showing functions of the MRC processing circuit 203 of FIG. The MRC processing circuit 203 includes multipliers 301, 311, 321, 331, 304, 31
4,324,334 and IIR low pass filter 302,
312, 322, 332 and delay circuits 303, 313, 3
23,333 and squaring circuits 305,315,325,33
5 and adders 306 and 307 and a normalizing circuit 308, and execute processing described later.

First, the principle of MRC signal processing will be briefly described. The MRC signal processing according to the embodiment is performed on the four phase-shifted data S _{0 to} S ₃ which are quasi-coherently detected. Where 4
Each of the two phase shift data S _n (n = 0, 1, 2, 3) includes I channel data Re (S _n ) and Q channel data Im (S _n ). That is, the phase shift data S _n
(N = 0, 1, 2, 3) can be expressed as the following Expression 22 when expressed by complex numbers. Here, the first phase shift data S ₀ is reference phase shift data having the maximum power, and is represented by Expression 23.

[0111]

Equation 22] _{S n = Re (S n)} + jIm (S n) = a n exp {j (φ m + θ 0 + δ n)}

S ₀ = Re (S ₀ ) + jIm (S ₀ ) = a ₀ exp {j (φ _m + θ ₀ )}

Here, a ₀ is an amplitude component of the reference phase shift data S ₀ , a _{1 to} a ₃ are amplitude components of the phase shift data S _{1 to} S ₃ , respectively, and φ _m is a modulation phase. is there. Also,
theta ₀ is the phase difference between the local oscillation signal generated by the phase data S ₀ and the local signal oscillator reference (not shown.), [delta] _n is the phase shift data S _n and the reference phase data S ₀ Is the phase difference. Φ _m and θ ₀ in Expressions 22 and 23 are as follows:
This can be eliminated by using the complex conjugate product arithmetic expression expressed by the following equation (24). Here, V in Equation 24 is a difference vector, and a value obtained by dividing the difference vector V by the amplitude a ₀ of the phase shift data S ₀ is referred to as a weight coefficient W _n (hereinafter, W _n is referred to as W 1), and is represented by Equation 25. * In Equations 24 and 25 represents complex conjugate.

[0113]

[Number 24] _{V = S 0 · S n *} = a 0 a n expj (δ n)

W _n = (1 / a ₀ ) V = (1 / a ₀ ) (S ₀ · S _n *)

Further, the phase shift data S _n is a complex conjugate of the difference vector V = (S ₀ · S _n *) of Equation 24 (S ₀ · S
_n *) by multiplying a *, has an amplitude proportional to the power of each phase shift data S _n, and the reference phase data S ₀ in phase of each vector X _n has is represented by the following equation 26 You. Therefore, the maximum ratio combining can be performed by combining the respective vectors _Xn expressed by Expression 26. That is, the MRC processing circuit 203 of the present embodiment basically performs the maximum ratio combining process based on the above principle.

[0115]

[Number 26] _{X n = S n · (S} 0 · S n *) * = a 0 a n 2 expj
(Φ _m + θ ₀ )

Here, the MRC processing circuit 20 of the present embodiment
In II, the IIR low-pass filters 302 and 31 are used to suppress the fluctuation of the amplitude of the phase shift data S _{0 to} S ₃ which are input signals due to the noise of the receiver and the band pass filter.
By using 2,322,332, the low-pass filtering expressed by the following Expression 27 is applied to the difference vector V expressed by the Expression 24. The IIR low-pass filters 302, 312, 32
No. 2,332 removes unnecessary waves of a predetermined frequency or more by delaying a part of the output by one sample period and repeating the feedback (for example, Kotaro Hirano, “Signal Processor and its Application”, Pascal Research Society, 1986 2
See month 28. ). However, the present invention is not limited to the first-order IIR low-pass filter, and may be configured by another low-pass filter such as a cyclic addition or FIR low-pass filter. Here, in the equation ^{_{27, F (S 0 m ·}} S n m *)
Is an output after being filtered by the IIR low-pass filter, and is referred to as a second weight coefficient in this specification. α is a filter coefficient, and in the present embodiment, α = 0.92212
Set to 6. M represents the number of samples, and F (a
₀ W _n ^m-1) is defined is calculated by ^{_{F (S 0 m-1 ·}} S n m-1 *), a second weighting factor of the n-th beam at (m-1) th. The second weighting coefficient is updated every time the number of samples is calculated using Expression 27. In this specification, the number of samples m is omitted when not particularly required.

[0117]

[Number 27] ^{_{F (S 0 m · S n}} m *) = S 0 m · S n m * + α · F
^{_{(A 0 W n m-1}} )

That is, in the present embodiment,
Thus, the phase shift data S_nAnd the difference vector V of Equation 24
Instead, the second weighting factor F after low-pass filtering represented by Expression 27
(S ₀ ^m・ S_n ^m*) = F (a₀W_n) To calculate the phase shift data
S_nAnd reference phase shift data S₀And are in phase.

[0119]

Xf _n = S _n · F (S ₀ · S _n *) = S _n · F (a ₀ W _n )

The MRC processing circuit 203 shown in FIG. 16 combines the in-phase vector Xf _n by the adding circuit 306 to perform maximum ratio combining, and
After the normalization in step 8, the finalized output vector data Z expressed by equation 29 is output. Here, the coefficient Ka is expressed by the following equation (30). That is, the final output vector data Z is output after being normalized by the total power of the four phase shift data S _{0 to} S ₃ .

[0121]

(Equation 29)

[Equation 30]

Next, referring to FIG. 16, MRC processing circuit 2
03 will be described. FIG. 16 is a block diagram showing the processing function of the MRC processing circuit 203. First, M
In the RC processing circuit 203, the first phase shift data S ₀
Are multipliers 301, 311, 321, 331 and delay circuit 3
03, the second phase-shifted data S ₁ is
1 is input to the delay circuit 313. Further, the third phase shift data S ₂ is input to the multiplier 321 and the delay circuit 323, and the fourth phase shift data S ₃ is input to the multiplier 331 and the delay circuit 333.

The multiplier 301 squares the input first phase shift data S ₀ and outputs square data (S ₀ ² ) to the IIR low-pass filter 302. The IIR low-pass filter 302 low-pass filters the squared data (S ₀ ² ) input from the multiplier 301, and filters the squared data F
(S ₀ ² ) is output to the multiplier 304 and the squaring circuit 305. Here, the squared data F (S ₀ ² ) is F (S ₀ · S ₀ *)
And becomes the second weighting factor F (a ₀ W ₀ ). The multiplier 304 multiplies the first phase shift data S ₀ input via the delay circuit 303 by the second weighting factor F (a ₀ W ₀ ), and multiplies the multiplication result data S ₀ · F (a ₀ W ₀ ) is output to the addition circuit 306. Here, the delay circuit 303 converts the first phase shift data S ₀ by the total delay amount of the first delay amount calculated by the multiplier 301 and the second delay amount calculated by the IIR low-pass filter 302. Delayed multiplier 304
Output to

The multiplier 311 multiplies the input first phase shift data S ₀ by the input second phase shift data S ₁ , and multiplies the multiplication result data (S ₀ · S ₁ *) by IIR low pass. Filter 3
12 is output. The IIR low-pass filter 312 outputs the multiplication result data (S ₀ · S ₁ *) input from the multiplier 311
Of the multiplication result data F (S ₀ · S ₁
*) As the second weighting factor F (a ₀ W ₁ ).
And a squaring circuit 315. The multiplier 314 outputs the second
As the weighting factor F (a ₀ W _1), by multiplying the second and phase data S ₁ inputted the in-phase second weighting factor F through the delay circuit 313 (a ₀ W ₁₎ Multiplication result data S ₁ · F
(A ₀ W ₁ ) is output to the addition circuit 306. Here, the delay circuit 313 converts the second phase shift data S ₀ by the total delay amount of the first delay amount calculated by the multiplier 311 and the second delay amount calculated by the IIR low-pass filter 312. The signal is delayed and output to the multiplier 314.

Similarly, multiplier 321 multiplies input first phase-shift data S ₀ and third phase-shift data S ₂ , and multiplies multiplication result data (S ₀ · S ₂ *) by IIR. Output to the low-pass filter 322. IIR low pass filter 32
2 is the multiplication result data (S
₀ · S ₂ *) is low-pass filtered, and the multiplication result data F after the filtering
The second weighting coefficient F (a ₀ W ₂ ), which is (S ₀ · S ₂ *), is output to the multiplier 324 and the squaring circuit 325. Multiplier 32
4 is input in phase with the second weighting factor F (a ₀ W ₂ ) input from the IIR low-pass filter 322 and the second weighting factor F (a ₀ W ₂ ) via the delay circuit 323. Is multiplied by the third phase shift data S _2, and the multiplication result data S _2.
F (a ₀ W ₂ ) is output to the addition circuit 306. Here, the delay circuit 323 converts the second phase shift data S ₀ by the total delay amount of the first delay amount calculated by the multiplier 321 and the second delay amount calculated by the IIR low-pass filter 322. The signal is delayed and output to the multiplier 324.

The multiplier 331 multiplies the input first phase shift data S ₀ by the fourth phase shift data S ₃ and outputs the multiplication result data (S ₀ · S ₃ *) by the IIR low. Output to the band pass filter 332. IIR low pass filter 33
2 is the multiplication result data (S
₀ · S ₃ *) is low-pass filtered, and the multiplication result data F after the filtering
The second weighting coefficient F (a ₀ W ₃ ), which is (S ₀ · S ₃ *), is output to the multiplier 334 and the squaring circuit 335. Multiplier 33
4 is input in phase with the second weighting factor F (a ₀ W ₃ ) input from the IIR low-pass filter 332 and the second weighting factor F (a ₀ W ₃ ) via the delay circuit 333. Is multiplied by the fourth phase shift data S _3, and the multiplication result data S _3.
F (a ₀ W ₃ ) is output to the addition circuit 306. Here, the delay circuit 333 converts the second phase shift data S ₀ by the total delay amount of the first delay amount calculated by the multiplier 331 and the second delay amount calculated by the IIR low-pass filter 332. The output is delayed and output to the multiplier 334.

The squaring circuit 305 squares the input second weighting coefficient F (a ₀ W ₀ ) to generate squared data ｛F (a
₀ W ₀ )｝ ² is output to the adding circuit 307. Similarly, the squaring circuits 315, 325, and 335 respectively input the second weighting coefficients F (a ₀ W ₁ ), F (a ₀ W ₂ ), and F (a ₀
W ₃ ) and squared data {F (a ₀ W ₁ )} ² , ΔF
(A ₀ W ₂ )｝ ² and {F (a ₀ W ₃ )} ² are output to the adding circuit 307.

The adder circuit 306 receives the input four multiplication result data S ₀ .F (a ₀ W ₀ ), S ₁ .F (a ₀ W ₁ ), S _2.
F (a ₀ W ₂ ) and S ₃ · F (a ₀ W ₃ ) are added, and vector data Za as addition result data is output to the normalization circuit 308. Here, the vector data Za, which is the addition result data, is expressed by the following equation 31, and represents the amplitude of the baseband signal. Therefore, the final output vector data Z is data in which the vector data Za representing the amplitude of the baseband signal is standardized by the total power of the four phase shift data S _{0 to} S ₃ .

[0129]

(Equation 31)

The adding circuit 307 receives the four squared data {F (a ₀ W ₀ )} ² , {F (a ₀ W ₁ )} ² , ΔF
(A ₀ W ₂ )｝ ² and {F (a ₀ W ₃ )} ² are added, and the addition result data is output to the normalization circuit 308. Here, the addition result data is represented by the following Expression 32, that is, the addition result data is a coefficient Ka represented by Expression 30.

[0131]

(Equation 32)

The normalization circuit 308 normalizes the vector data Za by multiplying the input vector data Za by a normalization coefficient K given by the following equation (33).
The final output vector data Z represented by Expression 29 is output. Here, the normalization circuit 308 is configured by, for example, a variable power amplifier.

[0133]

[Equation 33] K = 1 / {(Ka)}

FIGS. 17 and 18 are block diagrams when the MRC processing circuit 203 of FIG. 1 is constituted by a digital circuit. Here, FIG. 17 shows a first part of the MRC processing circuit 203 constituted by a digital circuit, and FIG. 18 shows a second part of the MRC processing circuit 203 constituted by a digital circuit. FIG. 19 is a flowchart showing a flow of the MRC processing executed by the MRC processing circuit 203 in FIGS. Here, to describe the flow chart of FIG. 19, as shown in FIG. 19, first, in step S1, an initial value of the weighting factor W _n and the normalized coefficient K. That is, the four weight data W _{0 to} W ₃ are set to 0, respectively, and the normalization coefficient K is set to 1. Next, in step S2, the vector data Za is calculated using Expression 31. Then, in step S3, the final output vector data Z is calculated by normalizing the vector data Za. Further, in step S4, the n is set to 0, in step S5, it calculates a difference vector V is multiplied by the complex conjugate S _n * and the phase shift data S ₀ and the phase shift data S _n is the reference. Then, in step S6, the second weight data F (a ₀
W _n ). Next, it is determined in step S7 whether n is 3 or not. If n = 3, the process proceeds to step S9. If n = 3, the process proceeds to step S8. In step S8, n is updated to n + 1, and the flow advances to step S5 to repeat steps S5, S6, and S7. In step S9, the coefficient Ka is calculated using Expression 30, and
The normalized coefficient K corresponding to the coefficient Ka is stored in the table ROM 13.
6 and updates the normalization coefficient K, and then proceeds to step S2. Hereinafter, steps S2 to S9 are repeated.

Next, referring to FIG. 17 and FIG.
The configuration of the processing circuit 203 will be described in detail. First,
As shown in FIG. 17, the first I-channel data Re (S ₀ ) after the phase shift processing output from the phase shift circuit 202.
Are temporarily stored in the input data register 121a, and then input to the input terminal 0 of the A multiplexer 125 and the input terminal 0 of the B multiplexer 126. Further, the first Q channel data Im (S ₀ ) after the phase shift processing output from the phase shift circuit 202 is input to the input data register 12.
1b, the A multiplexer 125
Input terminal 1 of the B multiplexer 126
Is input to Further, the second to fourth I-channel data Re (S ₁ ) to Re (S ₃ ) output from the phase shift circuit 202 after the phase shift processing and the Q-channel data I
m (S ₁ ) to Im (S ₃ ) are input data registers 122a, 122b, 123a, 123b, and 124, respectively.
After being temporarily stored in a and 124b, they are input to the input terminals 2 to 7 of the A multiplexer 125.

The A multiplexer 125 selectively selects one of the eight data input through the eight input terminals 0 to 7, and transfers the selected one data to the input terminal of the C multiplexer 127. Output to 0. The input terminal 1 of the C multiplexer 127 receives the I-channel intermediate data Re (Z) output from the intermediate register 134-1 described later.
The Q channel intermediate data Im (Z) output from the intermediate register 134-2 is input to the input terminal 2 of the C. 27, and the input terminal 3 of the C multiplexer 127 is output from the L multiplexer 163 of FIG. I channel weighting factor _{Re {F (a 0 W n} )} or Q-channel weighting factor _{Im {F (a 0 W n} )} is input. And
Output data from the C multiplexer 127 is input to one input terminal of the multiplier 131 via the multiplier register 129.

The B multiplexer 126 selectively selects one of the two data input through the two input terminals 0 and 1 and transfers the selected one data to the input terminal of the D multiplexer 128. Output to 2. Incidentally, D to the input terminal 0 of the multiplexer 128, described later L is outputted from the multiplexer 163 I-channel weighting factor _{Re {F (a 0 W n} )} or Q-channel weighting factor Im {F (a ₀ W in FIG. 18 _n )} is input to the input terminal 1 of the D multiplexer 128, and a table R
The normalization coefficient K output from the OM 136 is input.
The D multiplexer 128 has three input terminals 0, 1, 2,
, And selectively outputs one of the three data inputted through the multiplier 131 to the other input terminal of the multiplier 131 via the multiplicand register 130.

Multiplier 131 multiplies the multiplier data input via multiplier register 129 by the multiplicand data input via multiplicand register 130, and multiplies the multiplication result data via register 132 to accumulator 133 Output register 135-1 and output register 13
5-2 and output the final output vector data Z after the MRC processing. That is, the I-channel final output vector data Re calculated by the multiplier 131
(Z) is output after being temporarily stored in the output register 135-1.
m (Z) is output after being temporarily stored in the output register 135-2.

A cumulative adder 133 performs cumulative addition by adding or subtracting the multiplication result data input from the multiplier 131 via the register 132 based on the input addition / subtraction control signal C1. Is output. Output data from the accumulator 133 is determined by the intermediate registers 134-1 through 134- depending on the contents of the data.
3, the input terminal 1 or 2 of the C multiplexer 127 or the table ROM 1
36 is input to the address input terminal 36, while I
The signal is input to the input terminal 0 of the multiplexer 155. The table ROM 136 stores various coefficients Ka input in advance.
Is stored. When the address of the coefficient Ka is input to the table ROM 136, the corresponding normalized coefficient K is read out, and the input terminal of the D multiplexer 128 is input. 1 is input.

Further, as shown in FIG.
2 is temporarily stored in the channel number register 111,
It is input to the input terminal 0 of the E multiplexer 151 and the input terminal 0 of the F multiplexer 152. Phase shift circuit 202
Is temporarily stored in the channel number register 112, and then the second channel number data
The signal is input to the input terminal 1 of the multiplexer 151 and the input terminal 1 of the F multiplexer 152. The third channel number data output from the phase shift circuit 202 is temporarily stored in the channel number register 113 and then input to the input terminal 2 of the E multiplexer 151 and the input terminal 2 of the F multiplexer 152. The fourth channel number data output from the phase shift circuit 202 is temporarily stored in the channel number register 114, and then the input terminal 3 of the E multiplexer 151 and the F multiplexer 1
52 is input to the input terminal 3.

The E multiplexer 151 selectively selects one of the four data input through the four input terminals 0 to 3 and stores the selected channel number data in the I-channel wait RAM 161. It outputs to the address input terminal and one input terminal of the channel comparator 164. The F multiplexer 152 selects one input terminal among the four input terminals 0 to 3 and converts one channel number data into a Q channel weight RA.
M162 address input terminal and channel comparator 16
5 to one input terminal.

As described above, the input terminal 0 of the I multiplexer 155 receives the cumulative addition data from the cumulative adder 133 shown in FIG. 17, and the input terminal 1 of the I multiplexer 155 outputs the output of the L multiplexer 163 described later. Upper 8 bits of data are input as lower 8 bits of 16-bit input data, and 0 is input to upper 8 bits of input terminal 1. As a result, the output data of the L multiplexer 163 is applied to the input terminal 1 of the I multiplexer 155 by 1/127 ≒ 0.007874.
Is input as input data.

I multiplexer 155 selectively selects one of two data input through two input terminals 0 and 1 and accumulates the selected one data via register 156. Input terminal A of adder 157
To enter. Note that the output data of the L multiplexer 163, which will be described later, is directly input to the input terminal B of the accumulator 157 when the initial value write signal C3 rises. The accumulative adder 157 adds or subtracts the data input through the input terminal B and the data input from the input terminal A based on the addition / subtraction control signal C2, thereby accumulating and adding the result. Register data in register 1
The signal is input to the input terminal 0 of the J multiplexer 159 via 58. The J multiplexer 159 selectively selects one of the two data input through the two input terminals 0 and 1 based on the input reset signal, and converts the selected one data. Output. That is,
The reset signal input to the J multiplexer 159 is L
When the input signal is at the level, the input data input from the input terminal 0 is selected and output. When the input reset signal is at the H level, 0 input from the input terminal 1 is selected and output. The output data of the J multiplexer 159 is input to the data input terminal of the I-channel weight RAM 161 and the data input terminal of the Q-channel weight RAM 162.

The I-channel weight RAM 161 stores each I-channel address corresponding to each channel number,
The data of the I-channel weighting factor, which is the real part of the second weighting factor corresponding to each channel number, is stored, and the data of the I-channel weighting factor is updated as described later. Here, each channel number is determined corresponding to 16 beam positions having different beam directions. When an H level write enable signal WE1 is input to the I channel wait RAM 161,
The address specified by the channel number data of the I channel input from the E multiplexer 151
The updated I-channel weight coefficient data input from the multiplexer 159 is written. When the L-level write enable signal WE1 is input and the H-level output enable signal OE1 is input to the I-channel wait RAM 161, the address specified by the channel number data input from the E multiplexer 151. Is read out, and the data is input to the input terminal 0 of the L multiplexer 163.

The Q channel weight RAM 162 stores, in each Q channel address corresponding to each channel number,
The data of the Q channel weighting factor, which is the imaginary part of the second weighting factor corresponding to each channel number, is stored, and the data of the Q channel weighting factor is updated as described later. In the Q channel weight RAM 162,
When the H-level write enable signal WE2 is input, the updated Q channel weight coefficient data input from the J multiplexer 159 is written to the address specified by the channel number data input from the F multiplexer 152. When the L level write enable signal WE2 and the H level output enable signal OE2 are input to the Q channel weight RAM 162, the address specified by the channel number data input from the F multiplexer 152. Is read out, and the data is input to the input terminal 1 of the L multiplexer 163.

The L multiplexer 163 selectively selects one of the two data input through the two input terminals 0 and 1 and outputs the selected data.
The output data of the L multiplexer 163 is connected to the input terminal 3 of the C multiplexer 127 and the D multiplexer 1 of FIG.
The signal is input to the input terminal 0 of the I / M multiplexer 155 and the input terminal B of the accumulator 157 while being input to the input terminal 0 of the I / O multiplexer 28. Here, as described above, only the upper 8 bits of the output data of the L multiplexer 163 are input to the input terminal 1 of the I multiplexer 155 as the lower 8 bits of the data of the I multiplexer 155. With the above configuration, the above-described MRC processing is executed.

Next, the reset signal generation circuit 300 will be described. The reset signal generation circuit 300 includes a register 115 and a state data register 14 as shown in FIG.
1 to 144, a G multiplexer 153, an H multiplexer 154, channel comparators 164 and 165, OR gates 166 and 167, and a K multiplexer 168.

In the reset signal generating circuit 300, the register 115 temporarily stores the channel number data used in the previous processing, and the other input terminal of the channel comparator 164 and the other input terminal of the channel comparator 165. And output to The channel comparator 1
As described above, the channel number data to be processed this time is input to one of the input terminals 64 via the E multiplexer 151. The channel comparator 164 compares the currently processed channel number data with the previously processed channel number data. If the two input channel number data are different, the channel comparator 164 outputs an H level signal via the OR gate 166. The signal is output to the input terminal 0 of the K multiplexer 168, and if the two input channel number data are equal, an L level signal is output in the same manner.

As described above, channel number data to be processed this time is input to one input terminal of the channel comparator 165 via the F multiplexer 152, and the channel comparator 165 outputs the channel number data to be processed this time. The data is compared with the previously processed channel number data. If the two input channel number data are different, an H level signal is output to the input terminal 1 of the K multiplexer 168 via the OR gate 167,
If the two input channel number data are equal, an L-level signal is similarly output.

Further, the 1 input from the comparison circuit 204
The state data of the channel is temporarily stored in the state data register 141 and then stored in the G multiplexer 15.
3 and the input terminal 0 of the H multiplexer 154. The status data of the second channel output from the comparison circuit 204 is stored in the status data register 14.
After that, the data is temporarily stored in the input terminal 1 of the G multiplexer 153 and the input terminal 1 of the H multiplexer 152. The state data of the third channel output from the comparison circuit 204 is temporarily stored in the state data register 143 and then input to the input terminal 2 of the G multiplexer 153 and the input terminal 2 of the H multiplexer 154. The state data of the fourth channel output from the comparison circuit 204 is temporarily stored in the state data register 144, and is then input to the input terminal 3 of the G multiplexer 153 and the input terminal 3 of the H multiplexer 154.

The G multiplexer 153 selectively selects one of the four data input through the four input terminals 0 to 3, and outputs the state data of the selected one channel to the OR gate 166. To the input terminal 0 of the K multiplexer 168 via an input terminal, and the H multiplexer 154 selectively selects one of the four data input through the four input terminals 0 to 3 to be selected. The status data of the channel is output to the input terminal 1 of the K multiplexer 168 via the OR gate 167. The K multiplexer 168 selectively selects one of two data input through the two input terminals 0 and 1 and outputs the selected data to the J multiplexer 159. Here, OR gate 166
Outputs an L level signal when the previous processing channel of the I channel is the same as the current processing channel and the power of the channel is equal to or higher than the threshold, and otherwise outputs an H level signal. Is output to the reset terminal of the J multiplexer 159 via the K multiplexer 168, and the OR gate 167 determines that the previous processing channel of the Q channel is the same as the current processing channel and that the power of the channel is a threshold. In the above case, an L-level signal is output. Otherwise, an H-level reset signal is output to the reset terminal of the J multiplexer 159 via the K multiplexer 168. The reset signal generation circuit 300 is configured as described above.

Central processing unit (CPU) 180 in FIG.
Are the switching signals of the input terminals of the multiplexers described above and shown in FIGS.
E1, WE2, output enable signals OE1, OE2, addition / subtraction control signal C1 to accumulator 133, accumulator 1
Control signals such as an addition / subtraction control signal C2 and an initial value writing signal C3 to / from the CPU 57 are generated to control each device. As described above, the MRC processing circuit 203 including the reset signal generation circuit 300 is configured.

FIGS. 20 to 30 show the MRC processing circuit 20.
6 is a timing chart showing the operation of No. 3; The operation of the MRC processing circuit 203 will be described with reference to the timing chart. Here, the state number, which is the state number, is increased with time.

In FIGS. 20 to 30, MUX is a multiplexer, and the number in the column of the multiplexer is the input terminal number to be selected. The H level of the addition / subtraction control signals C1 and C2 indicates addition, and the L level indicates subtraction. When the latch trigger signal rises to the H level, the register 158 latches and outputs the input data. The intermediate registers 134-1 to 134-3 latch and output the input data when the respective latch trigger signals rise to the H level. Output register 135-
When each latch trigger signal rises to the H level, 1,135-2 latches and outputs an input signal.

The H level of the write enable signal WE1 indicates writing to the I-channel wait RAM 161. The H level of the write enable signal WE2 indicates writing to the Q channel wait RAM 162. Also,
Re (•) indicates a real part, and Im (•) indicates an imaginary part. Further, NOP in the column of multiplier data of the multiplier 131 indicates that the multiplier 131 is not processed. In addition,
F _n (n = 0, 1, 2, 3) is a second weighting factor F (a ₀
W _n ).

In FIGS. 20 to 30, the processing in each state is as follows. (1) In states 1 to 9, I-channel vector data Re (Za) which is a real part of vector data Za
The operation result is temporarily stored in the intermediate register 134-1 in the state 10.

(2) States 10 to 18 are processing of the Q-channel vector data Im (Za), which is the imaginary part of the vector data Za, and the calculation result is temporarily stored in the state 19 in the intermediate register 134-2. Is stored in In state 18, the multiplier 131 multiplies the I-channel vector data Re (Za), which is the real part of the vector data Za, by the normalization coefficient K, and the multiplication result data K · Re (Z) is temporarily stored. After being stored in the output register 135-1, it is output as the I channel data Re (Z) of the final output vector data Z.

(3) The states 19 to 22 are mainly for calculating the I-channel weighting factor Re (F ₀ ) which is the real part of the first second weighting factor F (a ₀ W ₀ ). The operation result Re (F ₀ ) is written to the I-channel wait RAM 161 in the state 23. In addition,
In state 21, the multiplier 131 sets the Q-channel vector data Im, which is the imaginary part of the vector data Za.
(Za) is multiplied by the normalization coefficient K, and the multiplication result data K · Im (Za) is temporarily stored in the output register 1.
After being stored in 35-2, it is output as Q channel data Im (Z) of the final output vector data Z. Further, in state 22, the first second weighting factor F (a
₀ W ₀ ), which is the imaginary part of Q channel weighting factor Im
The calculation process of (F ₀ ) is started. That is, the I-channel weighting factor R of the first second weighting factor F (a ₀ W ₀ )
e (F ₀ ) and the first second weighting factor F
The calculation processing of the Q channel weight coefficient Im (F ₀ ) of (a ₀ W ₀ ) and the normalization processing of the Q channel vector data Im (Za) of the vector data Za are executed substantially in real time.

(4) States 23 to 25 are mainly for calculating the Q channel weighting factor Im (F ₀ ) which is the imaginary part of the first second weighting factor F (a ₀ W ₀ ). The Q channel weighting factor Im (F
₀ ) is the state 26, the Q channel wait RAM 1
62 is written. In the state 25, the second second weighting coefficient F (a ₀ W ₁ ) is output from the multiplier 131.
Of the I-channel weighting factor Re (F ₁ ), which is the real part of, is started. That is, the real part of the calculation process of the first second weighting factor F (a ₀ W ₀₎ Q-channel weighting factor Im (F ₀₎ of the second second weighting factor F (a ₀ W ₁₎ And the calculation processing of the I-channel weighting factor Re (F ₁ ) is executed substantially in real time.

(5) The states 26 to 28 are mainly for calculating the I-channel weighting factor Re (F ₁ ) which is the real part of the second weighting factor F (a ₀ W ₁ ). The I channel weighting factor Re (F (F)
₁ ) In state 29, I channel wait RAM1
61 is written. In the state 28, the second weighting coefficient F (a ₀ W ₁ ) in the multiplier 131 is used.
The arithmetic processing of the Q channel weighting factor Im (F ₁ ), which is the imaginary part of, is started. That is, the imaginary part of the processing the I-channel weighting coefficient Re of the second second weighting factor _{F (a 0 W 1) (} F 1), 2 th second weighting factor F (a ₀ W ₁₎ And the calculation processing of the Q channel weighting coefficient Im (F ₁ ) is executed substantially in real time.

(6) States 29 to 31 are mainly for calculating the Q channel weighting factor Im (F ₁ ) which is the imaginary part of the second weighting factor F (a ₀ W ₁ ). The Q channel weighting factor Im (F
₁ ) is state 32, Q channel wait RAM 1
62 is written. In the state 28, the third second weighting coefficient F (a ₀ W ₂ ) is output from the multiplier 131.
Of the I-channel weighting factor Re (F ₂ ), which is the real part of. That is, the Q channel weighting factor I which is the imaginary part of the second weighting factor F (a ₀ W ₁ )
m (F ₁ ) and the third second weighting factor F
I channel weighting factor Re, which is the real part of (a ₀ W ₂ )
The calculation processing of (F ₂ ) is executed substantially in real time.

(7) The states 32 to 34 are mainly
To obtain a third second weighting factor F (a ₀W_TwoIs the real part of
I channel weighting factor Re (F_Two)
And the I channel weighting factor Re (F
_Two) Is the state 35 and the I channel wait RAM1
61 is written. In state 34, the multiplier
At 131, a third second weighting factor F (a₀W_Two)
Q channel weighting factor Im (F_Two) Performance
Calculation processing is started. That is, the third second weighter
Number F (a₀W_Two) Is the real part of the I-channel weighting factor R
e (F_Two) And the third second weighting factor F
(A₀W_Two) Is the imaginary part of the Q channel weighting factor Im
(F_Two) Arithmetic processing is executed substantially in real time
It is.

(8) The states 35 to 37 are mainly for calculating the Q channel weight coefficient Im (F ₂ ) which is the imaginary part of the third second weight coefficient F (a ₀ W ₂ ). The Q channel weighting factor Im (F
₂ ) In state 38, Q channel wait RAM 1
62 is written. In the state 37, the fourth second weighting coefficient F (a ₀ W ₃ ) is output from the multiplier 131.
Of the I-channel weighting factor Re (F ₃ ), which is the real part of. That is, the Q channel weighting factor I which is the imaginary part of the third second weighting factor F (a ₀ W ₂ )
m (F ₂ ) and the fourth second weighting factor F
I channel weighting factor Re which is a real part of (a ₀ W ₃ )
The calculation processing of (F ₃ ) is executed substantially in real time.

(9) The states 38 to 40 are mainly for calculating the I channel weighting factor Re (F ₃ ) which is the real part of the fourth second weighting factor F (a ₀ W ₃ ). The I channel weighting factor Re (F (F)
₃ ) The state 41 is an I channel wait RAM 1
61 is written. In the state 40, the fourth second weighting factor F (a ₀ W ₃ ) is output from the multiplier 131.
The arithmetic processing of the Q channel weighting factor Im (F ₃ ), which is the imaginary part of, is started. That is, the I-channel weighting factor R which is the real part of the fourth second weighting factor F (a ₀ W ₃ )
e (F ₃ ) and the fourth second weighting factor F
Q channel weighting factor Im which is an imaginary part of (a ₀ W ₃ )
The calculation processing of (F ₃ ) is executed substantially in real time.

(10) States 41 to 43 are mainly for calculating the Q-channel weighting coefficient Im (F ₃ ) which is the imaginary part of the fourth second weighting coefficient F (a ₀ W ₃ ). The Q channel weighting factor Im (F
₃ ) In state 44, Q channel wait RAM1
62 is written. In the state 43, the multiplier 131 starts the calculation process of the coefficient Ka. (11) States 44 to 51 are processing of calculating the coefficient Ka, and the result of the calculation is temporarily stored in the intermediate register 134-3.

That is, the states 0 to 18 of the above (1) and (2) mainly execute the arithmetic processing of the vector data Za in step S2 in the flowchart of FIG. State 19
In the state 43, the second weighting factor F of steps S4 to S7 in the flowchart of FIG.
(A ₀ W _n ) is being executed. Further, in the state (44) to the state (51) of the above (11), FIG.
Of the coefficient Ka in step S9 in the flowchart of FIG. Then, the arithmetic processing for normalizing the vector data Za in step S3 in the flowchart of FIG. Running on

The operation of the MRC processing circuit 203 will be described in detail with reference to FIGS. FIG. 20 is a first timing chart. First, the MRC processing circuit 203
Will be described with reference to the timing chart. In the timing chart, “state” is a serial number added for convenience in describing the state corresponding to the clock. Here, "X" in each multiplexer represents indefinite. The switching signal of each multiplexer, the latch trigger signal to each register shown in FIGS. 20 to 30, and the write enable signal WE1,
WE2 is generated by the controller (not shown) or a timing signal generation circuit (not shown) controlled by the controller.

As shown in FIG. 20, the A multiplexer 125, the C multiplexer 127, the D multiplexer 128, the E multiplexer 151, the G multiplexer 153, the F multiplexer 152, the H multiplexer 154, and the L multiplexer 163 are set at an intermediate timing of the state 0. Each is switched to input terminal 0. Therefore, the A multiplexer 125 and the C multiplexer 127
Are switched to the input terminal 0, so that the first I channel data Re (S ₀ ) is
Is input to the multiplier register 129 via the input terminal 0 of the C multiplexer 127 and the input terminal 0 of the C multiplexer 127. Further, since the E multiplexer 151 is switched to the input terminal 0, the I channel weight coefficient Re (F (F) corresponding to the first channel number is read from the I channel weight RAM 161.
₀ ) is read out, and the L multiplexer 163 and the D multiplexer 128 are switched to the input terminal 0.
The channel weight coefficient Re (F ₀ ) is transferred from the I-channel weight RAM 161 to the multiplicand register 130.

In state 1, the reset signal R1 rises and the data of the accumulator 133 is reset to 0. The I-channel data Re is output by the multiplier 131.
(S ₀ ) is multiplied by the I-channel weighting coefficient Re (F ₀ ), and the multiplication result data Re (S ₀ ) · Re (F ₀ ) is output to the register 132. Further, the A multiplexer 125 is switched to the input terminal 1 at an intermediate timing of the state 1, whereby the first Q channel data Im (S ₀ ) is transferred to the multiplier register 129. Also,
At this time, the L multiplexer 163 is also switched to the input terminal 1, whereby the Q channel weight coefficient Im (F ₀ ) corresponding to the first channel number data input via the F multiplexer 152 is output from the Q channel weight RAM 162. Read out, multiplicand register 1
30.

Next, in state 2, the multiplier 131
Multiplies the Q channel data Im (S ₀ ) by the Q channel weighting factor Im (F ₀ ) to obtain the multiplication result data Im
(S ₀ ) · Im (F ₀ ) is output to the register 132. Further, based on the H-level addition / subtraction control signal C1, 0 is added to the multiplication result data Re (S ₀ ) · Re (F ₀ ) of the state 1 input from the register 132, and the state 2
From the intermediate timing of the intermediate state to the intermediate timing of the state 3, T1 = Re (S ₀ ) · Re (F ₀ )
Is output. Here, the A multiplexer 125 is switched to the input terminal 2 at an intermediate timing of the state 2,
As a result, the second I channel data Re (S ₁ ) is transferred to the multiplier register 129. Further, the E multiplexer 151 is switched to the input terminal 1 at an intermediate timing of the state 2, and the I-channel wait RAM
The second I-channel weighting factor Re (F ₁ ) corresponding to the second channel number is read out from 161, and the L multiplexer 163 and the D multiplexer 12 that have been switched to the input terminal 0 at the intermediate timing of state 2.
8 to the multiplicand register 130. Here, at an intermediate timing of the state 2, the G multiplexer 153 is also switched to the input terminal 1.

Next, in state 3, the multiplier 131
Multiplies the second I-channel data Re (S ₁ ) by the I-channel weighting factor Re (F ₁ ), and outputs multiplication result data Re (S ₁ ) · Re (F ₁ ) to the register 132. Further, the accumulative adder 133 calculates the accumulative output data T1 based on the L-level addition / subtraction control signal C1.
An accumulation process is performed by subtracting the multiplication result data Im (S ₀ ) · Im (F ₀ ) of the state 2 output from the register 132, and a cumulative addition output is performed at an intermediate timing of the state 3 to an intermediate timing of the state 4. Data T2 = Re
(S ₀ ) · Re (F ₀ ) −Im (S ₀ ) · Im (F ₀ ). Also, the A multiplexer 125 is switched to the input terminal 3 at an intermediate timing of the state 3, whereby the second Q channel data Im (S ₁ ) is transferred to the multiplier register 129. Further, the F multiplexer 152 is switched to the input terminal 1 at an intermediate timing of the state 3, and the Q channel wait RAM 162
, The second Q channel weighting factor Im (F ₁ ) corresponding to the second channel number is read out, and the multiplicand register is switched via the L multiplexer 163 which is also switched to the input terminal 1 at the intermediate timing of state 2. 130
Is forwarded to Here, at an intermediate timing of the state 3, the H multiplexer 154 is also switched to the input terminal 1.

In state 4, multiplier 131 outputs 2
The second Q channel data Im (S ₁ ) is multiplied by the second Q channel weight coefficient Im (F ₁ ), and the multiplication result data Im (S ₁ ) · Im (F ₁ ) is output to the register 132. Further, the accumulator 133 calculates the accumulative addition output data T2 and the multiplication result data Re (S ₁ ) · Re (F ₁ ) of the state 3 input from the register 132 based on the H-level addition / subtraction control signal C1. Accumulation processing is performed by adding, and the state 5
At the intermediate timing of T3 = Re
(S ₀ ) · Re (F ₀ ) −Im (S ₀ ) · Im (F ₀ ) + R
e (S ₁ ) · Re (F ₁ ) is output. State 4
A multiplexer 125 is switched to input terminal 4 at an intermediate timing of
9, the third I-channel data Re (S ₂ ) is transferred. Further, the E multiplexer 151 is switched to the input terminal 2 at an intermediate timing of the state 4, and the third Q channel weight coefficient Re corresponding to the third channel number is read from the I channel weight RAM 161.
(F ₂ ) is read out, and the L multiplexer 1 which is also switched to the input terminal 0 at the timing intermediate to the state 4
It is input to the multiplicand register 130 via 63. Here, at an intermediate timing of the state 4, the G multiplexer 153 is also switched to the input terminal 2.

Similarly, in states 5 to 8, the multiplication by the multiplier 131 and the cumulative addition by the cumulative adder 133 are repeatedly executed. Then, in state 9, the accumulative adder 133 outputs the multiplication result data Im (S ₃ ) · Im (S ₃ ) of the state 8 inputted from the register 132 from the accumulated addition output data T7 based on the L-level addition / subtraction control signal C1. F ₃ ) is subtracted to perform accumulation processing, and I-channel intermediate data Re (Za) = T7−Im, which is accumulated addition output data, from the intermediate timing of state 9 to the intermediate timing of state 10.
(S ₃ ) · Im (F ₃ ) is output. At an intermediate timing of the state 9, the A multiplexer 125 is switched to the input terminal 1, whereby the multiplier register 12
9, the Q channel data Im (S ₀ ) is transferred. Further, at an intermediate timing of the state 9, the input terminal 0 of the E multiplexer 151 has been switched.
I channel weight coefficient Re (F ₀ ) corresponding to the first channel number from I channel weight RAM 161
Is read and input to the multiplicand register 130 via the L multiplexer 163 switched to the input terminal 0. Here, the F multiplexer 152 is switched to the input terminal 0 at an intermediate timing of the state 9.

In state 10, the reset signal R1 rises and the data of the accumulator 133 is reset to zero. At the start of the state 10, the latch trigger signal of the intermediate register 134-1 rises, and the I-channel vector data Re (Za) of the vector data Za is stored in the intermediate register 1
34-1 is temporarily stored. In state 10, the multiplier 131 outputs the Q channel data Im (S ₀ )
And the first I-channel weighting factor Re (F ₀ ), and outputs multiplication result data Im (S ₀ ) · Re (F ₀ ) to the register 132. The A multiplexer 125 is switched to the input terminal 0 at an intermediate timing of the state 10, whereby the first I-channel data Re (S ₀ ) is transferred to the multiplier register 129. Also,
At this time, the L multiplexer 163 is also switched to the input terminal 1, whereby the first Q channel weight coefficient Im (F ₀ ) corresponding to the first channel number data input via the F multiplexer 152 is changed to the Q channel. It is read from the weight RAM 162 and transferred to the multiplicand register 130. At the end of the state 10, the reset signal R1 falls and the cumulative adder 133 falls.
Is reset.

Next, in state 11, the multiplier 13
1 multiplies the I channel data Re (S ₀ ) by the Q channel weighting factor Im (F ₀ ),
(S ₀ ) · Im (F ₀ ) is output to the register 132. Also, since the accumulator 133 has been reset to 0,
Based on the H-level addition / subtraction control signal C1, 0 is added to the multiplication result data Im (S ₀ ) · Re (F ₀ ) of the state 10 input from the register 132, and the state 11
Cumulative addition output data at an intermediate timing of the state 12 from the intermediate timing _{E1 = Im (S 0) ·} Re
(F ₀ ) is output. Here, the A multiplexer 125 is switched to the input terminal 3 at an intermediate timing of the state 11, whereby the second Q channel data Im (S ₁ ) is transferred to the multiplier register 129. Further, the E multiplexer 151 is switched to the input terminal 1 at an intermediate timing of the state 11, and the second I-channel weight coefficient Re (F ₁ ) corresponding to the second channel number is read from the I-channel weight RAM 161. Similarly, the signal is transferred to the multiplicand register 130 via the L multiplexer 163 and the D multiplexer 128 which are switched to the input terminal 0 at an intermediate timing of the state 2. Here, at the intermediate timing of state 2,
The G multiplexer 153 is also switched to the input terminal 1.

Next, in state 12, the multiplier 13
1 multiplies the Q channel data Im (S ₁ ) by the I channel weighting factor Re (F ₁ ),
m (S ₁ ) · Re (F ₁ ) is output to the register 132.
Further, the accumulator 133 converts the multiplication result data Re (S ₀ ) · Im (F ₀ ) of the state 11 input from the register 132 from the accumulated addition output data E 1 based on the H-level addition / subtraction control signal C 1. The accumulation process is performed by subtraction, and the state 1 is shifted from the middle timing of the state 12 to the state 1.
3 at the intermediate timing of E3 = Im
(S ₀ ) · Re (F ₀ ) + Re (S ₀ ) · Im (F ₀ ). The A multiplexer 125 is switched to the input terminal 2 at an intermediate timing of the state 12, whereby the second I channel data Re (S ₁ ) is transferred to the multiplier register 129. In addition, state 1
The F multiplexer 152 is switched to the input terminal 1 at an intermediate timing between the two, and the Q channel wait RAM 1
The second Q corresponding to the second channel number from 62
The channel weighting coefficient Im (F ₁ ) is read out and transferred to the multiplicand register 130 via the L multiplexer 163 switched to the input terminal 1 at an intermediate timing of the state 12. Here, at an intermediate timing of the state 12, the H multiplexer 154 is also switched to the input terminal 1.

In the state 13, the multiplier 131
The I-channel data Re (S ₁ ) is multiplied by the second Q-channel weighting factor Im (F ₁ ), and the multiplication result data R
e (S ₁ ) · Im (F ₁ ) is output to the register 132.
Further, the accumulative adder 133 outputs the accumulative addition output data E2 and the register 1 based on the H level addition / subtraction control signal C1.
Multiplication result data Im of state 12 input from
(S ₁ ) · Re (F ₁ ) is added to perform an accumulation process.
At the intermediate timing of E3 = E2 +
Im (S ₁ ) · Re (F ₁ ) is output. The A multiplexer 125 is switched to the input terminal 5 at an intermediate timing of the state 13, whereby the Q channel data Im (S ₂ ) is transferred to the multiplier register 129. Further, the E multiplexer 151 is switched to the input terminal 2 at an intermediate timing of the state 13, and the third I-channel weight coefficient Re corresponding to the third channel number is read from the I-channel weight RAM 161.
(F ₂ ) is read out and input to the multiplicand register 130 via the L multiplexer 163 switched to the input terminal 0 at the same timing as in the state 13. Here, at an intermediate timing of the state 13, the G multiplexer 153 is also switched to the input terminal 2.

Similarly, the multiplication by the multiplier 131 and the accumulation by the adder
3 is repeatedly executed. Then, in state 17, the multiplier 131 multiplies the fourth I-channel data Re (S ₃ ) by the fourth Q-channel weighting factor Im (F ₃ ), and obtains the multiplication result data Re
(S ₃ ) · Im (F ₃ ) is output to the register 132. The accumulator 133 outputs an H-level addition / subtraction control signal C
1 and the accumulated addition output data E6 and the register 13
2 multiplied result data Im of state 16
(S ₃ ) · Re (F ₃ ) is added and accumulation is performed.
At the intermediate timing of E7 = E6 +
Im (S ₃ ) · Re (F ₃ ) is output. The C multiplexer 127 is switched to the input terminal 1 at an intermediate timing of the state 17, whereby the I-channel power data Re (Z) is transferred to the multiplier register 129. Further, the D multiplexer 128 is switched to the input terminal 1 at an intermediate timing of the state 17, whereby the normalization coefficient K read from the table ROM 136 is transferred to the multiplicand register 130. here,
At an intermediate timing of the state 17, the E multiplexer 151 is switched to the input terminal 0, and the L multiplexer 163 is switched to the input terminal 0.

In state 18, the multiplier 131
The I-channel power data Re (Z) is multiplied by the normalization coefficient K, and the multiplication result data K · Re (Z) is stored in the register 13.
Output to 2. Further, the accumulative adder 133 outputs the accumulative addition output data E based on the H-level addition / subtraction control signal C1.
7 and the multiplication result data Re (S ₃ ) · Im (F ₃ ) of the state 17 inputted from the register 132 are added up to perform accumulation processing, and from the intermediate timing of the state 18 to the intermediate timing of the state 19 Q channel vector data Im (Za) = E which is cumulative addition output data
7 + Re (S ₃ ) · Im (F ₃ ) is output. State 1
At an intermediate timing of 8, the B multiplexer 126 is switched to the input terminal 0, and the D multiplexer 128 is switched to the input terminal 2, whereby the first I-channel data Re (S ₀ ) is transferred to the multiplicand register 130. You. At an intermediate timing of the state 18, the C multiplexer 127 is switched to 0, whereby the I-channel data Re (S
₀ ) is transferred. Since the latch trigger signal of the intermediate register 134-2 rises at the end of the state 18, the Q-channel vector data Im (Za) which is the cumulative output data which is the output data of the cumulative adder 133 is temporarily stored in the intermediate register 134-2. It is memorized.

In state 19, accumulator 133
Is reset, the data of the accumulator 133 is reset to zero. Multiplier 131
Multiplies the first I-channel data Re (S ₀ ) by the first I-channel data Re (S ₀ ), and outputs multiplication result data Re (S ₀ ² ) to the register 132.
At an intermediate timing of the state 19, the A multiplexer 125 is switched to the input terminal 1, whereby the first Q channel data Im (S ₀ ) is transferred to the multiplier register 129. At this time, since the B multiplexer 126 is switched to the input terminal 1, the Q channel data Im (S ₀ ) is transferred to the multiplicand register 130. Further, at an intermediate timing of the state 19, the I multiplexer 155 is switched to the input terminal 1.

In the state 20, the multiplier 131
The Q channel data Im (S ₀ ) is multiplied by the Q channel data Im (S ₀ ), and the multiplication result data Im
² (S ₀ ) is output to the register 132. Since the initial value write signal C3 of the accumulator 157 rises at the start of the state 20, the initial value of the accumulator 157 is the first I channel weighting factor Re (F ₀ ) input from the input terminal B at the previous time. is set to p. At this time,
The upper 8 bits of data of the I channel weighting factor Re (F ₀ ) p are transferred from the I channel weight RAM 161 to the accumulator 157 via the register 156 as lower 8 bits of data. Here, the previous data such as the previous second weighting coefficient is distinguished by adding p after the sign. Here, the data transferred to the accumulator 157 via the register 156 is, as described above, the upper 8-bit data is transferred as the lower 8-bit data. Re (F
₀ ) Data obtained by multiplying p by 1 / 127１ ／ 0.007874. In the figure, 0.007874 × Re (F _n ) p and 0.007874 × Im (F _n ) p are indicated as Δd. Since the data of the accumulator 133 has been reset to 0 in the state 19, the accumulator 133
Adds 0 and the multiplication result data Re ² (S ₀ ) multiplied by the multiplier 131 in the state 19, and outputs the accumulated addition output data Re ² (S ₀ ) from the intermediate timing of the state 20 to the state 21. Output at an intermediate timing.

Further, at an intermediate timing of the state 20, the C multiplexer 127 is switched to the input terminal 2 and the Q channel vector data I is stored in the multiplier register 129.
m (Za) is transferred, the D multiplexer 128 is switched to the input terminal 1, and the normalization coefficient K is transferred to the multiplicand register 130. Also, at an intermediate timing of the state 20, the A multiplexer 125 and the B multiplexer 1
26 are switched to the input terminal 0.

In state 21, multiplier 131 outputs Q
Channel vector data Im (Za) and normalization coefficient K
And the multiplication result data K · Im (Z), that is, the I channel data Re of the final output vector data Z
(Z) is output. The accumulator 133 adds the accumulative addition output data Re ² (S ₀ ) and the multiplication result data Im ² (S ₀ ) multiplied by the multiplier 131 in the state 20, and starts the state from an intermediate timing of the state 21. 22
At the middle timing of the cumulative addition output data Re.
(S ₀ ² ) = Re ² (S ₀ ) + Im ² (S ₀ ) is output. Further, the accumulator 157 calculates the delta Δd input to the input terminal A from the previous first I-channel weighting factor Re (F ₀ ) p, which is the initial value, based on the addition / subtraction control signal C2.
Is accumulated by subtracting
(F ₀ ) p−Δd is output to the register 158 from the middle timing of the state 21 to the middle timing of the state 22. At the intermediate timing of the state 21, the B multiplexer 126 is switched to the input terminal 1 and the D multiplexer 128 is switched to the input terminal 2, and the first Q channel data Im is stored in the multiplicand register 130.
(S ₀ ) is transferred, the C multiplexer 127 is switched to the input terminal 0, and the first I
Channel data Re (S ₀ ) is transferred. Also, at an intermediate timing of the state 21, the I multiplexer 15
5 is switched to the input terminal 0, and the cumulative addition data Re (S ₀ ² ) of the cumulative adder 133 is transferred to the register 156.

In state 22, accumulator 133
Are reset to 0 at the start of the state 22. The multiplier 131 outputs the I channel data Re.
(S ₀₎ and Q channel data Im (S ₀₎ and then outputs the multiplication result data _{Re (S 0) · Im (} S 0). The accumulative adder 157 adds the accumulative addition data Re (F ₀ ) p−Δd to the I-channel data Re (S ₀ ) input to the input terminal A, based on the addition / subtraction control signal C 2. And the cumulative addition data Re
(F ₀ ) p−Δd + Re (S ₀ ) is output to the register 158 at an intermediate timing of the state 22. Here, the cumulative addition data Re (F ₀ ) p−Δd + Re (S ₀ ) can be expressed by the following Expression 34. In Expression 34, α is 0.992126 used in Expression 27.

[0185]

Re (F ₀ ) p−Δd + Re (S ₀ ) = Re (S ₀ ) + (1−0.007874) Re (F ₀ ) p = Re (S ₀ ) + α · Re (F ₀ ) p

As is apparent from _equations (27) and (34), the cumulative addition data Re (F ₀ ) p−Δd + Re (S ₀ ) is a real part of the updated second weighting factor F (a ₀ W ₀ ), that is, I
This is the channel weighting factor Re (F ₀ ). That is, R
e (F ₀ ) p−Δd + Re (S ₀ ) = Re (F ₀ ). Therefore, in FIG. 24, the I-channel weighting factor Re (F ₀ ) is described in the column of the output data of the accumulator 157. Then, at the end of the state 22, the write enable signal WE1 rises and is written to the I-channel wait RAM 161 at the address specified by the first channel number data. Further, at the middle timing of the state 22, the A multiplexer 12
5 is switched to the input terminal 0 and the multiplier register 129 is set to 1
The Qth channel data Im (S ₀ ) is transferred, and
The multiplexer 126 is switched to the input terminal 0 and the multiplicand register 130 stores the first I-channel data Re.
(S ₀ ) is transferred. At an intermediate timing of the state 22, the L multiplexer 163 and the I multiplexer 155
Are switched to the input terminal 1.

In state 23, multiplier 131 outputs
The Q channel data Im (S ₀ ) is multiplied by the I channel data Re (S ₀ ), and the multiplication result data Im (S ₀ )
• Output Re (S ₀ ) to the register 132. The accumulator 133 adds the multiplication result data Re (S ₀ ) · Im (S ₀ ) input from the multiplier 131 via the register 132 to 0 and accumulative addition output data Re (S ₀ ) · Im.
(S ₀ ) is output. At the start of the state 23, the initial value write signal C3 of the accumulator 157 rises, so that the initial value of the accumulator 157 is Im, which is the previous first Q channel weight coefficient input from the input terminal B.
(F ₀ ) is set to p. At this time, the upper 8 bits of data of the previous first Q channel weighting factor Im (F ₀ ) p are stored in the lower 8 bits from the Q channel weight RAM 162.
The data is transferred to the accumulator 157 via the register 156 as bit data. Here, the data transferred to the accumulator 157 via the register 156 is such that upper 8 bits of data are transferred as lower 8 bits of 16 bits of input data and 0 as upper 8 bits of the input data. Since it is input, the previous first Q channel weighting factor Im (F ₀ ) p is 1/127 ≒ 0.0
This is data multiplied by 07874. In addition, state 2
At an intermediate timing of 3, the A multiplexer 125 is switched to the input terminal 0.

In state 24, accumulator 133
Is the cumulative addition output data Re (S
₀ ) · Im (S ₀ ) and multiplier 131 in state 23
From the multiplication result data Im (S ₀ ) · Re (S ₀ ) from the intermediate timing of the state 24.
At the intermediate timing of the cumulative addition data Im (S ₀ ² ) = R
e (S ₀ ) · Im (S ₀ ) + Im (S ₀ ) · Re (S ₀ ). Further, the accumulator 157 subtracts the delta Δd input to the input terminal A from the previous first Q channel weighting coefficient Im (F ₀ ) p, which is the initial value, based on the addition / subtraction control signal C2. It accumulates and outputs the accumulated addition data Im (F ₀ ) p−Δd to the register 158 at an intermediate timing of the state 24. At an intermediate timing of the state 24, the A multiplexer 125 is switched to the input terminal 2, and the second I-channel data Re (S ₁ ) is transferred to the multiplier register 129. Further, since the B multiplexer 126 has been switched to the input terminal 0 and the D multiplexer 128 has been switched to the input terminal 2, the first I channel data Re (S ₀ ) is transferred to the multiplicand register 130. The E multiplexer 151 is switched to the input terminal 1 at an intermediate timing of the state 24, and the second channel number data is input to the address terminal of the I-channel wait RAM 161. At an intermediate timing of the state 24, the I multiplexer 155 is switched to the input terminal 0, and the cumulative addition data Im (S ₀ ² ) of the cumulative adder 133 is transferred to the register 156.

In state 25, accumulator 133
Are reset to 0 at the start of the state 25. The multiplier 131 outputs the I channel data Re.
(S ₁ ) is multiplied by the I-channel data Re (S ₀ ) to output multiplication result data Re (S ₀ ) · Re (S ₁ ). The accumulator 133 is reset at the start of the state 25. The accumulative adder 157 generates the accumulative addition data Im based on the addition / subtraction control signal C2.
(F ₀ ) p−Δd and Im input to input terminal A
(S ₀ ² ) and the accumulated data Im (F ₀ ) p−Δd + Im (S ₀ ² ).
5 to the register 158 at an intermediate timing. Here, the cumulative addition data Im (F ₀ ) p−Δd + Im (S ₀
² ) can be expressed by the following equation 35. In Expression 35, α is 0.992126 used in Expression 27.

[0190]

Im (F ₀ ) p−Δd + Im (S ₀ ² ) = Im (S ₀ ² ) + (1−0.007874) Im (F ₀ ) p = Im (S ₀ ² ) + α · Im (F ₀ ) p

[0191] As is apparent from the number 27 to the number 35, in the imaginary part of the cumulative data _{Im (F 0) p-Δd} + Im (S 0 2) and the second weighting factor F which is updated (a ₀ W ₀₎ is there. That is, Im (F ₀ ) p−Δd + Im (S ₀ ² ) = Im
(F ₀ ). Therefore, in FIG. 25, the column of the output data of the accumulator 157 describes the updated Q channel weighting coefficient Im (F ₀ ). Then, at the end of the state 25, the enable signal WE2 rises and is written to the address specified by the first channel number data of the Q channel wait RAM 162. At an intermediate timing of the state 25, the A multiplexer 125 is switched to the input terminal 3, the Q channel data Im (S ₁ ) is transferred to the multiplier register 129, the B multiplexer 126 is switched to the input terminal 1 and the multiplicand register 130 receives the Q signal. Channel data Im
(S ₀ ) is transferred. At an intermediate timing of the state 25, the L multiplexer 163 is switched to the input terminal 0, and the K multiplexer 168 is switched to the input terminal 1.

Similarly, states 26, 27, and 2
In step 8, the multiplication result data Re (S ₀ ) · Re (S ₁ ) and the multiplication result data Im (S ₁ ) · Im (S ₀ ) are cumulatively added to calculate the cumulative addition data Re (S ₀ S ₁ ). Then, the second I-channel weighting coefficient Re (F ₁ ) is calculated, and in the states 29, 30, and 31, the multiplication result data R
e (S ₁ ) · Im (S ₀ ) and multiplication result data Im (S ₁ )
Re (S ₀ ) is cumulatively added and the cumulative added data Im
(S ₀ S ₁ ) is calculated, the second Q-channel weighting coefficient Im (F ₁ ) is calculated, and the second Q-channel weighting coefficient Im (F ₁ ) is calculated.
, The weight coefficient F (a ₀ W ₁ ) is updated. In states 32, 33 and 34, the multiplication result data Re (S ₂ ) · R
e (S ₀ ) and multiplication result data Im (S ₂ ) · Im (S ₀ )
Are cumulatively added to calculate the cumulative addition data Im (S ₀ S ₁ ), and the third I-channel weight coefficient Re (F ₂ )
Is performed, and in states 35, 36, and 37,
The multiplication result data Re (S ₂ ) · Im (S ₀ ) and the multiplication result data Im (S ₂ ) · Re (S ₀ ) are cumulatively added to calculate the cumulative addition data Im (S ₀ S ₂ ). The calculation of the third Q-channel weighting factor Im (F ₂ ) is executed, and the third second weighting factor F (a ₀ W ₂ ) is updated. Further, in states 38, 39 and 40, the multiplication result data R
e (S ₃ ) · Re (S ₀ ) and multiplication result data Im (S ₃ )
Im (S ₀ ) is cumulatively added and the cumulative added data Re
(S ₀ S ₃ ) is calculated, and a fourth I-channel weighting factor Re (F ₃ ) is calculated.
At 42 and 43, the multiplication result data Re (S ₃ ) · Im
(S ₀ ) and the multiplication result data Im (S ₃ ) · Re (S ₀ ) are cumulatively added to calculate the cumulative addition data Im (S ₀ S ₃ ), and the fourth Q channel weighting factor Im (F ₃ ) is executed and the fourth second weighting factor F (a ₀
W ₃ ) is updated.

Here, at an intermediate timing of the state 42, the C multiplexer 127 is switched to the input terminal 3, the E multiplexer 151 is switched to the input terminal 0, and the L multiplexer 163 is switched to the input terminal 0. As a result, the I-channel weight RAM 16
The I-channel weight coefficient Re (F ₀ ) of the address designated by the first channel number data of 1 is read and transferred to the multiplier register 129. Further, at an intermediate timing of the state 42, the D multiplexer 128 is switched to the input terminal 0, so that the multiplicand register 13
The I-channel weight coefficient Re (F ₀ ) is also transferred to ₀ .

Then, in state 43, the multiplier 1
31 multiplies the I-channel weighting factor Re (F ₀ ) by the I-channel weighting factor Re (F ₀ )
e (F ₀ ) · Re (F ₀ ) is output to the register 132.
Also, at the start timing of the state 43, the reset signal R1 rises, and the accumulator 133 is reset. Further, since the E multiplexer 151 is switched to the input terminal 1 at an intermediate timing of the state 43,
The I-channel weight coefficient Re (F ₁ ) of the address specified by the second channel number data of the I-channel weight RAM 161 is read out and the multiplier register 129 is read.
And the multiplicand register 130 have the I-channel weighting factor Re
(F ₁ ) is transferred. As described above, states 42 and 43
Then, the process of step S6 in the flowchart of FIG. 19 is executed, and the process of step S9 is executed.

In state 44, multiplier 131 outputs I
The channel weighting factor Re (F ₁ ) is multiplied by the I channel weighting factor Re (F ₁ ), and the multiplication result data Re (F ₀ )
• Output Re (F ₀ ) to the register 132. The accumulative adder 133 adds the multiplication result data Re (F ₀ ) · Re (F ₀ ) of the multiplier 131 in the state 43 to 0 and accumulative addition output data T 1 = Re (F ₀ ) · Re.
(F ₀ ) is output. Since the E multiplexer 151 is switched to the input terminal 2 at an intermediate timing of the state 44, the I channel weight coefficient Re (F ₂ ) of the address specified by the third channel number data of the I channel weight RAM 161 is read. The I-channel weight coefficient Re (F ₂ ) is transferred to the multiplier register 129 and the multiplicand register 130.

Similarly, in states 45 and 46, multiplication result data Re (F ₂ ) · Re (F ₂ ) and multiplication result data Re (F ₃ ) · Re (F ₃ ) are output, respectively. The cumulative adder 133 outputs the cumulative addition output data T2 = T1 + Re (F ₁ ) · Re (F ₁ ) from the intermediate timing of the state 45 to the intermediate timing of the state 46, and from the intermediate timing of the state 46 to the state 47. At the intermediate timing of T3 = T2 + Re
(F ₂ ) · Re (F ₂ ) is output. Here, state 4
5, the F multiplexer 152 is switched to the input terminal 0 at the intermediate timing of the state 46, and the L multiplexer 163 is switched to the input terminal 1 at the intermediate timing of the state 46.
The Q channel weighting coefficient Im (F ₀ ) of the address designated by the first channel number data is read and transferred to the multiplier register 129 and the multiplicand register 130.

In state 47, multiplier 131 outputs Q
The channel weighting factor Im (F ₀ ) is multiplied by the Q channel weighting factor Im (F ₀ ), and the multiplication result data Im (F ₀ )
· Im a (F ₀₎ into the register 132. The accumulative adder 133 adds the accumulative addition output data T3 and the multiplication result data Re (F ₃ ) · Re (F ₃ ) to obtain a state 47.
The output of the cumulative addition from the intermediate timing in the middle of the timing of the state 48 data _{T4 = T3 + Re (F 3} ) · R
e (F ₃ ) is output. At an intermediate timing of the state 47, the F multiplexer 152 is switched to the input terminal 1, and the Q channel weight coefficient Im (F ₁ ) of the address specified by the second channel number data in the Q channel weight RAM 162 is read. And transferred to the multiplier register 129 and the multiplicand register 130.

Similarly, in states 48, 49, and 50, respectively, multiplication result data Im (F ₁ ) · Im
(F ₁ ), multiplication result data Im (F ₂ ) · Im (F ₂ ),
Multiplied result data Im (F ₃ ) · Im (F ₃ ) is output. The cumulative adder 133 outputs the cumulative addition output data T5 = T4 + Im (F ₀ ) · Im (F ₀ ) from the intermediate timing of the state 48 to the intermediate timing of the state 49, and outputs the state 50 from the intermediate timing of the state 49 to the state 50.
Cumulative output data T6 = T5 +
Im (F ₁ ) · Im (F ₁ ) is output, and the accumulated addition output data T7 = T6 + Im (F ₂ ) · Im is output from the middle timing of the state 50 to the middle timing of the state 51.
(F ₂ ) is output. Further, in state 51, the cumulative adder 133 adds the cumulative addition output data T7 and the multiplication result data Im (F ₃ ) · Im (F ₃ ) in state 50, and the cumulative addition output data T8 = T7 + Im (F ₃ )
Output Im (F ₃ ). Here, the cumulative addition output data T8 is a coefficient Ka expressed by Expression 30.

Since the latch trigger signal of the intermediate register 134-3 rises at the start timing of the state 52, the coefficient Ka, which is the accumulated addition output data D8, is latched in the intermediate register 134-3. The same is repeated thereafter, and the final output vector data Z that has been subjected to maximum ratio combination and standardized is output to the demodulator 7.

As described above in detail, the MRC processing shown in the flowchart of FIG. 19 can be executed by the MRC processing circuit 203 shown in FIGS.

The I channel data Re (Z) of the final output vector data Z output from the MRC processing circuit 203
And the Q channel data Im (Z) are input to the demodulator 7 and subjected to, for example, PSK demodulation, and the demodulated data digital signal is output from the demodulator 7 as a reception data signal.

The reception signal processing device for an array antenna of this embodiment includes a multi-beam combining process (hereinafter, referred to as a multi-beam process) by the DSPs 5-1 to 5-16.
Beam selection processing and phase shift processing by the beam selection circuit 201 and the phase shift circuit 202, and M
As shown in FIG. 31, the RC processing is sequentially executed by pipeline processing at time intervals between each sampling.
In FIG. 31, the multi-beam processing includes other quasi-orthogonal detection processing by the DSPs 5-1 to 5-16 and low-frequency filtering processing in addition to the multi-beam processing by Fourier transform.

That is, as shown in FIG. 31, during the time interval from the sampling of the n-th received signal to the sampling of the next (n + 1) -th received signal, the n-th multi-beam processing and (n− 1) After executing the first beam selection process and the phase shift process and the (n-2) th MRC process, the sampling of the (n + 1) th received signal from the (n + 1) th received signal sampling time (N + 1) -th multi-beam processing and n
The second beam selection processing and the phase shift processing and the (n-1) th MRC processing are executed. Next, at the time interval from the (n + 2) th sampling of the received signal to the (n + 3) th sampling of the received signal, (n + 2)
The third multi-beam processing, the (n + 1) th beam selection processing and phase shift processing, and the n-th MRC processing are executed. Thereafter, these processes are repeatedly executed by pipeline processing. After the execution of each process, the I-channel data and the Q-channel data of the received signal, which are the results of the processing for each sampling of the received signal, are output to the demodulation circuit 7.

As described above, the beam selection circuit 201, the phase shift circuit 202, and the MRC processing circuit 203 in the embodiment are all constituted by hardware circuits, and furthermore, as shown in FIG. Since the selection processing, the phase shift processing, and the MRC processing are sequentially pipelined with the processing time staggered, these processings can be executed at a higher speed as compared with the conventional example. Can be processed in real time. Moreover, the circuit configuration is simpler than the conventional example.

The reception signal processing apparatus for an array antenna according to the above-described embodiment includes the beam selection circuit 201 and selects the power data of four reception beams having large power data to perform the MRC processing. Processing circuit 203
Can be shortened and the circuit configuration can be simplified.

[0206] In the reception signal processing apparatus for an array antenna of the above embodiments, MRC processing circuit 203, by multiplying the second weighting factor F (a ₀ W _n) and each phase shift data S _n, each phase shift data has an amplitude proportional to the power of S _n and the reference phase shift data S ₀ and by adding the in-phase reduction by a plurality of vectors X _n and outputs. This gives M
Since the RC processing circuit 203 can output the final output vector data Z subjected to the maximum ratio combination as the received signal data, the received power / noise power ratio CN of the received signal data is obtained.
R can be maximized.

[0207] In the reception signal processing apparatus for an array antenna of the above embodiments, MRC processing circuit 203, since the output was normalized by normalization coefficients K, four total power of phase data S ₀ to S ₃ It is possible to output the normalized final output vector data Z.

In the array antenna reception signal processing device of the above embodiment, the MRC processing circuit 203 is provided with the multiplier 131 and the accumulators 133 and 157, so that the multiplier 131 and the accumulator 133 , 157 can be operated simultaneously. As a result, FIG.
The normalization process of the vector data Za in step S3 in the flowchart of FIG. 9 is executed in real time with the calculation process of the vector data Za in step S2 and the calculation process of the second weighting factor F (a ₀ W _n ) in steps S4 to S7. Therefore, the MRC process can be executed at a high speed.

In the reception signal processing device for an array antenna of the above embodiment, the MRC processing circuit 203 includes registers such as channel number registers 111 to 114 and A
A multiplexer such as the multiplexer 125;
31 and digital circuits such as the accumulators 133 and 157, so that an integrated circuit can be formed and the size can be reduced.

In the array antenna reception signal processing device of the above embodiment, since the MRC processing circuit 203 includes the reset signal generation circuit 300, the antenna corresponding to the power data of a plurality of beam-selected reception signals. When the channel number of the element changes, it is possible to prevent the convergence time in the MRC processing from becoming long, and it is unnecessary when the power data of the received signal is a noise level close to zero or a level corresponding thereto. It is possible to accurately execute the subsequent MRC process by removing the power data of the received signal.

In the received signal processing apparatus for an array antenna according to the above embodiment, the MRC processing circuit 203
Since the low-pass filters 302, 312, 322, and 332 are provided and the maximum ratio synthesis is performed using the second weighting coefficient F (a ₀ W _n ) after the filtering, the maximum ratio synthesis with less noise is performed. Can be.

As described above, since each DSP simultaneously executes processing including quasi-orthogonal detection, transversal FIR low-pass filtering, and FFT operation in the spatial domain, it is possible to execute at extremely high speed. . In the DSP, processing including quasi-orthogonal detection, transversal FIR low-pass filtering, and FFT operation to the spatial domain is performed. Compared with the signal processing of the array antenna, the device of the present embodiment has an advantage that a close multi-beam can be realized with a higher signal-to-noise ratio.

As described above, in the embodiment, as a method for efficiently executing the arithmetic processing including the multi-beam forming, two-dimensional two-dimensional axes of the physical arrangement of the antenna elements of the array antenna, ie, the X-axis In order to efficiently transmit and receive data calculated by the DSPs in the direction and the Y-axis direction between the DSPs, four
One data bus 101 to 104 and four data buses 105 to 108 in the Y-axis direction are used. In the above-described FFT operation processing, it is necessary to combine received signals received by the individual antenna elements and to convert the spatial information, so that the received data calculated by each DSP is
It is necessary to exchange data between the SPs. After the calculation by another DSP, the calculation result transmitted / received via the data buses 101 to 104 is used, so that the FFT operation can be executed efficiently. As a result, it is possible to increase the use efficiency of the DSP in each operation cycle. That is, by using data buses 101 to 116 dedicated to the FFT operation between the DSPs to transmit and receive data necessary for the operation, the operating rate of each DSP can be maximized. In other words, the multi-digital signal processor is configured so that the received signal processing can be distributed to all the DSPs.

As described above, the DSPs 5-1 to 5-1
As shown in FIG. 3, the ASIC arithmetic circuits of −16 are connected by using grid-shaped buses 101 to 116 to perform arithmetic processing such as a predetermined multi-beam synthesis.
All ASICs are executed in a distributed manner in the C operation circuit.
It is possible to increase the operation time of the ASIC operation circuit by increasing the time during which the operation circuit performs the operation at the same time. As a result, it is possible to provide a received signal processing device for an array antenna which can execute arithmetic processing for multi-beam formation at a higher speed than the conventional example and has a simple circuit configuration.

The array antenna received signal processing apparatus of the present embodiment does not depend on the carrier frequency,
The same received signal processing device can be used for a band.
That is, even if the carrier frequency is changed, if the communication data rate is the same, there is no effect on the operation algorithm of the digital signal processing device.

The same circuit can be used by adapting the frequency at which the DSP operates to an arbitrary data rate. This means that the operating frequency of the digital reception signal processing device is determined with respect to the actual data rate. This can be dealt with by changing only the operating frequency without changing it.

<Modification> In the array antenna reception signal processing apparatus of the above embodiment, the beam selection circuit 20
1 and the phase shift circuit 202, but the present invention is not limited to this, and the MRC processing circuit 203 is directly connected to the IRC
It may be configured to input channel and Q channel space data. Even with the above configuration, the same effects as in the embodiment can be obtained.

Further, in the received signal processing device for an array antenna of the above embodiment, the MRC processing circuit 203
Although the vector data Za is normalized using the normalization coefficient K to output the final output vector data Z, the present invention is not limited to this, and the vector data Za may be directly output. . Even with the above configuration, the same effects as in the embodiment can be obtained.

Furthermore, the reception signal processing device for an array antenna according to the above-described embodiment includes the comparison circuit 204 and the reset signal generation circuit 300. However, the present invention is not limited to this. Generating circuit 300
It may be configured without providing. Even with the above configuration, the same effects as those of the embodiment can be obtained.

Further, in the reception signal processing apparatus for an array antenna of the above embodiment, the MRC processing circuit 20
3 is an IIR low-pass filter 302, 312, 322,
332, but the present invention is not limited to this.
IR low-pass filters 302, 312, 322, 332
It may be configured without providing. Even with the above configuration, the same effects as in the embodiment can be obtained.

In the above embodiments, a reception signal processing apparatus for processing a plurality of high-frequency reception signals received by an array antenna composed of a plurality of antenna elements arranged in a two-dimensional matrix is described. However, the present invention is not limited to this, and the present invention relates to a reception signal processing device for processing a plurality of high-frequency reception signals received by an array antenna including a plurality of antenna elements arranged in a one-dimensional linear shape. Can be applied. in this case,
There is only one data bus connecting each DSP.

In the above embodiment, the beam selecting circuit 201 having the larger power data has
Although power data of a plurality of reception beams are selected, the present invention is not limited to this, and power data of at least two or more reception beams may be selected. Even with the above configuration, the same effects as those of the embodiment can be obtained.

[0223]

As described above, according to the received signal processing apparatus for an array antenna according to the first aspect of the present invention, an array antenna composed of a plurality of antenna elements closely arranged in a predetermined arrangement shape. Array signal receiving means for converting a plurality of received signals respectively received by the respective antenna elements into two orthogonal baseband data orthogonal to each other using a common local oscillation signal. In the apparatus, the conversion means (5)
A maximum ratio combining circuit (203) for maximum ratio combining and outputting as a standardized reception signal based on each of the two orthogonal baseband data converted by the maximum ratio combining circuit (203). Based on each of the two orthogonal baseband data converted by the converting means (5), the first received by the antenna element of the predetermined reference
And first arithmetic means (301, 311) for calculating a plurality of first data which are complex conjugate products of the respective received signals received by the respective antenna elements including the reference antenna element. , 321, 331) and the second
A second calculating means (304, 31) for calculating a plurality of second data which are each products of the received signal and the first data.
4, 324, 334), a third calculating means (306) for calculating the third data by adding the plurality of second data, and a plurality of data by squaring each of the first data. The fourth calculating means (3) for calculating the fourth data of
05, 315, 325, 335) and fifth arithmetic means (307) for calculating fifth data by adding the plurality of fourth data, and dividing 1 by the square root of the fifth data A sixth calculating means for multiplying the third data by the calculated sixth data to calculate the seventh data as a result of the multiplication to output a maximum ratio-synthesized and standardized reception signal (308), and the maximum ratio combination processing circuit (203) provides a table consisting of sixth data, which is a value obtained by dividing 1 by the square root of the fifth data with respect to various fifth data. First storage means (136) for storing in advance, and second storage means (1) for temporarily storing first data output from the accumulator (133).
61, 162) and third storage means (1) for temporarily storing third data output from the accumulator (133).
34-1 and 134-2), fourth storage means (134-3) for temporarily storing fifth data output from the accumulator (133), and a fourth storage means (134-3) for each of the second received signals. A first multiplexer (125) for selectively switching and outputting one of the orthogonal baseband data, and selectively switching and outputting one of the two orthogonal baseband data of the first received signal; A second multiplexer (126) that performs
5) and the second storage means (16)
1, 162) for selectively switching between the first data output from the third storage means (134-1, 134-2) and the third data output from the third storage means (134-1, 134-2). 127), the data output from the second multiplexer (126), the first data output from the second storage means (161, 162), and the data output from the fourth storage means (134-3). A fourth multiplexer (128) for selectively switching and outputting the sixth data output via the first storage means (136);
A multiplier (131) for multiplying the data output from the third multiplexer (127) with the data output from the fourth multiplexer (128); and a multiplier (131) at a predetermined timing. ) Are cumulatively added, and the third data or the fifth data of the cumulative addition result is stored in the third storage unit (1).
34-1 and 134-2) or the fourth storage means (13
4-3), or a cumulative adder (133) which outputs the first data output from the multiplier (131) to the second storage means (161, 162) without cumulative addition. , The first computing means (301, 311,
321, 331) and the second arithmetic means (304, 31).
4,324,334) and the fourth arithmetic means (305,
315, 325, 335) and the sixth arithmetic means (30
8) is executed by the multiplier (131), and the addition processing in the third arithmetic means (306) and the fifth arithmetic means (307) is executed by the accumulator (133). Control means (180) for executing the arithmetic processing in a time-division multiplex manner and controlling the multiplier (131) to output a reception signal that has been maximally combined and standardized. It is composed. Therefore, according to the present invention, the circuit configuration is simple and suitable for integration, and a received signal having the maximum ratio combined can be output, and the received power to noise power ratio CNR of the received signal can be increased.

[0224] According to the reception signal processing device for an array antenna of the second aspect, in the reception signal processing device for an array antenna of the first aspect, the maximum ratio combining processing circuit (203) further comprises the first ratio signal processing circuit. Low-pass filtering means (302, 312, 322, 3
32), and the maximum ratio combining circuit (203) includes:
The low-pass filtering means (302, 312, 322, 332)
By outputting the first data after low-pass filtering to the second arithmetic means (304, 314, 324, 334) or the fourth arithmetic means (305, 315, 325, 335). The second data or the fourth data is calculated. Therefore, according to the present invention, since the low-pass filtering means (302, 312, 322, 332) is provided, the fluctuation of the amplitude of the first data can be suppressed, and the maximum ratio combining with less noise is achieved. The received signal can be output.

Further, according to the third aspect of the present invention, in the array antenna reception signal processing device according to the first or second aspect, the predetermined number of antenna elements having a large reception power can be used. A beam selection circuit (201) for outputting each channel number data; and a phase shift circuit (202) for shifting the phase of each baseband data of each reception signal corresponding to the channel number data to the center of the array antenna. Because it has
The maximum ratio combining processing circuit can execute the maximum ratio combining of the second received signal shifted to the center of the array antenna at high speed.

According to the fourth aspect of the present invention, in the array antenna reception signal processing device according to the first, second, or third aspect, the selected plurality of channel number data may A comparison circuit (204) for outputting each state data indicating whether or not each corresponding power data is less than a predetermined threshold value, and a corresponding to the channel number data determined that the power data is less than the threshold value And a reset circuit (300) for resetting the first data to be reset to zero when the power data of the received signal is a noise level close to zero or a level corresponding thereto. And the maximum ratio combining process can be executed accurately.

[0227]

[0228]

[0229]

[Brief description of the drawings]

FIG. 1 is a block diagram of a reception signal processing device for an array antenna according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating functions of each DSP of FIG. 1;

FIG. 3 is a block diagram showing a connection between 16 DSPs in FIG. 1;

FIG. 4 is a block diagram showing a circuit of each DSP of FIG. 1;

FIG. 5 is a first timing chart showing the operation of each DSP of FIG. 1;

FIG. 6 is a second timing chart showing the operation of each DSP of FIG. 1;

FIG. 7 is a third timing chart showing the operation of each DSP of FIG. 1;

FIG. 8 is a fourth timing chart showing the operation of each DSP of FIG. 1;

FIG. 9 is a fifth timing chart showing the operation of each DSP of FIG. 1;

FIG. 10 is a block diagram illustrating a beam selection circuit 201 of FIG. 1;

FIG. 11 is a block diagram showing a phase shift circuit 202 of FIG. 1;

FIG. 12 is a plan view showing a beam phase shift process in the phase shift circuit 202 of FIG. 11;

13 is a graph showing the angle of the rotation vector of the FFT operation to each beam with respect to the antenna position of the array antenna before the phase shift processing of the phase shift circuit 202 of FIG. 11;

14 is a graph showing the angle of the rotation vector of the FFT operation to each beam with respect to the antenna position of the array antenna after the phase shift processing of the phase shift circuit 202 of FIG. 11;

FIG. 15 is a block diagram showing a comparison circuit 204 of FIG. 1;

16 is a block diagram illustrating each processing function of the MRC processing circuit 203 in FIG.

FIG. 17 is a block diagram showing in detail a first portion when the MRC processing circuit 203 of FIG. 1 is configured by a digital circuit.

FIG. 18 is a block diagram showing in detail a second part when the MRC processing circuit 203 of FIG. 1 is configured by a digital circuit.

FIG. 19 is a flowchart showing the flow of an MRC process executed by the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 20 is a first timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 21 is a second timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 22 is a third timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 23 is a fourth timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 24 is a fifth timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 25 is a sixth timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 26 is a seventh timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 27 is an eighth timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 28 is a ninth timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

FIG. 29 is a tenth timing chart showing the operation of the MRC processing circuit 203 shown in FIGS. 17 and 18.

30 is an eleventh timing chart showing the operation of the MRC processing circuit 203 shown in FIG. 17 and FIG.

FIG. 31 is a timing chart showing pipeline processing in the reception signal processing device for an array antenna of FIG. 1;

[Explanation of symbols]

1-1 to 1-16: antenna element; 2-1 to 2-16: down converter; 3-1 to 3-16: band-pass filter; 4-1 to 4-16: A / D converter; 1 to 5-16: DSP, 7: Demodulator, 11: Synchronous distributor, 12, 22: Multiplier, 13, 23: FIR low-pass filter, 14, 24: Fast Fourier transformer, 15: Sum of squares circuit Reference Signs List 20: Local oscillator, 21: π / 2 phase shifter, 31: Input register, 32: Weight ROM for beam forming, 33: Weight ROM for FFT, 34: Input multiplexer, 35: Data multiplexer, 36: Multiplexer and accumulator, 37: Register, 51a, 51b: Post-detection register, 52a, 52b: FIR register, 53a, 53b: FFT primary register 54a, 54b ... Spatial data register, 55: Power data register, 56a, 56b: Distributor, 61a, 61b: FIFO memory, 62: FIR output register, 63: Spatial data output register, 64: FFT multiplexer, 65: FFT output register, 101 through 108: data bus, 111, 112, 113, 114: channel number register, 121a, 121b, 122a, 122b, 123a,
123b, 124a, 124b ... input data register, 125 ... A multiplexer, 126 ... B multiplexer, 127 ... C multiplexer, 128 ... D multiplexer, 129 ... multiplier register, 130 ... multiplicand register, 131 ... multiplier, 132 ... register, 133 ... Accumulators, 134-1, 134-2, 134-3 ... Intermediate registers, 135-1, 135-2 ... Output registers, 136 ... Table ROM, 141,142,143,144 ... Status data registers, 151 ... E multiplexer, 152 F multiplexer, 153 G multiplexer, 154 H multiplexer, 155 I multiplexer, 156, 158 register, 157 accumulator, 159 J multiplexer, 161 I channel weight RA M, 162: Q channel weight RAM, 163: L multiplexer, 164, 165: Channel comparator, 166, 167: NOR gate, 168: K multiplexer, 201: Beam selection circuit, 202: Phase shift circuit, 203: MRC processing circuit , 204... Comparison circuit, 210-1 to 210-8, 211-1 to 211-
4,212-1,212-2,213,241,24
2, 243, 244... Comparators, 221a, 221b, 222a, 222b, 223a,
223b, 224a, 224b: input data register, 225: input data multiplexer, 226: multiplexer, 227: product-sum operation unit, 228: register, 229a, 229b: output data register, 231 to 234: channel number multiplexer, 235: channel Number multiplexer, 236: phase shift data ROM, 237: ReIm multiplexer, 300: reset signal generation circuit, 301, 311, 321, 331, 304, 314, 3
24,334 ... multiplier, 302, 312, 322, 332 ... IIR low-pass filter, 305, 315, 325, 335 ... square circuit, 306, 307 ... addition circuit, 308 ... standardization circuit, B1 to B4 ... Data line.

────────────────────────────────────────────────── ─── Continuing on the front page (72) Yoshio Karasawa, Inventor 5 Sanraya, Daiya, Seika-cho, Soraku-gun, Kyoto Prefecture, Japan ATR Optical Co., Ltd. Within the Radio Communication Research Laboratory (56) References JP-A-7- 235830 (JP, A) IEICE Technical Report, IEICE Technical Report P95-44, Vol. 95, No. 214, issued August 24, 1995, pp. 31-35, "Tracking characteristics of a digital beamforming antenna performing maximum ratio combining reception in beam space" (58) Fields investigated (Int. . ^7, DB name) H01Q 3/38

Claims (4)

(57) [Claims] 1. A plurality of reception signals respectively received by each antenna element of an array antenna comprising a plurality of antenna elements closely arranged in a predetermined arrangement shape and orthogonal to each other using a common local oscillation signal. In a reception signal processing device for an array antenna, comprising a conversion means (5) for converting to two orthogonal baseband data, a maximum ratio based on each two orthogonal baseband data converted by the conversion means (5). A maximum ratio combining circuit (20) that outputs a combined and standardized received signal.
3), wherein the maximum ratio combining circuit (203) is configured to perform a first reception performed by a predetermined reference antenna element based on each of the two orthogonal baseband data converted by the conversion means (5). First calculating means (301, 311, 32) for calculating a plurality of first data which are each complex conjugate products of the signal and each of the second received signals received by each of the antenna elements including the reference antenna element
, 331), and a second calculating means (3) for calculating a plurality of second data which are products of the respective second received signals and the respective first data.
04, 314, 324, 334), third calculating means (306) for calculating third data by adding the plurality of second data, and squaring each of the first data. Calculation means (305, 315, 3) for calculating a plurality of fourth data by
25, 335), a fifth calculating means (307) for calculating the fifth data by adding the plurality of fourth data, and a value obtained by dividing 1 by the square root of the fifth data. Sixth
The sixth operation means (3) which multiplies the third data by the above data to calculate the seventh data as a result of the multiplication and outputs a maximum ratio-synthesized and standardized reception signal
08), and the maximum ratio combining processing circuit (203) previously stores a table including sixth data, which is a value obtained by dividing 1 by the square root of the fifth data, for various fifth data. First storage means (136) for storing; second storage means (161, 162) for temporarily storing first data output from the accumulator (133); and accumulator (133). Storage means (134-1, 134-) for temporarily storing third data output from
2), fourth storage means (134-3) for temporarily storing fifth data output from the accumulator (133), and fourth orthogonal baseband data of the second received signals. A first multiplexer (125) for selectively switching and outputting one of the data, and a second multiplexer (125) for selectively switching and outputting one of the two orthogonal baseband data of the first received signal. 126), the data output from the first multiplexer (125), the first data output from the second storage means (161, 162), and the third storage means (134-
, 134-2) to selectively switch and output the third data outputted from the third multiplexer (12-3).
7), the data output from the second multiplexer (126), the first data output from the second storage means (161, 162), and the fourth storage means (134-
A third data which is selectively switched from the third data to the sixth data output via the first storage means (136).
A multiplexer (128) for multiplying the data output from the third multiplexer (127) by the data output from the fourth multiplexer (128); The plurality of data output from the multiplier (131) are cumulatively added, and the third data or fifth data of the cumulative addition result is stored in the third storage means (134-1, 134-2) or the third data, respectively. The data is output to the fourth storage means (134-3) or the multiplier (13
(1) a cumulative adder (133) that outputs the first data to the second storage means (161, 162) without cumulative addition; and a first arithmetic means (301, 311, 321). , 33
1) and the second arithmetic means (304, 314, 324,
334) and the fourth arithmetic means (305, 315, 32)
5,335) and the sixth arithmetic means (308) are executed by the multiplier (131), and the third arithmetic means (306) and the fifth arithmetic means (30) are executed.
7), the arithmetic processing is executed by time division multiplexing so that the accumulator (133) is executed by the accumulator (133), and the maximum ratio combined and standardized reception is performed from the multiplier (131). And a control means (180) for controlling a signal to be output. 2. The maximum ratio combining circuit (203) further comprises low-pass filtering means (302, 312, 322, 332) for low-pass filtering the first data and outputting the first data. The ratio combining circuit (203) converts the first data after low-pass filtering by the low-pass filtering means (302, 312, 322, 332) into the second arithmetic means (304, 31).
4,324,334) or the fourth arithmetic means (30
The received signal processing device for an array antenna according to claim 1, wherein the second data or the fourth data is calculated by outputting the second data or the fourth data to the array antenna (5, 315, 325, 335). 3. The received signal processing device for an array antenna further selects a plurality of predetermined antenna elements having a large received power based on the power data of each of the received signals, and assigns the selected antenna element to each of the selected antenna elements. A beam selection circuit (201) for outputting corresponding channel number data; and a baseband data of each reception signal corresponding to the channel number data based on the channel number data output from the beam selection circuit (201). And a phase shift circuit (202) for executing a phase shift process for shifting the phase of each phase to the center of the array antenna and outputting each baseband signal after the phase shift. (203) executes processing based on a plurality of phase-shifted baseband data output from the phase shift circuit (202). The received signal processing device for an array antenna according to claim 1 or 2, wherein: 4. The received signal processing device for an array antenna further determines whether each power data of each received signal corresponding to the selected plurality of channel number data is less than a predetermined threshold value. A comparison circuit (204) for outputting state data indicating whether or not the power data corresponding to the plurality of channel number data is less than a predetermined threshold value; A reset circuit (300) for resetting, to zero, first data corresponding to the channel number data for which the power data corresponding to each of the channel number data is determined to be less than the threshold value. The received signal processing device for an array antenna according to claim 1, 2 or 3, wherein: