JP3013580B2 - Orthogonal transformer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal transform apparatus for performing cosine transform or inverse cosine transform used as pre-processing or post-processing such as high-efficiency coding of an image signal or image processing.

[0002]

2. Description of the Related Art Hitherto, a high-speed algorithm has been employed in an orthogonal transform apparatus in order to reduce the hardware scale. In particular, the tendency is remarkable in the cosine transform and the inverse cosine transform that require a large number of multiplications.

FIG. 7 is a signal diagram of an 8-point high-speed cosine transform which is one of orthogonal transforms. In the figure, {y ₀ ,
, Y ₇ } are eight sets of input signals, {z ₀ ,..., Z ₇ } are eight sets of output signals, and z _i is represented as follows.

[0004]

(Equation 1)

[0005]

[Table 1]

Here, δ _i is a function that takes 1 when i is positive and takes a value cos (π / 4) when i is 0.
Now, in FIG. 7, each arrow indicates addition and subtraction, a solid arrow indicates addition, and a dotted arrow indicates subtraction (number to be subtracted). In addition, ○ and □ indicate that the number entered inside is multiplied, □ means multiplication that can be processed only by shift operation, and ○ means multiplication that cannot be calculated only by shift (hereinafter, referred to as real multiplication). I have.

FIG. 8 shows a block diagram of an orthogonal transform device for performing the orthogonal transform shown in the signal diagram of FIG. In the figure, reference numeral 1 denotes a rearranger for rearranging an input signal;
Is a butterfly operation unit for performing a butterfly operation on the output of the reordering unit 1, 3 is a reordering unit for reordering the output of the butterfly operation unit 2, 4 is a multiplier for multiplying the output of the reordering unit 3,
Reference numeral 5 denotes an adder for performing an addition process on the output of the rearranger 3, reference numeral 6 denotes a selector for selecting one of three outputs from the output of the rearranger 3, the output of the multiplier 4, and the output of the adder 5, and 7 denotes a selector 6 , A butterfly operation unit for rearranging the output of the butterfly operation unit 7, a multiplier 9 for multiplying the output of the rearranger 8, an adder 10 for adding the output of the rearranger 8, 11 is the output of the multiplier 9 and the adder 1
A selector for selecting one of the three outputs of the output of the selector 0 and the output of the rearranger 8; a butterfly operator 12 for performing a butterfly operation on the output of the selector 11; a multiplier 13 for multiplying the output of the butterfly operator 12; A rearranger 14 rearranges the output of the multiplier 13 and outputs an orthogonal transform signal. Also,
(FIG. 7) is assigned a number corresponding to the component requirement of (FIG. 8).

The operation of the orthogonal transform device shown in FIG. 8 will be described below. Input signal reordering _{{y 0, ···, y 7} } is the input signal (Fig. 7) by the reordering unit _{1 {y 0, ···, y} 3, y 7, ···, y 4} in Can be
The output of the reordering unit 1 is subjected to butterfly operation by a butterfly operation unit 2. The butterfly computing unit is a computing unit that calculates the sum and difference of two data separated by a certain sample time, and the butterfly computing unit 2 computes data four samples apart. Part of the output of the butterfly operation unit 2 is multiplied by 2C ₄ by the multiplier 4, and part of the data is added by the adder 5. Here, C _i is cos (i · π / 16).
The rearranger 3 performs rearrangement of data to be added and rearrangement for the next butterfly operation. The selector 6 selects one of the rearranger 3, the multiplier 4, and the adder 5,
It is input to the butterfly operation unit 7. The butterfly operation unit 7 performs a butterfly operation of two samples. A part of the output of the reordering unit 8 is multiplied by C ₄ or 2C ₂ or 2C ₆ by the multiplier 9, and a part of the output of the reordering unit 8 is added by the adder 10. In the selector 11, the rearranger 8 and the multiplier 9 are arranged in accordance with the algorithm shown in the signal diagram of FIG.
And one of the three outputs of the adder 10 is selected by the selector 11 and input to the butterfly operation unit 12. The butterfly operation unit 12 performs an operation on data separated by one sample, and the multiplier 13 multiplies the data by 1, 7, 8 or 2, C ₄ C ₆ or C ₄ . The results of these processes are generated in the order of {z ₀ , z ₄ , z ₂ , z ₆ , z ₁ , z ₇ , z ₃ , z ₅ } as shown in FIG. The rearranger 14 rearranges them in the order of {z ₀ ,..., Z ₇ }.

FIG. 9 is an orthogonal transform signal diagram of an inverse cosine transform which is an inverse transform of the orthogonal transform shown in FIG. FIG. 10 shows a block diagram of the orthogonal transformation device based on the signal diagram of FIG. Devices that perform the same operation are given the same numbers as in FIG.

FIG. 11 is a two-dimensional cosine transform comprising two-point cosine transform and four-point cosine transform, and FIG.
14 is a signal diagram of two-dimensional inverse cosine transform including point inverse cosine transform and four-point inverse cosine transform, and FIGS. 12 and 14 are signal diagrams of FIGS. 11 and 13, respectively. It is a block diagram of the orthogonal transformation apparatus which implements orthogonal transformation. An input signal _{{y 0, ···, y 7} } When the output signal _{{u 0,0, ···, u 3,0} , u 0,1, ···, u 3,1} The following It is represented as

[0011]

(Equation 2)

In FIG. 12 and FIG. 14, the same operations as those in FIG. 8 and FIG. 10 are denoted by the same reference numerals. The operation is clear from the signal diagrams of FIGS. 11 and 13, respectively, and the description is omitted.

[0013]

However, in the above-described orthogonal transform apparatus, a plurality of multipliers are required, and the hardware scale becomes large. In addition, since unique hardware (multiplier) is required for each orthogonal transform,
To perform a plurality of orthogonal transforms, the hardware scale is further increased.

In view of the above, an object of the present invention is to provide a means for realizing an orthogonal transform device in which the number of multipliers is reduced and hardware for realizing the orthogonal transform is simplified.

[0015]

SUMMARY OF THE INVENTION The present invention relates to a digital
Input signal consisting of eight sets of data
Fly arithmetic unit, one multiplier, and adder that performs addition and subtraction
And a sorter that sorts the order of the calculated values,
A selector for selecting one of the calculated values, and a selector for delaying the calculated value for a fixed time
With a delay to extend the output of at least two devices
Select with the selector and input to the multiplier and output to the multiplier.
Outputting a force to at least two selectors, two points cosine varying
Two-dimensional cosine transform consisting of
Or one-dimensional 8-point cosine transform or 2-point inverse cosine
Two-dimensional inverse cosine transform consisting of a transform and a four-point inverse cosine transform
Or at least two of one-dimensional 8-point inverse cosine transform
One for each of the input signal data.
You. The present invention also provides a first reordering device for reordering the order of the input signal with respect to an input signal consisting of eight sets of digitized data, and a butterfly operation comprising addition and subtraction of the output of the first reordering device. A first butterfly operation unit for performing the following, a second rearranger for rearranging the order of the output of the first butterfly operation unit, a first delay unit for delaying the output of the second rearranger for a fixed time, A first selector for selecting one of three outputs of a first delay unit output, a multiplier output, and an adder output; a second butterfly operation unit for performing a butterfly operation on the first selector output; A third rearranger for rearranging the order of the output of the second butterfly operation unit, a second delayer for delaying the output of the third rearranger for a predetermined time, an output of the second delayer, and the multiplier Output and the adder A second selector for selecting one of three forces, a third butterfly operator for performing a butterfly operation on the output of the second selector, and delaying the output of the third butterfly operator for a fixed time. A third delay device;
From the output of the third delay unit and the output of the multiplier,
A third selector for selecting one, a fourth rearranger for rearranging the order of the output of the third selector and outputting the result as an orthogonal transform signal, the output of the second rearranger and the third rearranger A fourth selector for selecting one of three outputs and an output of the third butterfly operation unit, the multiplier for multiplying the output of the fourth selector, and an output of the second reorderer. A fifth selector for selecting a set of data from two of the outputs of the third reorderer, and an adder for adding the fifth selector output; and a two-point cosine transform and four points Two-dimensional cosine transform consisting of cosine transform,
Alternatively, one of the one-dimensional eight-point cosine transform is performed for each data of the input signal.

The present invention also provides a first rearranger for rearranging the order of the input signals with respect to an input signal consisting of eight sets of digitized data, and a delay of an output of the first rearranger for a predetermined time. A first delay device to be activated, and a first delay device for selecting one of two outputs of the first delay device output and the multiplier output
And a first butterfly operation unit that performs a butterfly operation including addition and subtraction on the output of the first selector.
A second rearranger for rearranging the order of the output of the first butterfly operation unit, a second delayer for delaying the output of the second rearranger for a predetermined time, an output of the second delayer, and the multiplier A second selector for selecting one of three outputs, a subtractor output, a second butterfly operation unit for performing a butterfly operation on the second selector output, and a second butterfly operation unit output. A third rearranger for rearranging the order, a third delayer for delaying the output of the third rearranger for a predetermined time, and three outputs of the third delayer output, the multiplier output, and the subtractor output A third selector for selecting one of the following, a third butterfly operation unit for performing a butterfly operation on the output of the third selector, and a rearrangement of the order of the output of the third butterfly operation unit to obtain an orthogonal transform signal. Output fourth reorderer The first permutation output and the second reordering device output of said third reordering output 3
A fourth selector for selecting one of the outputs, the multiplier for multiplying the output of the fourth selector, and one of two outputs of the second reorderer output and the third reorderer output. A fifth selector for selecting one and the subtractor for subtracting the output of the multiplier from the output of the fifth selector, and a two-dimensional inverse cosine transform comprising two-point inverse cosine transform and four-point inverse cosine transform. One of the conversion and the one-dimensional eight-point inverse cosine conversion is performed for each data of the input signal.

Further, the present invention provides a first rearranger for rearranging the order of the input signals for an input signal consisting of eight sets of digitized data, and a delay of an output of the first rearranger for a predetermined time. A first delay device to be activated, and a first delay device for selecting one of two outputs of the first delay device output and the multiplier output
A first butterfly computing unit that performs a butterfly operation including addition and addition / subtraction on the output of the first selector, a second rearranger that rearranges the order of the output of the first butterfly computation unit, A second delay unit for delaying the output of the second rearranger for a predetermined time, a second selector for selecting one of three outputs of the second delay unit output, the multiplier output, and the adder / subtractor output; A second butterfly operation unit for performing a butterfly operation on the output of the second selector;
A third rearranger for rearranging the order of the output of the butterfly operation unit, a third delay unit for delaying the output of the third rearranger for a fixed time, the third delay unit output, the multiplier output, and the third A third selector for selecting one of the three adder / subtractor outputs, a third butterfly operator for performing a butterfly operation on the output of the third selector, and a third butterfly operator output for a predetermined time. A fourth delay unit that delays, a fourth selector that selects one of the fourth delay unit output and the multiplier output, and a fourth selector that rearranges the order of the fourth selector output to be orthogonal. A fourth rearranger that outputs a converted signal; and one of four of the first rearranger output, the second rearranger output, the third rearranger output, and the third butterfly operation unit. A fifth selector to select and the fifth selection Said multiplier for multiplying the output, the 1 to select one from three of the multiplier output and said third reordering output and the second permutation output
A fifth selector for selecting a set of data from the two outputs;
A second-dimensional cosine transform comprising two-point cosine transform and four-point cosine transform, a one-dimensional eight-point cosine transform, or a two-point inverse cosine transform; Either two-dimensional cosine transform consisting of point inverse cosine transform or one-dimensional eight-point inverse cosine transform is performed for each data of the input signal.

The present invention also provides a first rearranger for rearranging the order of the input signal with respect to an input signal consisting of eight sets of digitized data, and addition and subtraction of the output of the first rearranger. That performs butterfly operation consisting of
, A first delay unit for delaying the output of the first butterfly operation unit for a predetermined time, a first selector for selecting one of two outputs of a multiplier output and an adder output,
A second selector for selecting one of two of the first delay unit output and the first selector output, a second rearranger for rearranging the order of the second selector output, A second butterfly operation unit for performing a butterfly operation on the output of the second rearranger, a second delay unit for delaying the output of the second butterfly operation unit for a predetermined time, an output of the multiplier and an output of the adder A third selector for selecting one of the two,
A fourth selector for selecting one of two of the second delay unit output and the third selector output, a third rearranger for rearranging the order of the fourth selector output, A third butterfly operation unit that performs a butterfly operation on the output of the third rearranger, a third delay unit that delays the output of the third butterfly operation unit for a predetermined time, an output of the third delay unit, A fifth selector for selecting one out of two multiplier outputs, a fourth rearranger for rearranging the order of the fifth selector output and outputting as an orthogonal transform signal, and the first butterfly operation Selector for selecting one of three of an output of the second butterfly operation unit and an output of the third butterfly operation unit, and the multiplier for multiplying the output of the sixth selector. And the first butterfly operation unit output and the second butterfly operation unit. A seven-point selector for selecting one of two outputs of the fly operation unit, and an adder for adding the sixth selector output and the seventh selector output, and a two-point cosine transform And one-dimensional eight-point cosine transform, which is composed of a two-dimensional cosine transform and a four-point cosine transform, for each data of the input signal.

Further, the present invention provides a first rearranger for rearranging the order of the input signals with respect to an input signal composed of eight sets of digitized data, and a delay of an output of the first rearranger for a predetermined time. A first delay device for causing
A first selector for selecting one of two delay device outputs and a multiplier output, a second rearranger for rearranging the order of the first selector output, and the second rearranger A first butterfly operation unit for performing a butterfly operation consisting of addition and subtraction on an output, a second delay unit for delaying the output of the first butterfly operation unit for a predetermined time, and a multiplier output and a subtractor output. A second selector for selecting one;
A third selector output for selecting one out of two of the delay device output and the second delay device output; a third rearranger for rearranging the order of the third selector output; 3, a second butterfly operation unit that performs a butterfly operation on the output of the rearranger 3, a third delay unit that delays the output of the second butterfly operation unit for a predetermined time, and two of the output of the multiplier and the output of the subtractor. A fourth selector for selecting one of the first and second outputs from the third delayer output and the fourth selector output.
A fifth selector for selecting one, a fourth rearranger for rearranging the order of the fifth selector output, and a third butterfly operation unit for performing a butterfly operation on the output of the fourth rearranger. A fifth rearranger for rearranging the order of the output of the third butterfly operation unit and outputting the result as an orthogonal transformation signal; the output of the first rearranger, the output of the first butterfly operation unit, and the second butterfly; A sixth selector for selecting one of three arithmetic unit outputs, the multiplier for multiplying the sixth selector output, the first butterfly arithmetic unit output, and the second butterfly operation A seventh selector for selecting one out of two outputs of the multiplier, and a subtractor for subtracting the multiplier output from the seventh selector output, comprising a two-point inverse cosine transform and a four-point inverse cosine. 2D inverse cosine transformation Conversion, or is 1-dimensional 8-point inverse one of cosine transform those performed for each data of the input signal.

Further, the present invention provides a first rearranger for rearranging the order of the input signals with respect to an input signal consisting of eight sets of digitized data, and a delay of an output of the first rearranger for a predetermined time. A first delay device for causing
A first selector for selecting one out of two of the delay unit output and the multiplier output, a second rearranger for rearranging the output order of the first selector, and the second rearrangement Butterfly operation unit that performs a butterfly operation including addition and addition / subtraction on the output of a multiplier, a second delay unit that delays the output of the first butterfly operation unit for a predetermined time, and two output units of a multiplier output and an addition / subtraction unit A second selector for selecting one of the following, a third selector for selecting one of two of the second delay unit output and the second selector output, and the third selector A third rearranger for rearranging the output order, a second butterfly operation unit for performing a butterfly operation on the output of the third rearranger, and a third delay for delaying the output of the second butterfly operation unit for a predetermined time And one of the multiplier output and the adder / subtractor output. A fourth selector, a fifth selector for selecting one out of two of the third delay unit output and the fourth selector output, and an order of the fifth selector output. A fourth rearranger to be permuted, a third butterfly operation unit for performing a butterfly operation on the output of the fourth rearranger, a fourth delay unit for delaying the output of the third butterfly operation unit for a predetermined time, A sixth selector for selecting one of the fourth delay unit output and the multiplier output, and a fifth rearrangement for rearranging the order of the sixth selector output and outputting as an orthogonal transform signal And a seventh selector for selecting one of four of the first rearranger output, the first butterfly operation unit output, the second butterfly operation unit output, and the third butterfly operation unit The multiplier for multiplying the output of the seventh selector, An eighth selector for selecting one of two outputs from a first butterfly operation unit output and the second butterfly operation unit, and the adder / subtractor for performing addition / subtraction to the eighth selector output, Two-dimensional cosine transform consisting of two-point cosine transform and four-point cosine transform, or one-dimensional eight-point cosine transform, or two-dimensional cosine transform consisting of two-point inverse cosine transform and four-point inverse cosine transform, or one-dimensional eight-point inverse cosine Any one of conversion
And an orthogonal transformation device that performs one for each data of the input signal.

[0021]

[Function] 8-point cosine transform, 8-point inverse cosine transform,
For four kinds of orthogonal transforms, ie, two-dimensional cosine transform including two-point cosine transform and four-point cosine transform, two-dimensional inverse cosine transform including two-point inverse cosine transform and four-point inverse cosine transform, a specific high-speed operation algorithm is used. 8 when used
The number of actual multiplications required for the point calculation is eight or less. The operation algorithm is as described above, and the orthogonal transform apparatus is realized by one multiplier by using one multiplier capable of performing one multiplication in one sample processing time in a time division manner. be able to. Further, each orthogonal transform can be realized by one orthogonal transform device by utilizing the fact that the configuration methods of the orthogonal transform devices are similar.

[0022]

FIG. 1 is a block diagram of an orthogonal transform apparatus according to a first embodiment of the present invention. In the figure, 1 is a reordering device for reordering input signals, 2 is a butterfly operation device for performing butterfly operation on the output of the reordering device 1, 3 is a reordering device for reordering the output of the butterfly operation device 2, and 30 is a reordering device 3. 6 is a delay device for delaying the output of
A selector for selecting one of three outputs, an output of 0, an output of the multiplier 32, and an output of the adder 34, 7 is a butterfly operator for performing butterfly operation on an output of the selector 6, and 8 is an output of the butterfly operator 7 , 35 is a delay unit for delaying the output of the rearranger 8 for a predetermined time, and 11 is a multiplier 32
, An output of the adder 34, and an output of the delay unit 35, a selector 12 for performing a butterfly operation on the output of the selector 11, and a selector 36 for outputting the output of the butterfly operator 12. A delay unit that delays by a fixed time, 37 is a selector that selects one of two outputs of the delay unit 36 and the output of the multiplier 32, and 14 is a rearranger that rearranges the output of the multiplier 13 and outputs an orthogonal transform signal. , 31 are the sorters 3
, An output of the reordering unit 8 and one of the butterfly operation units 12.
1 is a multiplier for multiplying the output of 1;
Is a selector for selecting one set from two of the output of the reordering unit 8 and the output of the reordering unit 8, 34 is an adder that performs addition processing on one set of data that is the output of the selector 33, and 100 is a switch of the orthogonal transform method. This is a switching signal.

The operation of the orthogonal transform device of the present invention configured as described above will be described below. In FIG. 1, the same numbers are assigned to the components that operate in the same manner as the devices in FIG. 8 and FIG. 12.

First, in the orthogonal transform device of the present embodiment,
The case where the orthogonal transformation of the signal diagram shown in FIG. 7 is performed will be described. In FIG. 7, the number of actual multiplications is eight per one orthogonal transformation. In this embodiment, all the multiplication processes are performed in a time-division manner by using the multiplier 32 that can perform multiplication once per sample time. Also (FIG. 7)
In the above, the number of additions other than the butterfly operation is five, but in this embodiment, all the addition processing is performed in a time-division manner by using the adder 34 that can perform addition once in one sample time. Thus, the multiplier 4 (FIG. 8)
The multiplication is performed by a multiplier 32 in place of the components 9 and 13, and the addition is performed by an adder 34 instead of the adders 5 and 10 in FIG.
By selecting the data of the time division processing in 1, 33,
The same operation as that of FIG. 8 can be performed. Also,
In the orthogonal transform shown in FIG. 11, the number of actual multiplications is four, and the number of additions other than the butterfly operation is two. Further, when FIG. 12 is a block diagram of an orthogonal transform apparatus for realizing the orthogonal transform shown in FIG. 11 and FIG. 12 is compared with FIG. 8, FIG. 12 shows that the multiplier 4 and the adder 5 shown in FIG. Since the selector 6 is omitted, the orthogonal transformation of the signal diagram of FIG. 11 is performed similarly to the orthogonal transformation of the signal diagram of FIG. 7 as shown in FIG. It can be realized by a conversion device. Note that, in each device constituting (FIG. 7) and (FIG. 11), the calculation timing of the rearranger, the selector, the multiplier, and the adder is different. In response to the above, the operation timing of each device is switched by an external switching signal 100.

As described above, according to the present embodiment, 3
Transformation that performs orthogonal transform shown in the signal diagrams of FIGS. 7 and 11 by performing processing in a time-division manner using two butterfly operation units, one multiplier, one adder, and five selectors. The device can be realized.

FIG. 2 is a block diagram of an orthogonal transform apparatus according to a second embodiment of the present invention. In the figure, 1 is a reordering device for reordering input signals, 40 is a delay device for delaying the output of the reordering device 1 for a fixed time, 41 is one of two outputs of the output of the delay device 40 or the output of the multiplier 32. , A butterfly operator for performing butterfly operation on the output of the selector 41, a rearranger for rearranging the output of the butterfly operator 2, a delay unit for delaying the output of the rearranger 3 for a predetermined time, 6 is a selector for selecting one of three outputs of the output of the delay unit 30, the output of the multiplier 32 and the output of the subtractor 42, 7 is a butterfly operation unit for performing a butterfly operation on the output of the selector 6, and 8 is a butterfly operation A rearranger for rearranging the output of the multiplier 7, a delay unit 35 for delaying the output of the rearranger 8 for a predetermined time, 11 is one out of three outputs of the multiplier 32, the output of the subtractor 42, and the output of the delay unit 35. Select to select , 12 is a butterfly operation unit for performing butterfly operation on the output of the selector 11, 14 is a rearranger for rearranging the output of the butterfly operation unit 12 and outputting an orthogonal transform signal, 31 is an output of the rearranger 1 and an output of the rearranger 3 And rearranger 8
Is a selector for selecting one out of three outputs of the selector, 32 is a multiplier for multiplying the output of the selector 31, and 33 is one of two outputs of the output of the reorderer 3 and the output of the reorderer 8 Is a subtractor for subtracting the output of the multiplier 32 from the output of the selector 33, and 100 is a switching signal for switching the orthogonal transform method.

The operation of the orthogonal transform device of the present invention configured as described above will be described below. In FIG. 2, the same operations as those of the respective devices in FIG. 10 and FIG. 14 are denoted by the same reference numerals.

First, in the orthogonal transform device of the present embodiment,
The case where the orthogonal transformation of the signal diagram shown in FIG. 9 is performed will be described. In FIG. 9, the number of actual multiplications is eight per one orthogonal transformation. In this embodiment, all the multiplication processes are performed in a time-division manner by using the multiplier 32 that can perform multiplication once per sample time. Also (FIG. 7)
In the above, the number of subtractions other than the butterfly operation is 5, but in the present embodiment, all the subtraction processes are performed in a time-division manner by using the subtractor 42 that can perform addition once per sample time. In this manner, the multiplier 32 multiplies by the multiplier 32 instead of the multiplier 4, the multiplier 9 and the multiplier 13 in FIG. 8, and is subtracted by the subtractor 42 instead of the adder 5 and the adder 10 in FIG. 8. By selecting the data of the time division processing by the selector 31 and the selector 33, the same operation as that shown in FIG. 10 can be performed. In the orthogonal transformation shown in FIG. 13, the number of actual multiplications is four, and the number of additions other than the butterfly operation is two. Further, FIG. 13 is a block diagram of an orthogonal transformation device for realizing the orthogonal transformation shown in FIG.
4) is compared with FIG. 8 (FIG. 14), in which the multiplier 9, the subtractor 23 and the selector 11 in FIG. 10 are omitted. Therefore, the orthogonal transformation of the signal diagram of FIG. 13 is the same as the orthogonal transformation of the signal diagram of FIG.
Can be realized by the orthogonal transformation device shown in FIG. In addition,
Since the timings of calculation of the rearranger, the selector, the multiplier, and the adder are different between the devices constituting (FIG. 9) and (FIG. 13), the orthogonal transform device of this embodiment corresponds to the algorithm to be operated. Then, the operation timing of each device is switched by an external switching signal 100.

As described above, according to the present embodiment, 3
By using one butterfly operation unit, one multiplier, one subtractor, and five selectors and performing processing in a time-division manner, the orthogonal transformation for performing the orthogonal transformation shown in the signal diagrams of FIGS. 7 and 11 is performed. A conversion device can be realized. (FIG. 3) is a block diagram of an orthogonal transform apparatus according to a third embodiment of the present invention. In the figure, 1 is a reordering device for reordering input signals, 40 is a delay device for delaying the output of the reordering device 1 for a fixed time, 41 is one of two outputs of the output of the delay device 40 or the output of the multiplier 32. , A butterfly operator for performing butterfly operation on the output of the selector 41, a rearranger for rearranging the output of the butterfly operator 2, a delay unit for delaying the output of the rearranger 3 for a predetermined time, 6 is a selector for selecting one of three outputs, the output of the delay unit 30, the output of the multiplier 32, and the output of the adder / subtractor 50, 7 is a butterfly operation unit for performing butterfly operation on the output of the selector 6, and 8 is a butterfly operation A rearranger for rearranging the output of the multiplier 7, a delay unit 35 for delaying the output of the rearranger 8 for a predetermined time, 11 is one of three outputs of the multiplier 32, the output of the adder / subtractor 50, and the output of the delay unit 35. Select Selector, 12 is the butterfly operation device for butterfly operation the output of the selector 11, 36 is a delay circuit for a predetermined time delay the output of the butterfly operation device 12,
37 is a selector for selecting one of two outputs of the output of the delay unit 36 and the output of the multiplier 32; 14 is a rearranger for rearranging the output of the selector 37 to output an orthogonal transform signal; A selector for selecting one out of three of the output, the output of the reordering device 3 and the output of the reordering device 8, 32 is a multiplier for multiplying the output of the selector 31 and 33 is the output of the reordering device 3 A selector for selecting one device from three of the output of the rearranger 8 and the output of the multiplier 32 and outputting a set of data from the selected device. , 100 are switching signals for switching the orthogonal transform method.

The operation of the high-efficiency coding apparatus of the present invention configured as described above will be described below. (Fig. 3)
Is an orthogonal transformation device for realizing the four types of orthogonal transformation shown in (FIG. 7), (FIG. 9), (FIG. 11) and (FIG. 13).
This embodiment is different from the embodiment shown in FIG.
Is added and replaced by the adder / subtractor 50 in place of the adder 34, so that it is clear that the orthogonal transform of (FIG. 7) and (FIG. 11) can be processed from the previous embodiment. Further, in the present embodiment, a delay unit 36 and a selector 37 are added to the embodiment of FIG. 2 and replaced by an adder / subtractor 50 instead of the subtractor 42. ) And (FIG. 13) can be clearly processed.
Note that, in each device constituting (FIG. 7), (FIG. 9), (FIG. 11) and (FIG. 13), the calculation timings of the reordering unit, the selector, the multiplier, and the adder / subtractor are different. In the orthogonal transform device of the example, the operation timing of each device is switched by an external switching signal 100 in accordance with the algorithm to be operated.

As described above, according to the present embodiment, 3
Butterfly operation unit, one multiplier, one adder / subtracter, and 5
By using the selectors and processing in time division,
It is possible to realize an orthogonal transformation device that performs the orthogonal transformation shown in the signal diagrams of (FIG. 7), (FIG. 9), (FIG. 11), and (FIG. 13).

In this embodiment, (FIG. 7), (FIG. 9),
The four types of orthogonal transforms (FIG. 11) and (FIG. 13) have been described. In the case of the orthogonal transform in which the number of multiplications is 8 or less per transform, or the number of additions and subtractions other than butterfly operation is 8 or less per transform. In the case of orthogonal transform, the multiplier and the adder / subtracter can be shared as in the present embodiment, and the hardware scale can be reduced. Furthermore, hardware reduction by time division of a multiplier is possible other than 8-point orthogonal transformation.

FIG. 4 is a block diagram of an orthogonal transform apparatus according to a fourth embodiment of the present invention. In the figure, 1 is a reordering device for reordering input signals, 2 is a butterfly operation device for performing butterfly operation on the output of the reordering device 1, 30 is a delay device for delaying the output of the butterfly operation device 2 for a fixed time, and 17 is a delay device. A selector for selecting one of two outputs from the output of the selector 30 and the output of the selector 60 according to a selection signal, 8 is a rearranger for rearranging the output of the selector 17, and 7 is a butterfly operation on the output of the rearranger 8. A butterfly operation unit; 35, a delay unit for delaying the output of the butterfly operation unit 7 for a predetermined time; 18, a selector for selecting one of two outputs from the output of the selector 61 and the output of the delay unit 35 by a selection signal 100; Is the selector 1
A rearranger for rearranging the output of 8 and a rearranger 2 for 12
A butterfly operation unit for performing a butterfly operation on an output of 0, 36
Is a delay unit that delays the output of the butterfly operation unit 12 for a predetermined time, 19 is a selector that selects one of two outputs from the output of the delay unit 36 and the output of the multiplier 32 by the selection signal 100, 1
Reference numeral 4 denotes a rearranger for rearranging the output of the selector 19 to output an orthogonal transformation signal. Reference numeral 31 denotes one of three outputs, the output of the butterfly operation unit 2, the output of the butterfly operation unit 7, and the output of the butterfly operation unit 12, according to a selection signal. And 32 is a multiplier for multiplying the output of the selector 31;
33 is the output of the butterfly operation unit 2 and the butterfly operation unit 7
Is a selector for selecting one of two outputs from the output of the selector 33 in accordance with a selection signal. Reference numeral 34 denotes an adder for performing addition processing on a set of data output from the selector 33. Reference numeral 60 denotes an output of the adder 34. One of two outputs of the multiplier 32 is selected by a selection signal.
A selector 61 selects one of the outputs of the adder 34 and the output of the multiplier 32.

The operation of the orthogonal transform device of the present invention configured as described above will be described below. In FIG. 4, the same numbers are given to the devices that perform the same operations as the devices in FIG. 8 and FIG. 12. First, the case where the orthogonal transformation of the signal diagram shown in FIG. 7 is performed will be described. In FIG. 7, the number of actual multiplications is eight per one orthogonal transformation. In this embodiment, all the multiplication processes are performed in a time-division manner by using the multiplier 32 that can perform multiplication once per sample time. In FIG. 7, the number of additions other than the butterfly operation is five. However, in this embodiment, by using the adder 34 that can perform one addition per time of one sample,
All addition processing is performed in a time division manner. In this way, the multiplier 32 multiplies by the multiplier 32 instead of the multiplier 4, the multiplier 9 and the multiplier 13, and the addition is performed by the adder 34 instead of the adder 5 and the adder 10 (FIG. 8). Selector 31 and selector 3
By selecting the data of the time division processing in step 3, the same operation as in FIG. 8 can be performed. In addition, FIG.
In the orthogonal transformation shown in 1), the number of actual multiplications is four, and the number of additions other than the butterfly operation is two. Furthermore, (FIG. 1
FIG. 12 is a block diagram of an orthogonal transformation device for realizing the orthogonal transformation of (1) (FIG. 12). FIG. 12 shows a multiplier (4), an adder (5), and a selector (6) of FIG. Therefore, the orthogonal transform of the signal diagram of FIG. 11 can be realized by the orthogonal transform device of FIG. 4 similarly to the orthogonal transform of the signal diagram of FIG. .

As described above, according to this embodiment, 3
By using one butterfly operation unit, one multiplier, one adder and five selectors and performing processing in a time-division manner, the orthogonal transformation for performing the orthogonal transformation shown in the signal diagrams of FIGS. 7 and 11 is performed. A conversion device can be realized.

FIG. 5 is a block diagram of an orthogonal transform apparatus according to a fifth embodiment of the present invention. In the figure, 1 is a reordering device for reordering input signals, 40 is a delay device for delaying the output of the reordering device 1 for a predetermined time, and 45 is a selection signal from the output of the delay device 40 and the output of the multiplier 32. A selector for selecting one by 100, a rearranger for rearranging the output of the selector 45, a butterfly operation unit for performing a butterfly operation on an output of the rearranger 3, and a delay of an output of the rearranger 3 for a predetermined time. 17 is a selector for selecting one of two outputs from the output of the delay unit 30 and the output of the selector 60 according to the selection signal 100; 8 is a rearranger for rearranging the output of the selector 17; Butterfly operation unit for performing a butterfly operation on the output of the unit 8, and 35 is a butterfly operation unit
A delay unit 18 delays the output of the delay unit for a predetermined time.
A selector for selecting one of the selectors, 20 a rearranger for rearranging the output of the selector 18, 12 a butterfly operation unit for performing a butterfly operation on the output of the rearranger 20, 14 a rearrangement of the output of the butterfly operation unit 12 to perform an orthogonal transformation A rearranger for outputting a signal, 31 is a selector for selecting one of three outputs of the output of the rearranger 1, the output of the butterfly operation unit 2 and the output of the butterfly operation unit 7, and 32 is an output of the selector 31 Reference numeral 33 denotes a multiplier for selecting one of two outputs of the butterfly operation unit 2 and the output of the butterfly operation unit 7 by the selection signal 100. Reference numeral 42 denotes a selector 33.
And the output of the multiplier 32 are subtracted.
A selector 0 selects one of the two outputs of the output of the subtracter 42 and the output of the multiplier 32 by the selection signal 100.
Reference numeral 1 denotes a selector for selecting one of two outputs from the output of the subtracter 42 and the output of the multiplier 32 by a selection signal 100.

The operation of the orthogonal transform device of the present invention configured as described above will be described below. In FIG. 5, those units which perform the same operations as those shown in FIGS. 10 and 14 are given the same numbers. First, the case where the orthogonal transformation of the signal diagram shown in FIG. 9 is performed will be described. In FIG. 9, the number of actual multiplications is eight per one orthogonal transformation. In the present embodiment, all the multiplication processes are performed in a time-division manner by using the multiplier 32 that can perform multiplication once in one sample time. In FIG. 7, the number of subtractions other than the butterfly operation is five. However, in this embodiment, all the subtraction processes are performed in a time-division manner by using the subtractor 42 capable of performing one subtraction in one sample time. Perform In this way, instead of the multiplier 4, the multiplier 9 and the multiplier 13 (FIG. 8), the multiplication is performed by the multiplier 32, and the adder 5 and the adder 10 (FIG. 8).
Is subtracted by the subtractor 42 instead of and the data of the time division processing is selected by the selector 31 and the selector 33.
The same operation as (FIG. 10) can be performed. Also,
In the orthogonal transformation shown in FIG. 13, the number of actual multiplications is four, and the number of additions other than the butterfly operation is two. Furthermore, comparing FIG. 14 with FIG. 8 which is a block diagram of an orthogonal transformation device for realizing the orthogonal transformation of FIG.
(FIG. 14) omits the multiplier 9, subtractor 23 and selector 11 of (FIG. 10). Therefore, the signal of (FIG. 13) is similar to the orthogonal transformation of the signal diagram of (FIG. 9). The orthogonal transformation of the diagram can also be realized by the orthogonal transformation device shown in FIG.

As described above, according to the present embodiment, 3
By using one butterfly operation unit, one multiplier, one subtractor and five selectors, (FIG. 7) and (FIG. 1)
An orthogonal transformation device that performs the orthogonal transformation shown by the signal diagram 1) can be realized.

FIG. 6 is a block diagram of an orthogonal transform apparatus according to a sixth embodiment of the present invention. In the figure, 1 is a reordering device for reordering input signals, 40 is a delay device for delaying the output of the reordering device 1 for a predetermined time, and 45 is a selection signal from the output of the delay device 40 and the output of the multiplier 32. A selector for selecting one by 100, a rearranger for rearranging the output of the selector 45, a butterfly operator for performing butterfly operation on an output of the rearranger 3, and a reference numeral 30 for outputting the output of the butterfly operator 2 for a predetermined time. A delay device for delaying, 17 is a delay device 30
A selector for selecting one of two outputs from the output of the selector 60 and the output of the selector 60 by the selection signal 100, 8 is a rearranger for rearranging the output of the selector 17, and 7 is a butterfly for performing a butterfly operation on the output of the rearranger 8. An arithmetic unit, 35 is a delay unit for delaying the output of the butterfly arithmetic unit 7 for a predetermined time, and 18 is a selection signal 10 from two outputs of the delay unit 35 and the selector 61.
A selector that selects one by 0, 20 is a rearranger that rearranges the output of the selector 18, 12 is a butterfly operator that performs a butterfly operation on the output of the rearranger 20, 36 is a constant output of the butterfly operator 12 A time delay device,
19 is a selector for selecting one of two outputs from the output of the delay unit 36 and the output of the multiplier 32 by the selection signal 100, 14 is a rearranger for rearranging the output of the selector 19 and outputting an orthogonal transform signal, 31 is From the output of the rearranger 1, the output of the butterfly operation unit 2, the output of the butterfly operation unit 7, and the output of the butterfly operation unit 12,
A selector 32 for multiplying the output of the selector 31; and 33, one of the outputs of the butterfly operation unit 2 and the output of the butterfly operation unit 7 based on the selection signal 100.
A selector 62 for selecting one of the output of the selector 31 and an output of the multiplier 32 according to the selection signal 100; and 50 a selector for selecting the output of the selector 33 and the output of the selector 62. An adder / subtracter for performing addition / subtraction, 60 is a selector for selecting one of the output of the multiplier 32 and the output of the adder / subtractor 50 by the selection signal 100, and 61 is the output of the multiplier 32 and the output of the adder / subtractor 50. This is a selector for selecting one from the selection signals 100 according to the selection signal 100.

The operation of the high-efficiency coding apparatus of the present invention configured as described above will be described below. (FIG. 6)
Is an orthogonal transformation device for realizing the four types of orthogonal transformation shown in (FIG. 7), (FIG. 9), (FIG. 11) and (FIG. 13).
This embodiment is different from the embodiment shown in FIG.
And the selector 62 are added, and the adder / subtractor 50 is used instead of the adder 34. Therefore, it is clear that the orthogonal transform of (FIG. 7) and (FIG. 11) can be processed from the previous embodiment. . This embodiment is different from the embodiment shown in FIG.
6 and the selector 19 are added, and the adder / subtractor 50 is used instead of the subtractor 42. Therefore, it is clear that the orthogonal transformation of (FIG. 9) and (FIG. 13) can be processed from the previous embodiment. is there.

As described above, according to the present embodiment, 3
Butterfly operation unit, one multiplier, one adder / subtracter, and 5
(FIG. 7), (FIG. 9),
It is possible to realize an orthogonal transform device that performs the orthogonal transform shown by the signal diagrams in FIG. 11 and FIG.

This embodiment (FIG. 7), (FIG. 9),
The four types of orthogonal transforms (FIG. 11) and (FIG. 13) have been described. In the case of the orthogonal transform in which the number of multiplications is 8 or less per transform, or the number of additions and subtractions other than butterfly operation is 8 or less per transform. In the case of orthogonal transform, the multiplier and the adder / subtracter can be shared as in the present embodiment, and the hardware scale can be reduced. Furthermore, hardware reduction by time division of a multiplier is possible other than 8-point orthogonal transformation.

[0043]

As described above, according to the present invention, the hardware scale of the orthogonal transform apparatus can be greatly reduced by using the multiplier in a time division manner, and one orthogonal transform apparatus can be used. Can perform several kinds of orthogonal transformations, and its practical effect is great.

In the present invention, the data is rearranged at the input / output. However, the order of the input / output data may not be necessary depending on the specification application of the orthogonal transformation. In this case, the rearrangement of the corresponding input / output is performed. The vessel may be omitted.

[Brief description of the drawings]

FIG. 1 is a block diagram of an orthogonal transform apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of an orthogonal transform apparatus according to a second embodiment of the present invention.

FIG. 3 is a block diagram of an orthogonal transform apparatus according to a third embodiment of the present invention.

FIG. 4 is a block diagram of an orthogonal transform apparatus according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of an orthogonal transform apparatus according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram of an orthogonal transform apparatus according to a sixth embodiment of the present invention.

FIG. 7 is a signal diagram of orthogonal transform.

FIG. 8 is a block diagram of a conventional orthogonal transform device for realizing the orthogonal transform of FIG. 7;

FIG. 9 is a signal diagram of orthogonal transform.

FIG. 10 is a block diagram of a conventional orthogonal transform apparatus for realizing the orthogonal transform of FIG. 9;

FIG. 11 is a signal diagram of orthogonal transform.

FIG. 12 is a block diagram of a conventional orthogonal transform apparatus for realizing the orthogonal transform of FIG. 11;

FIG. 13 is a signal diagram of orthogonal transform.

FIG. 14 is a block diagram of a conventional orthogonal transform apparatus for realizing the orthogonal transform of FIG.

[Explanation of symbols]

1, 3, 8, 14, 15, 16, 20 Rearranger 2, 7, 12 Butterfly calculator 6, 11, 17, 18, 19, 31, 33, 37, 4,
5, 60, 61 Selector 32 Multiplier 34 Adder 42 Subtractor 50 Adder / Subtractor

────────────────────────────────────────────────── ─── Continuing on the front page (51) Int.Cl. ⁷ Identification symbol FI H04N 7/30 H04N 7/133 Z (72) Inventor Shoichi Nishino 1006 Ojidoma, Kazuma, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Japan Idaka Iwao 1006 Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-3-35353 (JP, A) US Patent 4831574 (US, A) Europe Patent Application Publication 366435 (EP, A2) Proceedings of the IEICE National Convention Vol. 1991, NO. Spring Pt7 Page. 7.41 1991 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/14 G06F 17/10 G06T 1/00 G06T 9/00 H04N 1/41 H04N 7/30 EPAT (QUESTEL) JICST file (JOIS) WPI (DIALOG)

Claims (13)

(57) [Claims] 1. An eight digitized data set.
For the input signal, three butterfly operation units and one power
Rearrange the order of the arithmetic value, the adder that performs addition and subtraction, and the operation value
And a selector for selecting one from a plurality of operation values.
Selector, and a delay unit for delaying the operation value for a predetermined time , wherein the outputs of at least two devices are selected by the selector, and
Input to the multiplier, and output the multiplier to at least two
Outputs to the selector and outputs a two-dimensional cosine transform consisting of two-point cosine transform and four-point cosine transform.
Sine transform, or one-dimensional 8-point cosine transform, or
Second order consisting of two-point inverse cosine transform and four-point inverse cosine transform
Original inverse cosine transform or one-dimensional 8-point inverse cosine transform
Performing at least two of the above for each data of the input signal
Conversion device. 2. A first method for rearranging the order of an input signal consisting of eight sets of digitized data.
A first reordering unit that performs a butterfly operation including addition and subtraction on the output of the first reordering unit, and a second reordering unit that rearranges the order of the output of the first butterfly operation unit. A first delay unit for delaying the output of the second reordering unit for a predetermined time, a first selector for selecting one of three outputs of the first delay unit output, a multiplier output, and an adder output; A second butterfly operation unit that performs a butterfly operation on the output of the first selector, a third rearranger that rearranges the order of the output of the second butterfly operation unit, and an output of the third rearranger for a predetermined time. A second delay unit that delays the output, a second selector that selects one of three outputs of the second delay unit output, the multiplier output, and the adder output, and a second selector output. The third butterfly performing a butterfly operation A computing unit, a third delay unit that delays the output of the third butterfly computing unit for a predetermined time, and a third unit that selects one of two outputs of the third delay unit output and the multiplier. A selector, a fourth rearranger for rearranging the order of the third selector output and outputting as an orthogonal transform signal, a second rearranger output, the third rearranger output, and the third butterfly. A fourth selector for selecting one of three arithmetic unit outputs, the multiplier for multiplying the fourth selector output, the second reorderer output and the third reorderer output A two-dimensional cosine transform comprising two-point cosine transform and four-point cosine transform, comprising a fifth selector for selecting a set of data from the two, and an adder for adding the output to the fifth selector. Either transformation or one-dimensional 8-point cosine transformation One of the orthogonal transform apparatus characterized by performing for each data of the input signal. 3. The orthogonal transform apparatus according to claim 1, wherein the delay unit and the selector are configured using a memory and a control mechanism of the memory. 4. A first method for rearranging the order of the input signals for an input signal composed of eight sets of digitized data.
, A first delay unit for delaying the output of the first rearranger for a fixed time, and a first selector for selecting one of two outputs of the first delay unit and the multiplier. A first butterfly operation unit for performing a butterfly operation consisting of addition and subtraction on the output of the first selector, a second rearranger for rearranging the order of the output of the first butterfly operation unit, and the second A second delay unit for delaying the output of the reordering unit for a predetermined time, a second selector for selecting one of three outputs of the second delay unit output, the multiplier output, and the subtractor output; A second butterfly operation unit that performs a butterfly operation on the selector output of the third, a third rearranger that rearranges the order of the output of the second butterfly operation unit,
A third delay unit that delays the output of the rearranger for a predetermined time, a third selector that selects one of three outputs of the third delay unit output, the multiplier output, and the subtractor output; A third butterfly operation unit that performs a butterfly operation on a third selector output, a fourth rearranger that rearranges the order of the third butterfly operation unit output, and outputs the result as an orthogonal transform signal, and the first rearrangement A fourth selector for selecting one of three of a filter output, the second rearranger output, and the third rearranger output; and the multiplier for multiplying the fourth selector output. A fifth selector for selecting one of the second rearranger output and the third rearranger output, and the subtractor for subtracting the multiplier output from the fifth selector output. Two-point inverse cosine transform and four-point inverse cosine Orthogonal transform apparatus characterized by performing two-dimensional inverse cosine transform consisting conversion, or 1-dimensional 8-point inverse one of cosine transform for each data of the input signal. 5. The orthogonal transform apparatus according to claim 3, wherein the delay unit and the selector are configured by using a memory and a control mechanism of the memory. 6. A first method for rearranging the order of an input signal composed of eight sets of digitized data.
, A first delay unit for delaying the output of the first rearranger for a fixed time, and a first selector for selecting one of two outputs of the first delay unit and the multiplier. A first butterfly operation unit for performing a butterfly operation including addition and addition / subtraction on the output of the first selector, a second rearranger for rearranging the order of the output of the first butterfly operation unit, and the second A second delay unit for delaying the output of the reordering unit for a fixed time, a second selector for selecting one of three outputs of the second delay unit output, the multiplier output, and the adder / subtractor output; A second butterfly operation unit for performing a butterfly operation on the selector output of the second, a third rearranger for rearranging the order of the output of the second butterfly operation unit, and a second rearranger for delaying the output of the third rearranger for a predetermined time. 3 delay units and the third delay unit A third selector for selecting one of three of the output of the multiplier, the output of the multiplier, and the output of the adder / subtractor; a third butterfly operation unit for performing a butterfly operation on the output of the third selector; A fourth delay unit for delaying the output of the butterfly operation unit No. 3 for a predetermined time; a fourth selector for selecting one of the fourth delay unit output and the multiplier output; and a fourth delay unit for selecting one of the fourth delay unit output and the multiplier output. A fourth rearranger for rearranging the order of the selector output and outputting the result as an orthogonal transform signal;
, The second rearranger output, the third rearranger output, and the third butterfly operation unit 4.
A fifth selector for selecting one of the outputs, the multiplier for multiplying the fifth selector output, the second reorderer output, the third reorderer output, and the multiplier output A fifth selector for selecting one of the three and selecting one set of data from the one output, and the adder / subtractor for performing addition / subtraction to the output of the fifth selector. Any of two-dimensional cosine transform consisting of transform and four-point cosine transform, or one-dimensional eight-point cosine transform, two-dimensional cosine transform consisting of two-point inverse cosine transform and four-point inverse cosine transform, or one-dimensional eight-point inverse cosine transform An orthogonal transform device for performing one of the above for each data of the input signal. 7. The orthogonal transform apparatus according to claim 5, wherein the delay unit and the selector are configured by using a memory and a control mechanism of the memory. 8. A first method for rearranging the order of the input signals for an input signal composed of eight sets of digitized data.
A first butterfly operation unit that performs a butterfly operation including addition and subtraction on the output of the first rearranger, and a first delay unit that delays the output of the first butterfly operation device for a predetermined time; Multiplier output and adder output 2
A first selector for selecting one of the two, a second selector for selecting one of two of the first delay unit output and the first selector output, and the second selection A second rearranger for rearranging the order of the device outputs, a second butterfly operation device for performing a butterfly operation on the output of the second rearranger,
A second delay unit for delaying the output of the second butterfly operation unit for a predetermined time, and two of the output of the multiplier and the output of the adder.
A third selector for selecting one of the outputs, a fourth selector for selecting one from two of the second delay unit output and the third selector output, and the fourth selection A third rearranger for rearranging the order of device outputs, a third butterfly operation unit for performing a butterfly operation on the third rearranger output,
A third delay unit for delaying the output of the third butterfly operation unit for a predetermined time, a fifth selector for selecting one of two of the third delay unit output and the multiplier output, 5
A fourth rearranger that rearranges the output order of the selectors and outputs as an orthogonal transform signal; and three of the first butterfly operation unit output, the second butterfly operation unit output, and the third butterfly operation unit output. A sixth selector for selecting one of the outputs, the multiplier for multiplying the output of the sixth selector, and an output of the first butterfly operation unit and an output of the second butterfly operation unit. And a adder for adding the sixth selector output and the seventh selector output, and comprises a two-point cosine transform and a four-point cosine transform. An orthogonal transformation device, wherein one of two-dimensional cosine transformation and one-dimensional eight-point cosine transformation is performed for each data of the input signal. 9. The orthogonal transform apparatus according to claim 7, wherein the delay unit and the rearranger are configured using a memory and a control mechanism of the memory. 10. A first rearranger for rearranging the order of said input signals with respect to an input signal comprising eight sets of digitized data, and a first rearranger for delaying an output of said first rearranger for a predetermined time. A delay unit, a first selector for selecting one of two of the first delay unit output and the multiplier output,
A second rearranger for rearranging the order of the first selector output, a first butterfly operation unit for performing a butterfly operation comprising addition and subtraction on the second rearranger output,
A second delay unit for delaying the output of the first butterfly operation unit for a predetermined time;
A second selector for selecting one, a third selector output for selecting one of the second delayer output and the second delayer output, and a third selector output. , A second butterfly operation unit that performs a butterfly operation on the output of the third rearranger, and a third operation unit that delays the output of the second butterfly operation unit for a predetermined time.
, A fourth selector for selecting one out of two of the multiplier output and the subtractor output, and two to one of the third delayer output and the fourth selector output. A fifth selector for selecting one, a fourth rearranger for rearranging the order of the fifth selector output, and a third butterfly operation unit for performing a butterfly operation on the output of the fourth rearranger. A fifth rearranger for rearranging the order of the output of the third butterfly operation unit and outputting the result as an orthogonal transformation signal; the output of the first rearranger, the output of the first butterfly operation unit, and the second butterfly; A sixth selector for selecting one of three arithmetic unit outputs, the multiplier for multiplying the sixth selector output, the first butterfly arithmetic unit output, and the second butterfly operation A seventh selector for selecting one out of two of the detector outputs; The subtractor subtracts the output of the multiplier from the output of the seventh selector. The subtractor performs two-dimensional inverse cosine transform including two-point inverse cosine transform and four-point inverse cosine transform, or one-dimensional eight-point inverse cosine transform. An orthogonal transformation device, wherein one of the operations is performed for each data of the input signal. 11. The orthogonal transform apparatus according to claim 9, wherein the delay unit and the rearranger are configured by using a memory and a control mechanism of the memory. 12. A first rearranger for rearranging the order of the input signals with respect to an input signal consisting of eight sets of digitized data, and a first rearranger for delaying an output of the first rearranger for a predetermined time. A delay unit, a first selector for selecting one of two of the first delay unit output and the multiplier output,
A second rearranger for rearranging the output order of the first selector, a first butterfly operation unit for performing a butterfly operation including addition and addition / subtraction on the output of the second rearranger, A second delay unit for delaying the output of the butterfly operation unit for a fixed time, a second selector for selecting one of two outputs of a multiplier output and an adder / subtractor output, the second delay unit output and the second output A third selector for selecting one out of two selector outputs, a third rearranger for rearranging the order of the third selector output, and a butterfly operation on the third rearranger output. A second butterfly operation unit for performing the operation, a third delay unit for delaying the output of the second butterfly operation unit for a predetermined time, and a fourth selector for selecting one of two outputs of a multiplier output and an adder / subtractor output And the third delay unit output and the fourth selector output A fifth selector for selecting one from two, a fourth rearranger for rearranging the order of the output of the fifth selector, and a third for performing a butterfly operation on the output of the fourth rearranger. A fourth arithmetic unit, a fourth delay unit for delaying the output of the third butterfly arithmetic unit by a predetermined time, and a sixth arithmetic unit for selecting one of the fourth delay unit output and the multiplier output. A selector, a fifth rearranger for rearranging the order of the sixth selector output and outputting as an orthogonal transform signal, the first rearranger output, the first butterfly operation unit output, and the second A seventh selector for selecting one of four of the butterfly operation unit output and the third butterfly operation unit, the multiplier for multiplying the output of the seventh selector, and the first butterfly operation Output of the second butterfly operation unit and the output of the second butterfly operation unit. The selecting an eighth selector for selecting one, the one by the seventh two to selection signal of the multiplier output and the selector output from 9
And a two-dimensional cosine transform comprising two-point cosine transform and four-point cosine transform, or a one-dimensional cosine transform, comprising an adder / subtracter for performing addition and subtraction of the eighth selector output and the ninth selector output. Either one of eight-point cosine transform, two-dimensional cosine transform including two-point inverse cosine transform and four-point inverse cosine transform, or one-dimensional eight-point inverse cosine transform
Orthogonal transform for each data of the input signal. 13. The orthogonal transform apparatus according to claim 11, wherein the delay unit and the rearranger are configured using a memory and a control mechanism of the memory.