JP3013521B2 - Solid color imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a charge coupled device (CCD).
The present invention relates to a solid-state imaging device using a solid-state image sensor such as a CCD image sensor formed by a Charge Coupled Device) as an imaging unit, and in particular, digitizes an imaging signal obtained by the solid-state image sensor and converts image data of a plurality of types of clock rates. The present invention relates to a solid-state imaging device for forming and outputting.

[0002]

2. Description of the Related Art Generally, in a solid-state imaging device using a solid-state image sensor having a discrete picture element structure, such as a CCD image sensor, for an image pickup section, the solid-state image sensor itself is a sampling system, so It is known that an aliasing component from the spatial sampling frequency f _CCD is mixed into an image signal by the sensor. Conventionally,
By providing a birefringent optical low-pass filter in the imaging optical system and suppressing the high-band component of the baseband component of the imaging signal, the Nyquist condition of the sampling system using the solid-state image sensor is satisfied, Of the baseband component is prevented from being generated.

[0003] In a color television camera device for picking up a color image, a three-primary-color image is picked up by a solid-state image sensor for picking up a green image and a solid-state image sensor provided with a color coding filter for red and blue picture elements. Multi-plate solid-state imaging devices, such as a two-plate solid-state imaging device and a three-plate solid-state imaging device that captures three primary color images with individual solid-state image sensors, have been put into practical use.

Further, as a technique for improving the resolution in the multi-plate type solid-state image pickup device, a solid-state image sensor for picking up a green image is used for a red image pick-up only by a half of a spatial sampling period of a picture element. A so-called space picture element shifting method in which a solid-state image sensor for picking up a blue image is staggered is known. By adopting the spatial picture element shifting method, a high resolution exceeding the limit of the number of pixels of the solid-state image sensor can be realized in the analog output multi-plate solid-state imaging device.

Also, D-1 and D-2 standards have been standardized as standards for professional digital video tape recorders used in broadcasting stations and the like, and digital video related equipment conforming to these standards has been standardized. Digital interfaces are also needed for color television camera devices.

Here, in the D-1 standard which is a standard of 4: 2: 2 digital component video signal, the sampling frequency is set to the horizontal frequency f in the NTSC system.
_{13.5M which} is 858 times _{H (NTSC)} and 864 times the horizontal frequency f _{H (PAL)} in the PAL system.
Hz, and can be locked at an integral multiple of the horizontal frequency in either method. Further, in the D-2 standard is a standard for digital composite video signal, the sampling frequency is four times the 4F _SC subcarrier being adapted to minimize beat interference between the subcarrier and sampling clocks, NTSC scheme Has a sampling frequency f _{S (NTSC)} of 14.3 MHz and a sampling frequency f _{S (PAL)} of the PAL system of 17.734 MHz.

[0007]

When a color television camera device for directly outputting a digital image signal conforming to the D-1 standard or the D-2 standard as described above is to be realized, the resolution is increased. In order to directly output a high-quality digital image signal with a low aliasing distortion and a good image quality, the sampling rate (the number of pixels) of the solid-state image sensor used in the image pickup unit must be an optical low-pass which is a pre-filter for the solid-state image sensor. Considering the imperfectness of the filter, that is, only a gentle roll-off characteristic can be obtained with an optical low-pass filter, and it is difficult to achieve both good MTF characteristics and reduced aliasing components. , D-1
It is necessary to make the sampling rate higher than the standard or the sampling rate in the D-2 standard. Further, in consideration of digital processing such as defect correction processing for each pixel of the solid-state image sensor, and prevention of occurrence of beat disturbance, the sampling rate of the solid-state image sensor is considered. And the sampling rate of the analog-to-digital converter for digitizing the image output signal of the solid-state image sensor.

In view of the above circumstances, the present invention provides a color television camera apparatus which directly outputs a digital image signal conforming to the D-1 standard or the D-2 standard as described above. The purpose of the present invention is to obtain a digital image signal having a high resolution and a high-resolution analog image signal.
The imaging output signal read from the solid-state image sensor at a sampling rate higher than the sampling rate in the D-2 standard is digitized, and the digital imaging output signal is clocked at twice the sampling rate in the D-1 or D-2 standard. After image processing with,
While outputting the digital image signal converted to the sampling rate in the D-1 standard or the D-2 standard,
An object of the present invention is to provide a solid-state color image pickup device which outputs an analog image signal obtained by converting a digital image pickup output signal obtained by performing image processing at a clock rate twice as high as the sampling rate in the standard or the D-2 standard into an analog signal.

[0009]

According to the present invention, there is provided a solid-state color image pickup apparatus for picking up a green image which is spatially shifted by a half of a pixel repetition pitch in order to achieve the above object. A solid-state image sensor, a solid-state image sensor for imaging a red image and a solid-state image sensor for imaging a blue image, and a digital image signal for each color read from the solid-state image sensor at a read clock rate of a first frequency f _{CCD at} the read clock rate. _FSTD = f _CCD · n / m for the analog-to-digital conversion means to be converted, and for each color image data of the read clock rate digitized by the analog-to-digital conversion means.
(Where m and n are positive integers satisfying m> n), and rate conversion means for forming each color image data at the sending clock rate of the second frequency f _STD , Data processing means for performing image processing at the sending clock rate on each color imaging data of the sending clock rate obtained by the means,
A solid-state color image pickup device for outputting color image data of the sending clock rate of the second frequency f _STD from the data processing means, wherein the n is an odd number, the green image data and the red With respect to the imaging data and the blue imaging data, the passbands of 0 to f _STD / 2 have substantially the same characteristics, and an up-conversion interpolation filter having different characteristics in which the carrier phases of the nf _CCDs are mutually inverted is provided. It is characterized by the following.

Further, in order to achieve the above object, the solid-state color image pickup device according to the present invention comprises a solid-state image sensor for picking up a green image, which is spatially displaced by a half of a pixel repetition pitch. A solid-state image sensor for capturing a red image and a blue image; and an analog-to-digital converter for digitizing, at the read clock rate, each color image signal read from the solid-state image sensor at a first frequency f _CCD read clock rate. And 2f _STD = f _CCD · n / m (where m,
n is a positive integer satisfying m> n), a first rate conversion means for forming each color imaging data of a processing clock rate of a second frequency 2f _STD , and the first rate conversion means A data processing unit for performing image processing at the processing clock rate on each of the imaging data at the processing clock rate obtained by the conversion unit, and a color image data at the processing clock rate obtained by the data processing unit at a third frequency f _STD A second rate conversion means for converting color image data of the processing clock rate obtained by the data processing means into analog image data, and a second analog conversion means for converting the color image data of the processing clock rate obtained by the data processing means into analog data. outputting color image data delivery clock rate of the frequency f _STD from said second rate converting means Rutotomoni, the analog color image signals into analog color image data of the second frequency 2f _STD processing clock rate a solid-state color imaging apparatus which outputs from the digital-to-analog conversion means, said rate converting means, the n is an odd number,
For the green imaging data, the red imaging data, and the blue imaging data, the pass bands of 0 to f _STD / 2 have substantially the same characteristics, and n
An up-conversion interpolation filter having different characteristics in which the carrier phases of the f _CCD are inverted with each other is provided.

[0011]

In the solid-state color image pickup device according to the present invention, a solid-state image sensor for picking up a green image and a solid-state image sensor for picking up a red image and a blue image, which are spatially shifted by １ ／ of the pixel repetition pitch. First from solid image sensor
The frequency f of each color image signal read at the _CCD read clock rate is digitized by the analog-to-digital conversion means at the read clock rate, and the color image data of the read clock rate digitized by the analog-to-digital conversion means is green-imaged. The passband of 0 to f _STD / 2 has substantially the same characteristics for the data, red imaging data and blue imaging data, and nf
F _STD = f _CCD by the rate conversion means provided with an up-conversion interpolation filter having different characteristics in which the carrier phases in the _CCD (n is an odd number) are inverted with each other.
A second frequency f _STD by performing a rate conversion process of n / m (where m and n are positive integers satisfying m> n)
Is formed for each color at the output clock rate. Then, the image processing is performed by the data processing means at the sending clock rate on each color imaging data of the sending clock rate obtained by the rate converting means, and the second frequency f is output from the data processing means.
Outputs color image data at the sending clock rate of _STD .

Further, in the solid-state color image pickup device according to the present invention, a solid-state image sensor for picking up a green image and a solid-state image sensor for picking up a red image and a blue image, which are spatially shifted by の of the pixel repetition pitch. each solid from the image sensor of the first frequency f _CCD respective color image pickup signals read at a clock rate digitized by the delivery clock rate by the analog-digital converter, the digitized said feeding clock rate by the analog-digital conversion means For each color image data,
For the green imaging data, the red imaging data, and the blue imaging data, the pass bands of 0 to f _STD / 2 have substantially the same characteristics, and n
f _CCD 2f (n is an odd number) by the first rate conversion means comprising an interpolation filter for up conversion having different characteristics the carrier phase at are mutually inverted _STD
= F _CCD · n / m (where m and n are positive integers satisfying m> n) to form each color imaging data at the processing clock rate of the second frequency 2f _STD , Data processing means performs image processing at the processing clock rate on each color image data of the processing clock rate obtained by the first rate conversion means. Then, the color image data at the processing clock rate obtained by the data processing means is converted by the second rate conversion means into color image data at the sending clock rate of the third f _STD and output. Also, the color image data at the processing clock rate of the second frequency 2f _STD obtained by the data processing means is converted into an analog signal by a digital-to-analog conversion means and output.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a solid-state color imaging device according to the present invention will be described below in detail with reference to the drawings. A solid-state color imaging device according to the present invention is configured, for example, as shown in FIG.

The solid-state image pickup device of the first embodiment shown in FIG. 1 separates image pickup light incident from an image pickup lens via an optical low-pass filter into three primary color light components by a color separation prism, thereby forming a subject image. The present invention is applied to an NTSC color television camera device that captures three primary color images with three CCD image sensors 1R, 2G, and 1B,
Image data conforming to the D1 standard and image data conforming to the D2 standard can be selectively output.

In the first embodiment, the three C images constituting the image pickup section of the color television camera device are used.
CD image sensor 1R, 1G, 1B may employ the spatial pixel shifting method, as shown in FIG. 2, with respect to the CCD image sensor 1G for green imaging, picture elements of the spatial sampling period tau _s 1 The CCD image sensors 1R and 1B for red image pickup and blue image pickup are shifted from each other by / 2. The three CCD image sensors 1R, 1G, and 1B are connected to the system controller 1
The first read clock pulse CK _CCD1 from the first read clock generator 14 or the second read clock pulse CK _CCD2 from the second read clock generator 15 via the clock changeover switch 13 that is controlled by the switch ₂ Is supplied and driven by the first or second read clock pulse CK _CCD1 or CK _CCD2 to read out the imaging charge of each picture element.

The first read clock generator 14
Is, D1 standard sampling frequency f _STD1 (858f _H
= 13.5MHz m ₁ / n ₁ times the) (where, m _1, n
₁ is an integer satisfying m ₁ > n ₁ ), for example, m ₁ = 4, n ₁ = 3
As A first read clock pulse CK _CCD1 having a sampling frequency f _CCD1 (18.00 MHz) is output. Further, the second reading clock generator 15, D2 standard of the sampling frequency f _STD2 (4f _sc = 14.3MH
z) m ₂ / n ₂ times (where m ₂ and n ₂ are m ₂ ≧ n ₂₎
Integers), for example, assuming that m ₂ = 5 and n ₂ = 4, Sampling frequency f _CCD2 (17.898 MHz)
The second read clock pulse CK _CCD2 is output.
The system controller 12 selects the first read clock pulse CK _CCD1 in the D1 standard imaging operation mode (hereinafter, referred to as D1 mode),
D2 standard imaging operation mode (hereinafter referred to as D2 mode)
At this time, switching control of the clock switch 13 is performed so that the second read clock pulse CK _CCD2 is selected.

Here, 18.00M in the D1 mode.
Hz sampling frequency f a first read clock pulse CK _{CCD 1} by the effective number of pixels of the CCD image sensor capturing charges of the picture elements are read out of the _{CCD 1} (the number of pixels in the final system blanking the Index) N ₁ (N ^H × N ^V )
Since f _CCD1 = 1144f _H , one horizontal operation period is set to 63.556 sec, and a blanking period is set to 10.
Assuming 9 μsec, N ^H = 1144 × (63.556-10.9) /63.556=947.8 per line, and the number of effective pixels V ₁ in the vertical direction is 485, and N ₁ = 947 a .8 ^H × 485 ^V. In the D2 mode, 17.898 MHz
Sampling frequency f a second reading clock pulse CK _{CCD 2} by effective number of pixels of the CCD image sensor capturing charges of the picture elements are read out of the _{CCD 1} (the number of pixels in the final system blanking the Index) N ₂ (N ^H × N ^V )
Since f _CCD2 = 1137.5f _H , one horizontal operation period is set to 63.556 sec, and the blanking period is set to 10.35 fH.
Assuming 9 μsec, N ^H = 1137.5 × (63.556-10.9) /63.556=942.4 and N ₂ = 942.4 ^H × 485 ^V per line.

A 2/3 "optical system (8.8 ^H × 6.
6 ^V = 11.0 ^D ), the ideal unit cell size is 9.29 μm ^H × 13.61 in the D1 mode.
μm ^V , and 9.34 μm ^H × 1 in D2 mode.
It becomes 3.61 μm ^V. Therefore, in this embodiment, the unit cell size of each of the CCD image sensors 1R, 1G, 1B is set to 9.3 μm ^H × 13.6 μm ^V.
The error of the diagonal and the aspect ratio of the image output by the CCD image sensor having the unit cell size of 9.3 μm ^H × 13.6 μm ^{V is} as follows: the diagonal error in the D1 mode is + 0.08%, and the aspect ratio error is −
0.23%, the diagonal error in the D2 mode is -0.3%, and the aspect ratio error is +0.35.
% And can be ignored.

The CCD image sensors 1R, 1R,
1G, 1B unit cell size is 9.25 μm ^H × 1
Assuming that 3.5 μm ^V , the diagonal and aspect ratio errors are -0.5% in the D1 mode, -0.4% in the aspect ratio, and D2 in the D1 mode.
The error of the diagonal in the mode is -0.9% and the error of the aspect ratio is + 0.15%. In addition, each of the above CCDs
Assuming that the unit cell size of the image sensors 1R, 1G, and 1B is 9.2 μm ^H × 13.5 μm ^V , the error of the diagonal and the aspect ratio is -0.7% in the D1 mode and the error of the aspect ratio is Error is + 0.1%
And the diagonal error in the D2 mode is -1.
At 3%, the aspect ratio error is + 0.7%.

Three C's using the above spatial picture element shifting method
For the three primary color images of the subject image, the CD image sensors 1R, 1G, and 1B are configured such that the CCD image sensor 1G for capturing the green image and the CCD image sensors 1R and 1B for capturing the red image and the blue image capture τ _s. The position shifted by / 2 is spatially sampled. Accordingly, the three primary color imaging signals S _{R *} , S _{G *} , S _{B *} by the respective CCD image sensors 1R, 1G, 1B are signal spectra in the D1 mode in which reading is performed by the first read clock pulse CK _CCD1 . D2 for performing reading by the second read clock pulse CK _CCD2 shown in FIG.
The signal spectrum in the mode is shown in FIG.
The green image signal S _{G *} by the CCD image sensor 1G
Of the sampling frequency f _{CCD 1,} f _{CCD 2} components and the respective CCD image sensors 1R, 1B by the red image signal S _{R *} and the blue image signal S _{B *} of the sampling frequency f _{CCD 1,} f _{CCD 2} ingredients are opposite phases It has become.

The respective color image pickup signals S _{R *} , S _{G *} , S _{B *} read from the CCD image sensors 1 R, 1 G, 1 B by the first or second read clock pulses CK _CCD1 , CK _{CCD 2} are respectively Analog processing circuits 2R, 2 for performing correlated double sampling processing, level control, etc.
The signals are supplied to analog / digital (A / D) converters 3R, 3G, 3B via G, 2B.

Each of these A / D converters 3R, 3G, 3B
Is the respective color image pickup signals _{S R *, S G *,} S B * clock rate or equal to the sampling rate of the read clock pulse CK _{CCD 1,} CK _{CCD 2} of the same sampling frequency f _{CCD 1,} the f _{CCD 2} clock pulse CK _AD1 CK
_AD2 is selectively supplied via the clock changeover switch 13. Then, the A / D converter 3R,
3G, 3B, said respective color image pickup signals _{S R *, S G *,} S B * a and directly digitized by reading clock rate of the sampling frequency f _{CCD 1,} f _{CCD 2} by the clock pulse CK _AD1 CK _AD2, each color imaging Signals S _{R *} , S
_{G *,} the digital color signals of the same signal spectrum as the spectrum of _{S B * D R *, D} R *, to form a D B _*.

Each of the digital color signals D _R , D _G , and D _B obtained by the A / D converters 3R, 3G, 3B is a first
Is supplied to the digital process processing circuit 4.

The first digital process processing circuit 4
The clock pulses CK _DP1 and CK _{DP2 of the} same sampling frequencies f _CCD1 and f _{CCD2 as those} of the read clock pulses CK _CCD1 and CK _CCD2 are supplied via the clock switch 13. Then, the first digital processing circuit 4, the sampling frequency f _{CCD 1,} the digital color signals of the read clock rate of _{f CCD2 D R *, D R} *, with respect to D B _*, the clock pulse CK _DP1 , CK _DP2 performs image processing for each picture element such as defect correction at the above read clock rate without causing beat interference. The first digital processing circuit 4 each digital color signal subjected to the image processing for each pixel by _{D R *, D R *,} D B * , respectively rate converter 5
The signal is supplied to the second digital process processing circuit 6 via R, 5G and 5B.

Each of the above rate converters 5R, 5G, 5B
The clock pulses CK _DP1 and CK _{DP2 of the} same sampling frequency f _CCD1 and f _{CCD2 as those} of the read clock pulses CK _CCD1 and CK _CCD2 are supplied via the clock changeover switch 13 and the first sending clock generator. first feeding clock pulses CK _STD1 or the second feeding clock pulses CK _STD2 from the second feeding clock generator 17 is supplied via the clock selector switch 18 from 16.

Here, the first sending clock generator 16 outputs a sampling frequency f _STD1 (85
8f _H = 13.5 MHz) and outputs a first sending clock pulse CK _STD1 . The second sending clock generator 17 has a sampling frequency f of the D2 standard.
_A second sending clock pulse CK _STD2 of _STD2 (4f _sc = 14.3 MHz) is output. Then, the changeover switch 18 selects the first sending clock pulses CK _STD1 the D1 mode, also, to select the second feed clock pulse CK _STD2 when called D2 mode, by the system controller 12 Switching is controlled.

Each of the above rate converters 5R, 5G, 5B
As shown in FIG. 5, for example, a six-stage shift register 21 to which input data _xn of a read clock rate of the sampling frequencies f _CCD1 and f _CCD2 is supplied,
A multiplier 23 for multiplying the output of each stage of the shift register 21 by a coefficient a _P given by the coefficient register 22;
Adder 24 for adding the multiplied output by multiplier 23
And the sum output y _m ′ of the reading clock rates of the sampling frequencies f _CCD1 and f _CCD2 obtained by the adder 24 is converted to the sampling frequency f of the D1 and D2 standard.
_It comprises a latch circuit 25 for taking out at the sending clock rate of _{STD1 and fSTD2} .

The rate converter 5G has a D
In the one mode, the coefficient a _{P of the} impulse response as shown in FIG. 6 is given to the multiplier 23 by the coefficient register 22 according to the processing sequence shown in Table 1, so that the sampling frequency f _CCD1 (18.00 M
Hz) readout clock rate of the digital color signal D
_{G * is changed} to the sampling frequency f _STD1 (13.5M
Hz) of the digital color signal D at the sending clock rate of
Performs rate conversion processing to convert to _G.

[0029]

[Table 1]

Each of the rate converters 5 for performing a rate conversion process on the digital color signals DR _* and DB _* .
In R and 5B, the coefficient a _{P of the} impulse response as shown in FIG. 7 is given to the multiplier 23 by the coefficient register 22 according to the processing sequence shown in Table 2, so that the digital color signal D _{R at the} read clock rate is obtained. _* performs rate conversion processing to convert the D B _* D1 digital chrominance signal D _R standards delivery clock rate, the D _B.

[0031]

[Table 2]

That is, each of the above rate converters 5R,
5G and 5B are signals of the sampling frequency f _CCD1 (18.00 MHz) supplied from the first digital process processing circuit 4 by the interpolation processing and the downsampling processing as shown in FIGS. 3 and 8 in the D1 mode. Each digital color signal D _{R *} , D _{G *} ,
A rate conversion process is performed on DB _* such that m ₁ = 4, n ₁ = 3 and f _STD1 = f _CCD1 / n ₁ / m ₁ = 18.00 / 3/4 MHz = 13.5 MHz. The digital color signals D _R , D _G , and D _B at the sending clock rate of the standard sampling frequency f _STD1 (13.5 MHz) are formed.

Here, in the solid-state color imaging device of the first embodiment, since the spatial picture element shifting method is employed as described above, the actual sample of the green imaging signal _{SG *} by the CCD image sensor 1G is used. Π between ● and the actual sample ▲ of the red imaging signal SR _* by the CCD image sensor 1R.
In the case where n is an odd number (n = 3), the up-converted sequence is set, for example, to a phase that matches the actual sample of green imaging data. If they are not treated to give a phase difference of π, the two will not be in phase. D1
In both the standard and the D2 standard, since R, B, and G have the same phase, it is necessary to insert a π phase shifter.

This is nf _CCD (= 4) in the frequency domain.
f _STD1 ), the carrier at the sampling frequency f _CCD1 is 0 to f _STD / 2 with respect to the green imaging data, red imaging data, and blue imaging data whose carriers are inverted with respect to each other. The passband has almost the same characteristics, and nf
_The above nf _CCD (= 4f _STD1 ) is obtained by using an up-conversion interpolation filter having the characteristics shown in FIG. 3 in which the carrier phases of _CCD1 (= 4f _STD1 ) are inverted.
4f by inverting the carrier phase at _STD1), the output shown in Figure 3 having uniform phase at the nf _CCD (= 4f _STD1) can be obtained from the interpolation filter.

[0035] Then, a the n is an odd number, with respect to a green imaging data and red imaging data and the blue imaging data, the pass band of 0 to F _STD / 2 is substantially the same characteristics, nf _CCD
The different characteristics that the carrier phases at
6 and 7 described above in terms of an impulse response.
become that way.

Each of the rate converters 5R, 5R
G and 5B are supplied from the first digital process processing circuit 4 by the coefficient register 22 providing the multiplier 23 with the coefficient a _{P of the} impulse response in the D2 mode in accordance with a predetermined processing sequence. Sampling frequency f _CCD2 (17.898M
Hz) for each of the digital color signals _{DR *} , _{DR *} , and _{DB * at} the read clock rate, assuming that n ₂ = 4 and m ₂ = 5, f _STD2 = f _CCD · n ₂ / m ₂ = 17 .898 / 4/5 MHz = 14.3 MHz, a rate conversion process as shown in FIG. 9 is performed, and each digital color signal D _R , at the sending clock rate of the sampling frequency f _STD2 (14.3 MHz) of the D2 standard is used.
D _G, forms a D _B.

Each of the above rate converters 5R, 5G, 5B
Said the resulting sampling frequency f _STD1, f _STD2
Digital color signals D _R , D _G , D
_B is serially output via a parallel-serial conversion circuit 9RGB. Further, each of the above rate converters 5R,
The sampling frequency f obtained by 5G and 5B
_The digital color signals D _R , D _G , and D _{B at} the sending clock rates of _{STD 1} and f _STD2 are converted by the second digital process circuit 6 into the sampling frequencies f _STD1 ,
After being subjected to process processing such as gamma correction at a clock rate of f _STD2 , it is supplied to a third digital process processing circuit 7 and is converted into an analog signal by digital / analog (D / A) converters 10R, 10G, and 10B, respectively. Then, they are output as analog color signals R, G, and B via post filters 11R, 11G, and 11B, respectively.

The third digital process processing circuit 7
In each digital chrominance signals of delivery clock rate of the sampling frequency f _STD1, f _STD2 supplied from the second digital processing circuit 6 D _R, D _G,
By matrix calculation processing for D _B, the feeding of the clock rate digital luminance signal D _Y, the digital color difference signal D _U, D _V, composite video signal D
Forming the video signal D _VF for _CS and viewfinder.

The third digital process processing circuit 7
The digital luminance signal D _Y , the digital color difference signals D _U , _DV and the composite video signal D _{CS at the} sending clock rate obtained by the above are serially output via the parallel-serial conversion circuit 9. In the D1 mode, the digital luminance signal D _Y and the digital color difference signals D _U and D _{V at} the sending clock rate of the sampling frequency f _STD1 obtained by the third digital process processing circuit 7 are respectively processed by the D1 processing circuit 8. digital color difference signal D _U, the D _V downsampling process is performed on the clock rate of 6.75 MHz, also, the digital luminance signal D _Y is decorated with delay compensation processing and output in parallel. Further, the digital luminance signal D _Y , the digital color difference signals D _U and D _V , the composite video signal D _CS and the view finder video signal D _VF obtained by the third digital process processing circuit 7 are digital analog ( D / A) converter 10Y, 1
0U, 10V, 10CS, and 10VF, which are converted into analog signals, the analog luminance signal Y, the analog color difference signals U,
V, an analog composite video signal CS, and a video signal VF for a viewfinder are output via post filters 11Y, 11U, 11V, 11CS, and 11VF, respectively.

In the above embodiment, the present invention is applied to the NTS.
When applied to a C-type color television camera device, D1
Although it is possible to selectively output image data conforming to the standard and image data conforming to the D2 standard, the present invention
Not intended monkey limited only to the embodiments described above, as _{m 1 = 8, n 1 =} 5 in D1 _{mode, f CCD1 = f STD1 · m} 1 / n 1 = 858f H · 8/5 = 13.5 · 8 A sampling frequency f _CCD1 of / 5 MHz = 21.6 MHz is adopted, and in the D2 mode, m ₂ = 3 and n ₂ = 2, and f _CCD2 = f _STD2 · m ₂ / n ₂ = 4f _sc · 3/2 = A sampling frequency f _CCD2 of 6f _sc = 21.48 MHz may be employed. Also,
In the above embodiment, image data conforming to the D1 standard and D
Although image data conforming to the two standards is selectively output, a solid-state imaging device dedicated to D1 mode or D2 mode may be used. In this case, a common solid-state image sensor may be used. it can.

Further, for example, the present invention can be applied to a color television camera device of the PAL system, and selectively output image data conforming to the D1 standard and image data conforming to the D2 standard. When the present invention is applied to a color television camera device of the PAL system, the first reading clock generator 14, m ₁ / n of the D1 standard sampling frequency f _STD1 (858f _H = 13.5MHz)
₁ time (where m ₁ and n ₁ are integers satisfying m ₁ > n ₁ ), for example, assuming that m ₁ = 4 and n ₁ = 3, A first read clock pulse CK _CCD1 having a sampling frequency f _CCD1 (18.00 MHz) is output. Further, the second read clock generator 15 outputs m ₂ =
as n _2, Sampling frequency f _CCD2 (17.734 MHz)
The second read clock pulse CK _CCD2 is output.

Further, the first sending clock generator 16 outputs a sampling frequency f _STD1 (85
8f _H = 13.5 MHz) and outputs a first sending clock pulse CK _STD1 . The second sending clock generator 17 has a sampling frequency f of the D2 standard.
_A second sending clock pulse CK _STD2 of _STD2 (4f _sc = 17.734 MHz) is output.

The rate converters 5R, 5R
G, 5B is the D1 mode, the digital color signals of the read clock rate of the sampling frequency f _CCD1 (18.00MHz) supplied from the first digital processing circuit _{4 D R *, D G *} , D _{For B *} , m
_{Assuming that 1} = 4 and n ₁ = 3, a rate conversion process of f _STD1 = f _CCD1 / n ₁ / m ₁ = 18.00 / 3/4 MHz = 13.5 MHz is performed, and the sampling frequency f _STD1 (13 The digital color signals D _R , D _G , and D _B at the output clock rate of (.5 MHz) are output. Further, when the D2 mode, the first digital processing read clock rate each digital color signal D of the sampling frequency f _{CCD 2} is supplied from the circuit _{4 (17.734MHz) R *, D} G *, the D _{B *} for,
Each of the digital color signals D _R , D _G , and D _{B at} the sending clock rate of the sampling frequency f _STD2 (17.734 MHz) of the D2 standard is subjected to the rate conversion processing of m ₂ = n _2.
Is output.

Here, a 、 ２ ″ optical system (8.8 ^H × 6.
6 ^V = 11.0 ^D ), the ideal unit cell size is 9.402 μm ^H × 11.478 μm in the D1 mode.
^V , 9.542 μm ^H × 11.47 in D2 mode
Since it is 8 μm ^V , for example, the unit cell size of each of the CCD image sensors 1R, 1G, 1B is 9.4 μm.
By setting m ^H × 11.4 μm ^V , the error of the diagonal and the aspect ratio is -0.26% in the D1 mode and -0.66 in the aspect ratio.
%, And the diagonal error in the D2 mode is-
At 1.2%, the aspect ratio error is + 0.8%. The unit cell size is 9.5 μm ^H × 11.
Assuming 4 μm ^V , the diagonal and aspect ratio errors are as follows: the diagonal error in the D1 mode is + 0.4%, the aspect ratio error is −1.7%, and the diagonal error in the D2 mode is −1.7%. At 0.5%, the error of the aspect ratio becomes -0.24%. In addition, if the error of the aspect ratio is 2% or less, it can sufficiently withstand practical use.

Next, a solid-state color image pickup device according to a second embodiment, whose configuration is shown in the block diagram of FIG. 10, will be described.

In the second embodiment, the three C images constituting the image pickup section of the color television camera device are used.
Similarly to the first embodiment, the CD image sensors 31R, 31G, and 1B are different from the CCD image sensor 31G for picking up a green image by the spatial sampling period τ of the picture element.
Only half of the _s, CCD image sensors 31R for red imaging and blue imaging, are arranged staggered 31B. The three CCD image sensors 31R and 31B are connected to the first read clock pulse CK _CCD1 or the second read clock pulse CK _CCD1 from the first read clock generator 44 via the clock switch 43 controlled by the system controller 42. Read clock pulse CK from the read clock generator 45 of FIG.
_CCD2 is supplied and driven by the first or second read clock pulse CK _CCD1 , CK _CCD2 to read out the imaging charge of each picture element.

The first read clock generator 44
Is, D1 standard sampling frequency f _STD1 (858f _H
= 13.5MHz m ₁ / n ₁ times the) (where, m _1, n
₁ is an integer satisfying m ₁ > n ₁ ), for example, m ₁ = 4, n ₁ = 3
As A first read clock pulse CK _CCD1 having a sampling frequency f _CCD1 (18.00 MHz) is output. Further, the second reading clock generator 45, D2 standard of the sampling frequency f _STD2 (4f _sc = 14.3MH
z) m ₂ / n ₂ times (where m ₂ and n ₂ are m ₂ ≧ n ₂₎
Integers), for example, assuming that m ₂ = 5 and n ₂ = 4, A second read clock pulse CK _CCD2 having a clock frequency f _CCD2 (17.898 MHz) is output. Then, the system controller 42 selects the first read clock pulse CK _CCD1 in the imaging operation mode of the D1 standard (hereinafter referred to as D1 mode), and
The switching control of the clock switch 43 is performed so that the second read clock pulse CK _CCD2 is selected in the standard imaging operation mode (hereinafter, referred to as D2 mode).

Three C's using the spatial picture element shifting method
The CD image sensors 31R, 31G, and 31B are provided with a CCD for capturing the green image for the three primary color images of the subject image.
Spatial sampling is performed at a position where the image sensor 31G and the CCD image sensors 31R and 31B for capturing the red image and the blue image are shifted by τ _s / 2. Therefore, each of the CCD image sensors 31R, 31G, 3
FIG. 11 shows a signal spectrum of the _three primary color imaging signals S _{R *} , S _{G *} , and S _{B *} in the D1 mode in which reading is performed by the first read clock pulse CK _CCD1 .
Further, as shown in FIG. 12, the signal spectrum in the D2 mode in which reading is performed by the second read clock pulse CK _CCD2 is shown in FIG.
The sampling frequency f of the green image signal S _{G *} by _G
CCD1 and f _CCD2 components and each of the above CCD image sensors 31
The components of the sampling frequencies f _CCD1 and f _CCD2 of the red imaging signal S _{R *} and the blue imaging signal S _{B *} by R and 31B have phases opposite to each other.

The first or second read clock pulses CK _CCD1 and CK _CCD2 read out the color image signals S _{R *} , S _{G *} and S _{B *} read from the CCD image sensors 31R, 31G and 31B, respectively. Analog processing circuit 3 that performs correlated double sampling processing and level control
Analog digital (A) via 2R, 32G, 32B
/ D) are supplied to the converters 33R, 33G, 33B.

Each of these A / D converters 33R, 33G, 3
3B, the above respective color image pickup signals _{S R *, S G *,} S B * equal clock rate or the read sampling rate clock pulses CK _{CCD 1,} CK _{CCD 2} and the same sampling frequency f _{CCD 1,} f _{CCD 2} of the clock pulse CK _AD1 CK
_AD2 is selectively supplied via the clock changeover switch 43. Then, the A / D converter 33
R, 33G, and 33B represent the respective color image pickup signals S _{R *} , S _{G *} ,
_{SB *} is digitized as it is at the sampling frequency f _CCD1 , f _CCD2 read clock rate by the clock pulse CK _AD1 CK _AD2 , and the same signal as the spectrum of each color imaging signal S _{R *} , _{SG *} , SB _* each digital color signal D _{R *} spectrum, D R _*, to form a D B _*.

The A / D converters 33R, 33G, 33B
Digital color signals D _R , D _G , D
_B is supplied to the first digital process processing circuit 34.

The first digital process processing circuit 3
4 is the read clock pulse CK _CCD1 , CK _CCD2
Clock pulses CK _DP1 and CK _{DP2 of the} same sampling frequencies f _CCD1 and f _CCD2 are supplied via the clock switch 43. Then, the first digital processing circuit 34, the sampling frequency f _{CCD 1,} the digital color signals of the read clock rate of _{f CCD2 D R *, D R} *, with respect to D B _*, the clock pulse CK _DP1 , CK _DP2 performs image processing for each picture element such as defect correction at the above read clock rate without causing beat interference. The digital color signals D _{R *} , D _{R *} , and D _{B *} subjected to image processing for each picture element by the first digital process processing circuit 34 are passed through the rate converters 35 _R , 35 G, 35 B, respectively. Is supplied to the digital process processing circuit 36 of FIG.

Each of the above rate converters 35R, 35G,
35B is the read clock pulse CK _CCD1 , CK
Clock pulse CK _DP11, CK _DP12 of the same sampling frequency f _{CCD 1,} f _{CCD 2} together with is supplied via the clock changeover switch 43 and the _{CCD 2,} the first processing clock pulses CK from the first process clock generator 46 The second from the _DP21 or the second processing clock generator 47
The processing clock pulse CK _DP22 is supplied via the clock changeover switch 48.

Here, the first processing clock generator 4
6, D1 standard sampling frequency f _STD1 (858f
_H = 13.5 MHz) twice the sampling frequency 2f
_STD1 (27 MHz) first processing clock pulse CK
Outputs _DP21 . Further, the second processing clock generator 47 _outputs the sampling frequency f _STD2 (4f _sc
= 14.3 MHz) twice the sampling frequency 2f
Second processing clock pulse C of _STD2 (28.6 MHz)
_Outputs K _DP22 . The changeover switch 48
Is the first processing clock pulse CK in the D1 mode.
Select _DP21, also to select the second process clock pulse CK _{DP 22} to D2 mode, the switching control by the system controller 42.

The above rate converters 35R, 35G,
35B has the same configuration as that of each of the rate converters 5R, 5G, and 5B in the first embodiment described above. In the D1 mode, the rate converter 35G outputs the sampling frequency f _CCD1 (18.00M
Hz) readout clock rate of the digital color signal D
The _{G *} perform rate conversion processing for converting the digital color signal D _{G **} twice the processing clock rate of the sampling frequency 2f _STD1 (27 MHz) of the sampling frequency f _STD1 of D1 standard. In addition, each of the rate converters 35R, 35R
5B is the D1 mode, the read clock rate of the digital chrominance signals D _{R *,} D B _* the D1 2 times the sampling frequency 2f standard sampling frequency f _STD1
A rate conversion process for converting digital color signals D _{R **} and D _{B **} at a processing clock rate of _STD1 (27 MHz) is performed.

That is, each of the rate converters 35
R, 35G and 35B perform the sampling frequency f _CCD1 (18.00) supplied from the first digital process processing circuit 34 by the interpolation processing and the downsampling processing as shown in FIGS. 11 and 13 in the D1 mode.
Each digital color signal of the read clock rate MHz) D _R *, as D _G *, with respect to _{D B *, m 1 = 4} , n 1 = 3, _Is performed, and a sampling frequency 2f _STD1 (2
7 MHz) of processing the digital chrominance signals D _{R **} clock rate, D _{G **,} to form a D _{B **.}

Each of the rate converters 35R, 35R
5G, 35B is the D2 mode, the digital color signals of the read clock rate of the sampling frequency f _CCD2 (17.898MHz) supplied from the first digital processing circuit _{34 D R *, D R *} , D _{For B *} , n ₂ = 4 and m ₂ = 5, 12 and FIG. 14, and each digital color signal D _{R ** at} a processing clock rate of a sampling frequency 2f _STD2 (28.6 MHz) which is twice the sampling frequency f _STD2 of the D2 standard. , D _{G **} , D
Form _{B **} .

Each of the above rate converters 35R, 35G,
The sampling frequency 2 obtained by 35B
f _STD1, 2f _STD2 process clock rate each digital color signals D _{R **} in, D _{G **,} D _{B **} is being Dan down sampled to 1/2 of the clock rate by Dan down sampling circuit 38RGB, the D1 standard sampling frequency f _STD1 or D2 standard of the sampling frequency f _STD2
Digital clock signals D _R ,
Parallel-serial conversion circuit 39RGB as D _G and D _B
Is output serially. Furthermore, each rate converter 35R, 35G, each digital color signals D _R processing clock rate of the sampling frequency 2f _STD1, 2f _STD2 obtained by 35B, D _G, D _B, in the second digital processing circuit 36 After being subjected to process processing such as gamma correction at the above processing clock rate, it is supplied to a third digital process processing circuit 37 and is converted into an analog signal by digital / analog (D / A) converters 40R, 40G and 40B, respectively. hand,
Output as analog color signals R, G, B via post filters 41R, 41G, 41B, respectively.

The third digital process processing circuit 3
7, the digital luminance signal D _{R **} , D _{G **} , and D _{B **} supplied from the second digital process processing circuit 36 at the processing clock rate are subjected to matrix operation processing to obtain a digital luminance signal D _{R. Y **} , each digital color difference signal D _{U **} , D _{V **} , composite video signal D
_{A CS **} and a video signal _{DVF **} for a viewfinder are formed.

The third digital process processing circuit 3
7, the digital luminance signal D _{Y ** at the} above processing clock rate, and the digital color difference signals D _{U **} and D _{V **}
And composite video signal D _{CS **} is being Dan down sampled to 1/2 of the clock rate by Dan down sampling circuit 38, the feed clock rate of the sampling frequency f _STD2 of the D1 standard sampling frequency f _STD1 or D2 standard Each digital color signal D _R , D
_G, is serially output through a parallel-serial conversion circuit 39 together with the parallel output as D _B.

The digital luminance signal D _{Y **} , digital color difference signals D _{U **} , D _{V **} , composite video signal D _{CS **} and view finder signal obtained by the third digital process circuit 37 are also provided. Video signal D
_{VF **} is converted into an analog signal by digital-to-analog (D / A) converters 40Y, 40U, 40V, 40CS, and 40VF, respectively, and the analog luminance signal Y, the analog color difference signals U and V, the analog composite video signal CS, and the view As the video signal VF for the finder, post filters 41Y, 41U, 41V, 41CS, 4
Output via 1VF.

[0062]

According to the solid-state color imaging device of the present invention,
Each color image pickup signal read out from each solid-state image sensor at the first frequency f _CCD readout clock rate is digitized by the analog-to-digital conversion means at the above-mentioned readout clock rate. For the imaging data, f _STD =
f _CCD · n / m (where m and n are positive integers satisfying m> n) and perform a second frequency f
Form imaging data at the sending clock rate of _STD ,
The image data at the sending clock rate obtained by the rate conversion means is subjected to image processing at the sending clock rate by the data processing means, and the image data at the sending clock rate at the second frequency f _STD is subjected to the data processing. Output from the imaging means, the image signal read from the solid-state image sensor having a higher sampling rate (the number of pixels) than the sampling rate in the D-1 standard or the D-2 standard is converted into the D-1 standard or the D-2 standard.
It is possible to form and output image data of the sampling rate in the standard. Since the sampling rate of the imaging signal read from the solid-state image sensor is higher than the sampling rate in the D-1 standard or the D-2 standard, the influence of imperfections of the optical low-pass filter, which is a pre-filter, on the solid-state image sensor is reduced. By avoiding this, it is possible to directly output a digital image signal having high resolution and good image quality with little aliasing distortion. Furthermore, since the sampling rate of the solid-state image sensor and the sampling rate of the analog-to-digital conversion means for digitizing the image signal by the solid-state image sensor match, it is possible to prevent occurrence of beat disturbance, It is possible to perform digital processing such as defect correction processing for each pixel of the solid-state image sensor.

Therefore, according to the present invention, the D-1 standard and the D
In a color television camera device that directly outputs a digital image signal that conforms to the -2 standard, a digital color image signal with less aliasing and good image quality can be obtained.

In the solid-state color image pickup device according to the present invention, an image signal read from each solid-state image sensor at the read clock rate of the first frequency f _CCD is digitized by the analog-to-digital conversion means at the read clock rate. The image data at the above read clock rate digitized by the analog-to-digital conversion means is converted into two-
A rate conversion process is performed so that f _STD = f _CCD · n / m (where m and n are positive integers satisfying m> n) to form imaging data at a processing clock rate of the second frequency 2f _STD. Subjecting image data at the processing clock rate obtained by the first rate conversion means to image processing at the processing clock rate by data processing means;
The image data of the processing clock rate obtained by the data processing means is converted into image data of the sending clock rate of the third frequency f _STD by the second rate conversion means and is output. It is possible to form and output color image data of the above-mentioned D-1 standard or D-2 standard from each image pickup signal read from each solid-state image sensor having a higher sampling rate than the two standard sampling rates. In addition, since the sampling rate of the imaging signal read from the solid-state image sensor is higher than the sampling rate in the D-1 standard or the D-2 standard, the imperfectness of an optical low-pass filter that is a pre-filter for the solid-state image sensor is caused. By avoiding the influence, it is possible to obtain a digital color image signal with high resolution and good image quality with little aliasing distortion. Further, since the sampling rate of the solid-state image sensor and the sampling rate of the analog-to-digital converter for digitizing the image signal read from the solid-state image sensor are identical, it is possible to prevent occurrence of beat disturbance, It is possible to perform a defect correction process for each pixel of the solid-state image sensor by digital processing.

Further, since the image data at the processing clock rate obtained by the data processing means is converted into an analog signal by the digital-to-analog converting means and output, a high-resolution analog color image signal can be output. Moreover, in the present invention, n is an odd number, and the pass band of 0 to f _STD / 2 has substantially the same characteristic for green imaging data, red imaging data and blue imaging data, and nf
By performing rate conversion processing using an up-conversion interpolation filter that has different characteristics in which the carrier phase in the _CCD is inverted, the solid-state color imaging device that adopts the spatial pixel shift method has the same phase of green imaging data. And red imaging data and blue imaging data.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a solid-state color imaging device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing an arrangement state of each CCD image sensor in the solid-state color imaging device of the first embodiment.

FIG. 3 shows D1 of the solid-state color imaging device according to the first embodiment.
FIG. 4 is a diagram illustrating a signal spectrum used for describing an imaging operation in a mode.

FIG. 4 shows D2 of the solid-state color imaging device of the first embodiment.
FIG. 4 is a diagram illustrating a signal spectrum used for describing an imaging operation in a mode.

FIG. 5 is a block diagram illustrating a configuration of a rate converter in the solid-state color imaging device according to the first embodiment.

FIG. 6 is a diagram showing an impulse response in an imaging operation in a D1 mode of the interpolation filter of the rate converter.

FIG. 7 is a diagram showing an impulse response in a D2 mode imaging operation of the interpolation filter of the rate converter.

FIG. 8 shows D1 of the solid-state color imaging device of the first embodiment.
FIG. 5 is a diagram provided for describing an operation of the rate converter in an imaging operation in a mode.

FIG. 9 shows D2 of the solid-state color imaging device of the first embodiment.
FIG. 5 is a diagram provided for describing an operation of the rate converter in an imaging operation in a mode.

FIG. 10 is a block diagram illustrating a configuration of a solid-state color imaging device according to a second embodiment of the present invention.

FIG. 11 shows a solid-state color imaging device according to the second embodiment.
FIG. 4 is a diagram illustrating a signal spectrum used for describing an imaging operation in one mode.

FIG. 12 shows D of the solid-state color imaging device of the second embodiment.
FIG. 3 is a diagram illustrating a signal spectrum used for describing an imaging operation in two modes.

FIG. 13 illustrates a solid-state color imaging device according to the second embodiment.
FIG. 7 is a diagram provided for describing an operation of a rate converter in an imaging operation in one mode.

FIG. 14 illustrates a solid-state color imaging device according to the second embodiment.
FIG. 7 is a diagram provided for describing an operation of a rate converter in an imaging operation in two modes.

[Explanation of symbols]

1R-1B, 31R-31B ... CCD image sensor 3R-3B, 33R-33B ... A / D converter 4, 34 ... 1 digital process processing circuit 5R to 5B, 35R to 35B ... rate converter 6, 36 ... second digital process processing circuit 7, 37 ... ··· Third digital process processing circuit 8, 9 RGB, 38, 39 RGB ··· Parallel / serial conversion circuit 10R to 10VF, 40R to 40VF ··· D / A converter 12, 42 · ······ System controller 13, 18, 43, 48 ································································································· Generator 16,1 .............. feed clock generator 46 and 47 .............. processing clock generator

Claims (2)

(57) [Claims] 1. A solid-state image sensor for capturing a green image, a solid-state image sensor for capturing a red image, and a solid-state image sensor for capturing a blue image, which are spatially shifted by １ ／ of a pixel repetition pitch. The first frequency f from the image sensor
Analog-to-digital conversion means for digitizing each color image signal read at the read clock rate of the _CCD at the above read clock rate; and f _STD = f for each color image data at the above read clock rate digitized by the analog to digital conversion means. _CCD n / m (where m and n are m>
n is a positive integer).
Rate conversion means for forming each color imaging data of the sending clock rate of the second frequency f _STD , and data processing means for performing image processing on each color imaging data of the sending clock rate obtained by the rate converting means at the sending clock rate A solid-state color imaging device for outputting color image data at the sending clock rate of the second frequency f _STD from the data processing means, wherein the n is an odd number, The passband of 0 to f _STD / 2 has substantially the same characteristics for the imaging data, the red imaging data and the blue imaging data, and the nf _CCD
A solid-state color imaging device comprising an up-conversion interpolation filter having different characteristics in which the carrier phases are inverted from each other. 2. A solid-state image sensor for capturing a green image, a solid-state image sensor for capturing a red image, and a solid-state image sensor for capturing a blue image, which are spatially shifted by １ ／ of a pixel repetition pitch. Analog-to-digital conversion means for digitizing each color image signal read from the image sensor at a first frequency f _CCD read clock rate at the read clock rate; and each color at the read clock rate digitized by the analog-digital conversion means. Regarding imaging data, 2f _STD = f _CCD · n / m (where m and n are m
> N is a positive integer) and a first rate conversion means for forming each color imaging data of the processing clock rate of the second frequency 2f _STD , and a first rate conversion means A data processing means for performing image processing on the obtained imaging data at the processing clock rate at the processing clock rate; and a sending clock of the third frequency f _{STD which} outputs the color image data at the processing clock rate obtained by the data processing means. includes a second rate converting means for converting the color image data rate, and a digital-to-analog converting means for analog the color image data of the processing clock rate obtained by the data processing means, the third frequency f _STD Output from the second rate conversion means. A solid-state color image pickup device for outputting, from the digital-to-analog conversion means, an analog color image signal obtained by converting color image data having a processing clock rate of the second frequency 2f _STD into analog, the rate conversion means comprising: Is an odd number, and the pass band of 0 to f _STD / 2 has substantially the same characteristics with respect to the green imaging data, the red imaging data and the blue imaging data, and the nf _CCD
A solid-state color imaging device comprising an up-conversion interpolation filter having different characteristics in which the carrier phases are inverted from each other.