JP3013100B2 - Method for manufacturing dielectric tunnel structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Dielectric tunnel structure in which a dielectric barrier layer is interposed between a first region having conductivity and a second region having a high dielectric and semiconductor band structure The object of the present invention is to provide a method of manufacturing a dielectric barrier structure in which characteristics are not degraded even when a pinhole occurs in a dielectric barrier layer, and a first region having conductivity, a high dielectric constant, A method of manufacturing a dielectric tunnel structure in which a dielectric barrier layer is interposed between a second region having a semiconductor band structure and a second region having a high dielectric constant and a semiconductor band structure. Depositing a dielectric barrier layer on the entire surface of the dielectric barrier layer to reduce the dielectric constant of the surface of the second region exposed at the bottom surface through a pinhole in the dielectric barrier layer. Exposing it to an aqueous acid solution, Depositing a first region having conductivity on the dielectric barrier layer.

[Industrial applications]

The present invention relates to a method for manufacturing a dielectric tunnel structure in which a dielectric barrier layer is interposed between a first region having conductivity and a second region having a high dielectric constant and a semiconductor band structure.

In recent years, a superconducting diode using a laminated structure of a conductive region made of a superconductor, a dielectric barrier layer, and a region (semiconductor region) having a high dielectric constant and a semiconductor band structure,
A dielectric tunnel structure device such as a superconducting base transistor has been proposed.

FIGS. 5A and 5B are explanatory views of a superconducting diode using a dielectric tunnel structure.

In this figure, 21 is a first conductive region made of a superconductor, 22 is a first dielectric barrier layer, 23 is a region having a high dielectric constant and a semiconductor-like band structure (semiconductor region), and 24 is a second region.
The dielectric barrier layer 25 is a second conductive region.

This superconducting diode has a first conductive region 21 made of a superconductor, a first dielectric barrier layer 22, a high dielectric constant, as shown in the schematic configuration diagram of FIG. It is composed of a laminate of a region (semiconductor region) 23 having a semiconductor band structure, a second dielectric barrier layer 24, and a second conductive region 25.

Then, as an example of a material constituting the diode, the first conductive region 21 is Nb, the first dielectric barrier layer
22 and the second dielectric barrier layer 24 are made of Si, and the semiconductor region 23 is made of Nb-doped SrTiO ₃ .

FIG. 5 (b) shows the band structure of the superconducting diode.

As shown in this figure, when a voltage is applied between the first conductive region 21 and the second conductive region 25 at both ends of the above-described superconducting diode, the potential of the dielectric layer with respect to electrons decreases. The band structure is bent in such a way that the first dielectric barrier layer 22 and the second dielectric barrier layer, each of which has a significantly lower dielectric constant than the semiconductor region 23,
Occurs in 24.

Since the first dielectric barrier layer 22 and the second dielectric barrier layer 24 are formed so narrow that carriers pass by a tunnel phenomenon, the semiconductor region 23 is viewed from the first conductive region 21. The effective barrier height is the first conductive region
It would be given by the energy difference between the conduction band of the Fermi level E _F and the semiconductor region 23 of the 21.

Since this effective barrier height can be reduced to about the ionization energy of the donor in the semiconductor region 23, 1 meV
The following values can be obtained:

When the first conductive region 21 in the superconducting state is irradiated with an electromagnetic wave having an energy exceeding twice the energy gap Δ of the superconductor, superconducting electrons (Cooper pairs) in the superconductor are emitted. Since the carrier is split by absorbing the energy of the electromagnetic wave to become a carrier, it is possible to configure an electromagnetic wave detecting device having minute energy.

In addition, when the above-described dielectric tunnel structure is applied to the base region of a transistor, a barrier layer as low as several meV can be obtained, and a signal can be minutely switched.
Since a superconducting base transistor with extremely low power consumption is formed, a high-density high-performance computer can be formed by this.

[Conventional technology]

The dielectric tunnel structure used for the superconducting diode or the like basically includes a region having a high dielectric and a semiconductor band structure (semiconductor region), a dielectric barrier layer,
It is composed of a conductive region.

The dielectric constant of this semiconductor region has a value, for example, 1000 times or more higher than that of the dielectric barrier layer.

When the dielectric constant of the semiconductor region is increased as described above, the following two phenomena occur.

First phenomenon A large band bending occurs in the dielectric barrier, and the band bending generated in the depletion layer on the surface of the semiconductor region becomes very small.

For this reason, this value is about 1 eV in a normal semiconductor, but is about several meV in this case.

Second phenomenon When a voltage is applied to this dielectric tunnel structure, the voltage applied to each dielectric layer is divided by the inverse ratio of the capacitance per unit area of each layer. Joins the barrier layer.

By these two phenomena, a superconducting diode or a superconducting base transistor operating at a low voltage of about several mV can be obtained.

Conventionally, this dielectric tunnel structure has a thickness of several tens of millimeters on a semiconductor region having a high dielectric constant and a semiconducting band structure.
The dielectric barrier layer 27 is deposited by sputtering or the like, and a dielectric region is deposited thereon.

[Problems to be solved by the invention]

However, since the dielectric barrier layer is as thin as several tens of degrees, it is difficult to avoid generation of pinholes.

Then, when a pinhole occurs, the conductive region reaches the semiconductor region having a high dielectric constant through the pinhole, and the voltage applied to the dielectric barrier layer itself decreases, thereby enabling the dielectric tunnel structure to operate at a low voltage. Further, the above two phenomena are inhibited.

Therefore, in the dielectric tunnel structure manufactured by the conventional manufacturing method, there is a problem that the characteristics are not as expected and deteriorate.

An object of the present invention is to provide a method of manufacturing a dielectric tunnel structure in which characteristics are not deteriorated even when a pinhole is generated in a dielectric barrier layer.

[Means for solving the problem]

In a method of manufacturing a dielectric tunnel structure according to the present invention, a dielectric barrier layer is provided between a first region having conductivity and a second region having a high dielectric constant and a semiconductor band structure. A method of manufacturing an interposed dielectric tunnel structure, comprising: depositing a dielectric barrier layer over a second region having a high dielectric constant and a semiconducting band structure; Exposing the entire dielectric barrier layer to an aqueous acid solution to reduce the dielectric constant of the surface of the second region exposed on the bottom surface through the pinhole; Depositing a first region having conductivity.

[Action]

6 (a) to 6 (c) are diagrams illustrating the principle of the manufacturing method of the present invention.

In this figure, 26 is a region having a high dielectric constant and a semiconductor band structure (semiconductor region), 27 is a dielectric barrier layer, 28 is a pinhole, 29 is a low dielectric constant region, and 30 is a conductive region.

First Step (See FIG. 6A) A dielectric barrier layer 27 is deposited on a region (semiconductor region) 26 having a high dielectric constant and a semiconducting band structure.

In this case, the thickness of the deposited layer is extremely small, several tens
It is difficult to avoid pinholes 28 in the deposited layer.

Second Step (See FIG. 6B) A low dielectric constant region 29 is formed on the surface of the semiconductor region 26 through the pinhole 28 by performing the processing described in the embodiment.

Third step (see FIG. 6 (c)) A conductive region 30 is deposited thereon.

The characteristics of the dielectric tunnel structure manufactured by the conventional manufacturing method and the manufacturing method of the present invention will be described.

 First, a case where the pinhole 28 does not occur will be considered.

In this case, the dielectric constant of the dielectric barrier layer is ε ₃ , its thickness is d ₃ , the dielectric constant of the surface of the semiconductor region is ε ₂ , and the thickness of the depletion layer is
Let d be ₂ .

When a voltage V is applied to this structure, the voltage applied to each dielectric layer becomes the capacitance ε ₃ / d ₃ , ε ₂ /
Since the voltage is divided by the inverse ratio of d _2, the voltage applied to the dielectric barrier layer is given by ((1+ (d ₃ ε ₂ ) / (d ₂ ε ₃ )) ⁻¹ V.

However, the situation changes when a pinhole 28 is formed in the dielectric barrier layer and the conductive region 30 reaches and contacts the surface of the semiconductor region 26.

Now, assuming that the area of the pinhole is S, since the conductive region is in contact with the region having a high dielectric constant, the capacitance of the pinhole is S ·
ε ₂ / d ₂ .

However, since ε ₂ is very large (about 1000 times) as compared with ε ₃ , this capacitance value is not negligible compared to the capacitance A · ε ₃ / d ₃ of the entire dielectric barrier layer having the area A. Become.

Therefore, the apparent capacitance of the dielectric barrier layer increases, and the voltage applied to the dielectric barrier layer, which is determined by the inverse ratio of the dielectric constant of each layer, decreases.

Contrary to this, according to the manufacturing method of the present invention, after depositing the barrier layer on the semiconductor region, a process for reducing the dielectric constant of the surface of the semiconductor region exposed on the bottom surface of the pinhole may be performed. Dielectric constant ε _x much smaller than ε _{2 with}
Has the thickness thereof to form a low dielectric region 29 that is a d _x a, the capacity S · ε _x / d _x, before performing the process S · epsilon
Can be very small than ₂ / d _2, the pinhole 28 will not have the effect of reducing the voltage applied to the dielectric barrier layer.

The dielectric constant of a region having a high dielectric constant and a semiconducting band structure (semiconductor region) used for a dielectric tunnel structure is closely related to its crystal structure, and is chemically or physically as described in the embodiments. By modifying the surface structure by means, the surface permittivity can be significantly reduced, and such treatment does not change the low permittivity barrier to a high permittivity. Even if a pinhole having a harmful effect on the operation of the body tunnel structure is generated, the harmful effect can be easily eliminated.

In addition, since the influence of the surface modification is substantially performed only in a portion having a pinhole, the operation of the device itself is not adversely affected.

As a result, the yield rate of the dielectric tunnel structure can be improved.

〔Example〕

Hereinafter, an embodiment of a method for manufacturing a dielectric tunnel structure of the present invention will be described with reference to the drawings.

(1) First Embodiment FIGS. 1 (a) to 1 (d) are explanatory views of a manufacturing process according to a first embodiment of the present invention.

In this figure, 1 is an Nb-doped SrTiO ₃ layer, 2 is a Si barrier layer, 3 is a pinhole, 4 is a container, 5 is HF: H ₂ O, 6 is a low dielectric constant region, and 7 is an Nb layer.

First step (See Fig. 1 (a)) Nb-doped SrTi with high dielectric constant and semiconducting band structure
On the O ₃ layer 1, a polycrystalline or amorphous Si barrier layer 2 is deposited to a thickness of 60 ° by sputtering.

As described above, since the Si barrier layer 2 is formed to be extremely thin enough to allow carriers to pass through by the tunnel phenomenon, it is difficult to eliminate the pinhole 3 entirely.

Second step (see FIG. 1 (b)) Next, the sample obtained in the first step is taken out of the sputtering apparatus and placed in a HF: H ₂ O (= 1: 10) 5 filled in a container 4 for 10 seconds. Immerse and process.

Third Step (See FIG. 1 (c)) Next, the sample is washed with pure water for 1 minute, dried, mounted again on the sputtering apparatus, and the Nb layer 7 is deposited to a thickness of 2500 °.

Fourth step (see FIG. 1 (d)) Thereafter, the Nb layer 7 and the Si barrier layer 2 are selectively removed by photolithography and reactive dry etching using CF ₄ + 5% O ₂ , and the required size is removed. To form a tunnel structure.

Exposed on the bottom surface of the pinhole 3 of the Si barrier layer 2 by the treatment of the aqueous acid solution in the second step.
Since the low dielectric constant region 6 is formed on the surface of the Nb-doped SrTiO ₃ layer 1, the characteristics of the dielectric tunnel structure do not deteriorate even if the pinhole 3 exists.

The dielectric tunnel structure manufactured according to this embodiment is used as a part of the configuration of the above-described superconducting diode, superconducting base transistor, and the like.

In addition, an aqueous solution of an acid such as a concentrated phosphoric acid aqueous solution (H ₂ PO ₄ ) can be used in addition to the above-mentioned HF: H ₂ O in this embodiment.

(2) Second Embodiment FIGS. 2 (a) to 2 (d) are explanatory views of a manufacturing process according to a second embodiment of the present invention.

In this figure, 8 is the same as that described with the same reference numerals in FIG. 1 except that 8 is an airtight container and 9 is chlorine gas.

First step (see FIG. 2 (a)) On the Nb-doped SrTiO ₃ layer 1 by sputtering
A Si barrier layer 2 is deposited to a thickness of 60 °.

Second Step (See FIG. 2 (b)) Next, the sample obtained in the first step is taken out of the sputtering apparatus and exposed to a chlorine gas 9 filled in an airtight container 8.

Third step (see FIG. 2 (c)) Then, the sample was mounted again on the sputtering device, and the Nb layer 7 was removed.
Is deposited to a thickness of 2500 mm.

Thereafter, the Nb layer 7 and the Si barrier layer 2 are processed by photolithography and reactive dry etching using CF ₄ + 5% O ₂ to form a dielectric tunnel structure of a required size.

By exposing the sample to the etching gas,
A low dielectric constant region 6 is formed on the surface of the Nb-doped SrTiO ₃ layer 1.

(3) Third Embodiment FIGS. 3 (a) to 3 (d) are explanatory views of a manufacturing process according to a third embodiment of the present invention.

In this figure, it is the same as that described with the same reference numerals in FIG. 1 except that 10 is an Al ₂ O ₃ barrier layer and 11 is CF ₄ plasma.

First Step (See FIG. 3 (a)) An Al ₂ O ₃ barrier layer 10 is deposited on the Nb-doped SrTiO ₃ layer 1 by reactive sputtering.

Second Step (See FIG. 3 (b)) Next, the sample is exposed to plasma generated by high-frequency discharge in 10 mTorr of CF ₄ gas without removing the sample from the sputtering apparatus.

Third Step (See FIG. 3 (c)) Next, an Nb layer 7 is deposited on the Al ₂ O ₃ barrier layer 10 to a thickness of 2500 ° without removing the sample from the sputtering apparatus.

Fourth step (see FIG. 3 (d)) Thereafter, the Nb layer 7 and the Al ₂ O ₃ barrier layer 10 are processed by a photolithography technique and reactive dry etching using CF ₄ + 5% O ₂ to obtain a required size. A dielectric tunnel structure is formed.

The low dielectric constant region 6 is formed on the surface of the Nb-doped SrTiO ₃ layer 1 through the pinhole _{3 of} the Al ₂ O ₃ barrier layer 10 by exposing the sample to plasma.

According to the present embodiment, there is an advantage that the process time is shortened because it is not necessary to take out the sample from the sputtering apparatus, and since the surface of the Al ₂ O ₃ barrier layer 10 is not contaminated by wet processing, There is an advantage that the adhesive force is improved when the Nb layer 7 is deposited in the step.

Fourth Embodiment FIGS. 4 (a) to 4 (d) are explanatory diagrams of a manufacturing process according to a fourth embodiment of the present invention.

In this figure, the elements are the same as those described in FIG. 1 except that 12 is an Sb ion.

First Step (See FIG. 4A) A Si barrier layer 2 is deposited on the Nb-doped SrTiO ₃ layer 1 by sputtering.

Step 2 (see FIG. 4 (b)) Next, the sample is taken out of the sputtering apparatus, and Sb ions are directed toward the Si barrier layer 2 by an ion implantation apparatus.
12 is injected at an acceleration voltage of 100 keV by 10 ¹⁵ cm ^-2 .

Third step (see FIG. 4 (c)) Then, the sample is inserted again into the sputtering apparatus,
An Nb layer 7 is deposited on the Si barrier layer 2 to a thickness of 2500 °.

Fourth step (see FIG. 4 (d)) Thereafter, the Nb layer 7 and the Si barrier layer 2 are processed by photolithography and reactive dry etching using CF ₄ + 5% O ₂ to obtain a dielectric having a required size. A body tunnel structure is formed.

By the process of implanting Sb ions 12 into the Si barrier layer 2, Nb-doped SrTi is passed through the pinholes of the Si barrier layer 2.
A low dielectric constant region 6 is formed on the surface of the O ₃ layer 1.

According to the present embodiment, the same advantages as the method using CF ₄ gas as in the third embodiment are obtained, and the thickness of the surface layer where the dielectric constant is reduced can be further increased. There is an advantage that the degree of improvement is further improved.

Fifth Embodiment A Si layer is deposited as a barrier layer by sputtering on a high dielectric constant semiconductor, for example, SrTiO ₃ doped with Nb.

Second step Next, the sample is taken out of the sputtering apparatus and
The upper surface of the barrier layer is irradiated with KrF excimer laser light.

Third step Next, the sample is inserted again into the sputtering apparatus,
An Nb layer having a thickness of 2500 mm is deposited on the Si barrier layer.

Fourth Step After that, the Nb layer and the Si barrier layer are processed by photolithography and reactive dry etching using CF ₄ + 5% O ₂ to form a dielectric tunnel structure of a required size.

By irradiating the surface of the Nb-doped SrTiO ₃ layer with a laser beam, a low dielectric constant region is formed on the surface of the Nb-doped SrTiO ₃ layer through the pinhole of the Si barrier layer.

〔The invention's effect〕

As described above, according to the present invention, even if a pinhole occurs in a barrier layer deposited on a layer having a high dielectric constant and a semiconducting band structure, a low dielectric constant is applied to the surface through the bottom surface of the pinhole. Since the region is formed, the characteristics of the dielectric tunnel structure are not deteriorated, whereby a device such as a superconducting diode or a superconducting base transistor having good characteristics can be formed.

[Brief description of the drawings]

1 (a) to 1 (d) are explanatory views of a manufacturing process according to a first embodiment of the present invention, and FIGS. 2 (a) to 2 (d) are explanatory views of a manufacturing process according to a second embodiment of the present invention. Figures (a) to (d) show the third embodiment of the present invention.
FIGS. 4 (a) to 4 (d) are explanatory views of the manufacturing process of the embodiment, and FIGS. 4 (a) to 4 (d) are explanatory diagrams of the manufacturing process of the fourth embodiment of the present invention.
6B is an explanatory view of a superconducting diode using the dielectric tunnel structure, and FIGS. 6A to 6C are explanatory views of the principle of the manufacturing method of the present invention. 1 ...... Nb-doped SrTiO ₃ layer, 2 ...... Si barrier layer, 3 ...... pinhole, 4 ...... _{vessel, 5 ...... HF: H 2 O} , 6 ...... low dielectric region, 7 ...... Nb layer, 8 ... airtight container, 9 ... chlorine gas,
10 ... Al ₂ O ₃ barrier layer, 11… CF ₄ plasma, 12… Sb ion

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-163811 (JP, A) JP-A-1-102973 (JP, A) JP-A-1-129481 (JP, A) JP-A-57- 126183 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 39/00 H01L 39/22-39/24 H01L 29/06 H01L 29/88-29/96 H01L 49/00 -49/02

Claims (5)

(57) [Claims] A method for manufacturing a dielectric tunnel structure in which a dielectric barrier layer is interposed between a first region having conductivity and a second region having a high dielectric constant and a semiconductor band structure. Depositing a dielectric barrier layer over a second region having a high dielectric constant and a semiconducting band structure; and exposing a bottom surface exposed through a pinhole in the dielectric barrier layer to a bottom surface thereof. Exposing the entire dielectric barrier layer to an aqueous solution of an acid to reduce the dielectric constant of the surface of the second region; and depositing a conductive first region on the dielectric barrier layer. A method for manufacturing a dielectric tunnel structure, comprising: 2. A method for manufacturing a dielectric tunnel structure in which a dielectric barrier layer is interposed between a first region having conductivity and a second region having a high dielectric constant and a semiconductor band structure. Depositing a dielectric barrier layer over a second region having a high dielectric constant and a semiconducting band structure; and exposing a bottom surface exposed through a pinhole in the dielectric barrier layer to a bottom surface thereof. Exposing the entire dielectric barrier layer to a corrosive gas to reduce the dielectric constant of the surface of the second region; and depositing a conductive first region on the dielectric barrier layer. A method for manufacturing a dielectric tunnel structure, comprising: 3. A method for manufacturing a dielectric tunnel structure in which a dielectric barrier layer is interposed between a first region having conductivity and a second region having a high dielectric constant and a semiconductor band structure. Depositing a dielectric barrier layer over a second region having a high dielectric constant and semiconducting band structure; and Exposing the entire dielectric barrier layer to plasma obtained by discharging in gas to reduce the dielectric constant of the surface of the second region; and forming a first conductive region on the dielectric barrier layer. A method for manufacturing a dielectric tunnel structure, comprising: 4. A method of manufacturing a dielectric tunnel structure in which a dielectric barrier layer is interposed between a first region having conductivity and a second region having a high dielectric constant and a semiconductor band structure. Depositing a dielectric barrier layer over a second region having a high dielectric constant and a semiconducting band structure; and exposing a bottom surface exposed through a pinhole in the dielectric barrier layer to a bottom surface thereof. Irradiating the dielectric barrier layer with accelerated ions to reduce the dielectric constant of the surface of the region 2; and depositing a conductive first region on the dielectric barrier layer. A method for manufacturing a dielectric tunnel structure, comprising: 5. A method for manufacturing a dielectric tunnel structure in which a dielectric barrier layer is interposed between a first region having conductivity and a second region having a high dielectric constant and a semiconductor band structure. Depositing a dielectric barrier layer over a second region having a high dielectric constant and semiconducting band structure; and Irradiating an electromagnetic wave toward the dielectric barrier layer to reduce the dielectric constant of the surface of the second region, and depositing a conductive first region on the dielectric barrier layer. A method for manufacturing a dielectric tunnel structure, comprising: