JP3012563B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a built-in oscillation circuit, and more particularly, to a method of forming a capacitor in an oscillation circuit portion by oxidizing a first polysilicon layer below a two-layer polysilicon layer. The present invention relates to a semiconductor integrated circuit whose capacitance value determines the oscillation characteristics of an oscillation circuit.

[0002]

2. Description of the Related Art Referring to FIG. 3 which shows a circuit diagram of a conventional oscillation circuit section of this type in a semiconductor integrated circuit, this oscillation circuit section 1b is an example in which a two-layer polysilicon is used for a capacitive element. P-channel type between potential and ground potential
OS transistor (hereinafter referred to as Pch transistor)
P1 and N-channel MOS transistors (hereinafter referred to as N
N1 are connected in series, and the gate electrode of the Pch transistor P1 is connected to the ground potential. The drain electrode serving as each series connection point is connected to a capacitive element C
1, and to the input terminal of the next-stage inverter G1. The output terminal of the inverter G1 is further cascaded with the inverter G2. The output terminal of the inverter G2 connects the Pch transistor P2 and the Nch transistor N2 connected in series between the power supply potential and the ground potential in series, and connects to the gate electrode of the Nch transistor N2. The gate electrode of the Pch transistor P2 is connected to the ground potential, the drain electrode of the series connection point is connected to the ground potential via the capacitor C2, and further connected to the input terminal of the next-stage inverter G3. This is a circuit that extracts an oscillation output signal from the output terminal OUT of the inverter G3 and connects this signal to the gate electrode of the Nch transistor N1.

When a power supply voltage is supplied to a power supply terminal, Pc
Since the gate electrodes of the h transistors P1 and P2 are connected to the ground potential and maintain the low level, the transistors are always on when the power supply potential exceeds the threshold, and the transistors P1 and P2 are connected through the Pch transistors P1 and P2, respectively. The corresponding capacitance elements C1 and C2 are charged to the power supply potential.

Here, as a state of the oscillation circuit section 1b at a certain point, a case where the Nch transistor N2 is in a cutoff state is considered.

[0005] The capacitive element C2 is charged by the Pch transistor P2, and the input potential of the inverter G3 becomes the high level of the power supply potential. At this time, the output of the inverter G3,
That is, the output OUT of the oscillation circuit section 1b is at a low level.

The Nch transistor N1 connected to input the output OUT is in a non-conductive state because the input of the gate electrode is at a low level, and the capacitance element C1
Is charged by the Pch transistor P1. The charged high level causes the inverter G1
Of the gate electrode of the inverter G rises, and the potential
When the threshold voltage exceeds 1, the output voltage of the inverter G1 goes low and the output of the inverter G2 goes high.

Due to the high level of the output of the inverter G2, the potential of the gate electrode of the Nch transistor N2 in the next stage rises, and the potential of the Nch transistor N2 rises.
When the threshold voltage is exceeded, the transistor becomes conductive.

If the driving capability of the Nch transistor N2 is designed to be sufficiently larger than the driving capability of the Pch transistor P2, the electric charge charged in the capacitor C2 is discharged to the ground potential through the Nch transistor N2. , The potential of the gate electrode of the inverter G3 decreases,
When the potential falls below the threshold voltage of the inverter G3, the output voltage of the inverter G3 and the output OUT of the oscillation circuit section 1b change from a low level to a high level.

Further, when the output OUT changes to the high level, the Nch transistor N1 to which the output OUT is input also becomes conductive because the potential of the gate electrode thereof becomes the high level, and similarly, the output of the inverter G1 also becomes the low level. From the high level to the high level, and the output of the inverter G2 changes from the high level to the low level.

Due to the output low level of the inverter G2, the potential of the gate electrode of the next-stage Nch transistor N2 also decreases. When the potential falls below the threshold voltage of the Nch transistor N2, the Nch transistor N2 is turned off again, and the oscillation circuit is turned off. The output OUT also goes low.

By repeating the above-described operation, the output OUT repeats the high level and the low level, and oscillation is performed.

The oscillation characteristics at this time are determined by the capacitance elements C1 and C2.
, The larger the capacitance value of the capacitance elements C1 and C2, the longer the charge and discharge time and the lower the oscillation frequency. When the capacitance values of the capacitance elements C1 and C2 are small, the charge / discharge time of the capacitance elements C1 and C2 becomes short and the oscillation frequency becomes high. Therefore, the oscillation characteristics of the oscillation circuit section 1b1 greatly depend on the capacitance values of the capacitors C1 and C2.

Next, a description will be given of a method of forming a capacitance element constituting this oscillation circuit with an interlayer capacitance of two-layer polysilicon.

The capacitive element C constituting the oscillation circuit section 1b
Referring to FIG. 4A showing the relationship between the equalizer circuit of FIG. 1 and C2 and the two layers and FIG. 4B showing the sectional view thereof, the first polysilicon 3 and the second polysilicon 3 are formed on the semiconductor substrate 6. The polysilicon 4 is insulated by the insulating film 5, and the capacitance element C1 or C2
Is formed. At this time, the insulating film 5 is formed by oxidizing the first polysilicon 3.

[0015]

In the above-described conventional semiconductor integrated circuit having a built-in oscillation circuit portion using a two-layer polysilicon, that is, a capacitance value formed by an interlayer capacitance between the first polysilicon and the second polysilicon. In addition, there is a drawback that the interlayer capacitance value varies due to a variation in the semiconductor manufacturing process, and the oscillation characteristics greatly vary.

The reason will be described with reference to FIG. 4B and FIG. 5 showing its oscillation characteristics. In FIG. 5, FIG. 5 (a) shows the first polysilicon with respect to the impurity concentration of the first polysilicon.
FIG. 5B is a diagram illustrating a change in the thickness of the insulating film after polysilicon oxidation, and FIG. 5B is a diagram illustrating a change in the interlayer capacitance value with respect to the insulating film. FIG. 5C is a diagram showing a change in the interlayer capacitance value with respect to the impurity concentration of the first polysilicon.
(D) is a diagram showing a change in the layer resistance of the first polysilicon with respect to the impurity concentration of the first polysilicon. FIG.
(E) is a diagram showing a change in the oscillation frequency with respect to the impurity concentration of the first polysilicon.

Referring to FIG. 4B, in the sectional structure of the capacitive element, the capacitance values of capacitive elements C1 and C2 are determined by the area of second-layer polysilicon 4 and the thickness of insulating film 5.

As described above, the insulating film 5 is formed by oxidizing the first-layer polysilicon 3.
The relationship between the impurity concentration in the layer polysilicon and the thickness of the insulating film formed when the first layer polysilicon is oxidized is:
Referring to FIG. 5A, it is known that the film thickness increases as the impurity concentration increases.

Referring to FIG. 5B, as the thickness of the insulating film increases, the capacitance value decreases. That is, referring to FIG. 5C, the capacitance values of the capacitance elements C1 and C2 formed using the two-layer polysilicon tend to decrease as the impurity concentration in the first-layer polysilicon increases. .

Therefore, when the impurity concentration of the first polysilicon changes due to a change in the semiconductor manufacturing process, the capacitance values of the capacitors C1 and C2 also change. At this time, as described above, since the oscillation characteristics of the oscillation circuit section 1b greatly depend on the capacitance values of the capacitors C1 and C2, there is a disadvantage that the oscillation characteristics also vary (FIG. 5E )
Of the conventional example).

An object of the present invention has been made in view of the above-mentioned drawbacks of the related art, and a capacitive element for determining oscillation characteristics is formed by oxidizing a first polysilicon which is a lower layer of a two-layer polysilicon. In a semiconductor integrated circuit that incorporates an oscillation circuit unit that uses a built-in capacitance element, by suppressing fluctuations in oscillation characteristics caused by fluctuations in the semiconductor manufacturing process, it is possible to provide a highly reliable and high-performance product. is there.

[0022]

A semiconductor integrated circuit according to the present invention comprises a first and a second polysilicon layer on a semiconductor substrate.
Oscillation circuit that oscillates by charging and discharging a plurality of formed capacitive elements
In the semiconductor integrated circuit with a built-in unit, the oscillation circuit
Means include the first and second polysilicon layers.
A resistance element formed by a layer resistance of a lower first polysilicon layer
Charge current flowing from the power supply potential to the capacitive element
Control means for controlling the amount is provided separately from the oscillation circuit section.
And the first and the above due to the variation of the manufacturing process.
The concentration of the second polysilicon layer fluctuates, and the capacitance of the capacitor element changes.
The amount and the resistance of the resistance element are set to predetermined design values.
If the built-in power supply is out of range ,
In response to the supply, the control means may determine the predetermined design
The second element is caused by the resistance element having a resistance value deviated from the second value.
The emission in a direction to offset the variation in the concentration of the silicon layer.
Controlling the oscillation circuit section and the above-described capacitor built in the oscillation circuit section.
It has a function of suppressing the displacement of the capacitance value of the quantum element .

Further, the control means includes a power supply potential and a connection potential.
Connect the resistance element and gate to the power supply potential between the ground potential
Connected N-channel MOS transistors in series.
The resistance element and the N-channel MOS transistor.
The divided voltage determined by the resistance value of each transistor
Multiple cascaded inverters that make up the oscillation circuit section
Driving capability of each P-channel MOS transistor
Can be controlled .

Further, a plurality of charge / discharge circuits in the oscillating circuit section are provided.
The number of oscillation capacitance elements is controlled by the control means.
Each can be charged according to the driving ability .

[0025]

[0026]

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An oscillation circuit section incorporated in a semiconductor integrated circuit according to the present invention is characterized in that a capacitance element for determining oscillation characteristics is obtained by oxidizing a first polysilicon layer which is a lower layer of upper and lower polysilicon layers. In the oscillation circuit that is formed, the first polysilicon is replaced with a conventional oscillation circuit in which the capacitance value of the capacitive element also changes with the change in the impurity concentration of the lower first polysilicon and, as a result, the oscillation characteristic also changes. The oscillation circuit section is controlled by a control means used as a resistance element, thereby canceling fluctuations in oscillation characteristics.

First, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. Referring to FIG. 1, this semiconductor integrated circuit has an oscillation circuit section 1a and a control circuit section 2 for controlling the oscillation circuit section 1a. The oscillation circuit section 1a connects a Pch transistor P1 and an Nch transistor N1 in series between a power supply potential and a ground potential, and connects a drain electrode serving as a series connection point to the ground potential via a capacitive element C1 and to the next stage. To the input terminal of the inverter G1.

The output terminal of the inverter G1 is further cascaded with an inverter G2. The output terminal of the inverter G2 is connected to the gate electrode of the Nch transistor N2 of the Pch transistor P2 and the Nch transistor N2 connected in series between the power supply potential and the ground potential. And to the input terminal of the inverter G3 connected to the next stage.

An oscillation output signal is extracted from the output terminal OUT of the inverter G3, and the output terminal OUT is connected to N
It is also connected to the gate electrode of the channel transistor N1. Further, the gate electrodes of the Pch transistors P1 and P2 are configured to be connected to the output terminal of the control circuit unit 2.

The control circuit unit 2 connects the resistance element R1 and the Nch transistor N3 in series between the power supply potential and the ground potential, connects the gate electrode of the Nch transistor N3 to the power supply potential, and connects the drain electrode of the Nch transistor N3 to the power supply potential. This is a circuit configured as a control signal output terminal.

Referring to FIG. 2 showing a sectional view of the structure of the resistance element used in the control circuit section 2 described above, this resistance element R
1, a first-layer polysilicon 3 is formed on a semiconductor substrate 6 by using a general CMOS manufacturing process, and an insulating film 8 formed on the first-layer polysilicon is selectively removed. An electrode 9 is formed in the removed portion, and a resistance element R1 is formed by connecting the electrode 9 and the first polysilicon layer (R1 in the resistance element equivalent circuit of FIG. 2).

The basic operation of the oscillation circuit section 1a is the same as that of the above-described conventional oscillation circuit section 1a. Therefore, when a product is manufactured in a state where the impurity concentration of the first polysilicon deviates from the original design value due to a change in the semiconductor manufacturing process,
When this semiconductor integrated circuit is operated, the capacitance elements C1, C
The capacitance value of No. 2 fluctuates from a previously designed value, and with this fluctuation, the oscillation characteristic of the oscillation circuit section 1a also fluctuates.

Referring again to FIG. 5 showing the above-mentioned oscillation characteristics, in the operation of this embodiment, since the resistance element R1 constituting the control circuit section 2 is also formed of the first polysilicon, for example, As the impurity concentration of 1 polysilicon increases, the layer resistance of the first polysilicon decreases (FIG. 5D), and therefore, the resistance element R1 is commercialized with a low resistance value.

The Nch transistor N3 constituting the control circuit 2 is always in a conductive state because its gate electrode is fixed to the power supply potential. Therefore, during operation, the output voltage of the control circuit unit 2 becomes a voltage value obtained by dividing the power supply voltage VDD by the resistance value of the resistance element R1 and the on-resistance value of the Nch transistor N3, and when the resistance value of the resistance element R1 decreases, the control circuit The output voltage of the section 2 rises to the power supply voltage VDD side, and when the resistance value of the resistance element R1 increases, the output voltage of the control circuit section 2 drops to the ground potential side.

As described above, the oscillation characteristics of the oscillation circuit section 1a vary depending on the capacitance values of the capacitance elements C1 and C2, and the capacitance values of the capacitance elements C1 and C2 are determined by the impurity of the first polysilicon constituting the capacitance element. Varies with concentration.

Here, when the impurity concentration of the first polysilicon 3 forming the capacitance elements C1 and C2 is high, the capacitance values of the capacitance elements C1 and C2 decrease as described above, and the oscillation circuit section 1a In the oscillation operation of the capacitor C1,
Since the charge / discharge time of C2 is shortened, the on / off operation cycle of the oscillating operation is shortened, and therefore, it acts in the direction of increasing the oscillation frequency.

At this time, since the resistance value of the resistance element R1 is reduced by increasing the impurity concentration of the first polysilicon 3, the output voltage of the control circuit unit 2 rises to the power supply potential level. When the output voltage of the control signal output from the output terminal of the control circuit unit 2 rises, the oscillation circuit unit 1
The input potentials of the gate electrodes of the Pch transistors P1 and P2 constituting a also increase, and the current between the source and the drain decreases, so that the current driving capability decreases.

Here, a case where the Nch transistor N2 is in a cut-off state as an example of the state of the oscillation circuit section 1a at a certain point will be described. The capacitance element C2 having a reduced capacitance value because the impurity concentration of the first polysilicon is high.
Are charged by the Pch transistor P2 having a reduced current driving capability in a state where the charging period is long, and the inverter G
The input potential of No. 3 is at the high level of the power supply potential. At this time, the output of the inverter G3, that is, the oscillation circuit unit 1
The output OUT of a is at a low level.

The Nch transistor N1 connected to input the output OUT is in a non-conductive state because the input of the gate electrode is at the low level, and the capacitance element C1
Is charged by the Pch transistor P1, but as described above, Pc having a reduced current drive capability
The corresponding capacitive element C1 is charged to the power supply potential via the h transistor P1.

Since the current drive capability of the Pch transistor P1 is also reduced, the charging time of the capacitor C1 is also increased, so that the on / off operation cycle of the oscillating operation is lengthened, thus acting to lower the oscillating frequency.

The potential of the gate electrode of the inverter G1 rises due to the high level charged while the charging time is prolonged, and when the potential exceeds the threshold voltage of the inverter G1, the output voltage of the inverter G1 goes low. The output of the inverter G2 becomes high level.

Due to the high level of the output of the inverter G2, the potential of the gate electrode of the Nch transistor N2 connected to the next stage rises, and when the potential exceeds the threshold voltage of the Nch transistor N2, it becomes conductive. .

The driving capability of Nch transistor N2 is Pc
Since the driving capacity of the transistor P2 is designed to be sufficiently larger than that of the
2 is discharged to the ground potential through the Nch transistor N2. Therefore, the potential of the gate electrode of the inverter G3 decreases toward the low level. And the output O of the oscillation circuit section 1a.
The UT changes from a low level to a high level.

Further, when the output OUT of the oscillation circuit section 1a changes to the high level, the Nch transistor N1 to which the output OUT is input also becomes conductive because the potential of the gate electrode thereof becomes the high level. The output of G1 also changes from low level to high level, and the output of inverter G2 changes from high level to low level.

By repeating the above operation, the oscillation is performed in such a manner that the capacitance of the capacitive element is reduced even if the capacitance of the capacitive element is reduced due to a variation in the manufacturing process, that is, the oscillation cycle is lengthened.

When the impurity concentration of the first polysilicon constituting the capacitor is low, the capacitance of the capacitor C
1, the capacitance value of C2 increases and acts in the direction of lowering the oscillation frequency. However, the output voltage of the control circuit unit 2 increases the layer resistance value of the first polysilicon, and the resistance elements R1 and Nc
The divided voltage with the h transistor N3, that is, the output voltage of the control circuit unit 2 drops to the ground potential side. Since the Pch transistors P1 and P2 operate so as to be activated by the decrease to the ground potential, the current driving capability is increased and the oscillation frequency is increased.

This operation is also repeated in the same manner as the above-described operation.
The capacitance value of C2 is large → charging time is short → oscillation cycle is short,
It can be understood that the same operation is performed by reading each of the above, and the description is omitted here. Therefore, even though the capacitance of the capacitive element is increased due to a variation in the manufacturing process, oscillation is performed in such a manner as to cancel the capacitance, that is, oscillation is performed in a direction to shorten the oscillation period, and the oscillation frequency is controlled so as to increase. Settle down to a pre-determined frequency.

By the above-described control operation, the control circuit section 2 can check that the oscillation characteristics of the oscillation circuit section 1a fluctuate even if the control circuit section 2 is commercialized with the impurity concentration of the first polysilicon forming the capacitance element fluctuated. Performs the suppression function (Fig. 5
(E) Characteristic value of the present invention). Therefore, the frequency is kept constant.

The control circuit 2 is an N-channel type MOS.
Since the transistor N3 is always in a conductive state, a current flows from the power supply potential to the ground potential. However, the resistance value of the resistance element R1 and the ON resistance value of the N-channel MOS transistor N3 can be designed to be large. Thus, current consumption can be reduced.

[0051]

As described above, the semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a built-in oscillating circuit section including a plurality of capacitive elements for determining oscillation characteristics. Capacitive element using polysilicon and 2
A resistance element using a layer resistance of a lower first polysilicon layer of the layer polysilicon, wherein the layer resistance of the resistance element and the capacitance value of the capacitance element are embedded in a state deviated from predetermined values due to fluctuations in the manufacturing process. And a control means for taking out this shift as a voltage change at the time of operation and suppressing a change in the oscillation characteristic of the oscillation circuit unit in response to the voltage change, the control means comprising an impurity concentration in the first polysilicon. When the capacitance value of a plurality of capacitance elements changes due to fluctuations in the oscillation characteristics, the charging time of each capacitance element is controlled in response to a voltage change corresponding to the simultaneously changing resistance value, and the oscillation frequency before the fluctuation Since the fluctuation of the capacitance value is canceled out so as to be equal to the above, the fluctuation of the oscillation characteristic of the oscillation circuit section which fluctuates from the range of the design value due to the fluctuation of the semiconductor manufacturing process is suppressed.

Therefore, a high-performance product having a stable oscillation frequency can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a sectional structural view of a resistance element constituting the oscillation circuit section of the present invention.

FIG. 3 is a circuit diagram illustrating an example of a conventional oscillation circuit unit.

FIG. 4A is an equivalent circuit diagram of a capacitive element. (B) is a sectional structural view thereof.

FIG. 5 is a diagram of oscillation characteristics used for explaining the operation of the conventional example and the present invention.

[Explanation of symbols]

 1a, 1b Oscillation circuit section 2 Control circuit section 3 First polysilicon 4 Second polysilicon 5 Insulating film 6 Semiconductor substrate 8 Insulating film 9 Electrode P1, P2, Pch transistor N1, N2, N3 Nch transistor G1, G2, G3 Inverter C1, C2 Capacitance element R1 Resistance element OUT Output of oscillation circuit

Claims (3)

(57) [Claims] 1. A first and second policy on a semiconductor substrate.
Oscillates due to charging and discharging of multiple capacitance elements formed by the recon layer
In a semiconductor integrated circuit having a built-in oscillating circuit means, the oscillating circuit means comprises the first and second policies.
Formed by the layer resistance of the lower first polysilicon layer of the recon layer
Having a resistance element formed and flowing from the power supply potential to the capacitance element.
Control means for controlling the amount of charging current is
In addition to the above,
The concentration of the first and second polysilicon layers fluctuates,
The capacitance value of the capacitance element and the resistance value of the resistance element are predetermined.
The control means responds to the supply of the power supply voltage by
The resistance element whose resistance value deviates from the determined design value
Offset the variation in the concentration of the second polysilicon layer.
Control the oscillation circuit section in the direction
A device for suppressing a deviation of the capacitance value of the stored capacitance element
A semiconductor integrated circuit having a function . 2. The control means according to claim 1, wherein said control means comprises a power supply potential and a ground potential.
The resistance element and the gate are connected to the power supply potential
Constructed by connecting N-channel MOS transistors in series
The resistance element and the N-channel MOS transistor
The above voltage is generated by the divided voltage determined by the resistance value of each transistor.
Cascaded inverters and
The driving capability of each P-channel MOS transistor
2. The semiconductor integrated circuit according to claim 1, which controls . 3. A plurality of oscillators charged and discharged by said oscillation circuit section.
The transfer capacitance element is provided with the driving capability controlled by the control means.
The semiconductor integrated circuit according to claim 2, wherein that will be charged respectively in response to a force.