JP3012559B2 - Voltage controlled current switch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage-controlled current switch circuit, and more particularly to a switch-on control voltage that can be arbitrarily set, and a current value at the time of the switch-on being linearly controlled by the control voltage. To a voltage-controlled current switch circuit that can

[0002]

2. Description of the Related Art As an example of a conventional voltage-controlled current switch circuit of this type, for example, as disclosed in Japanese Patent Application Laid-Open No. 4-156716, a voltage is applied to the gate of a MOS transistor, and Turn on MOS transistor
It is common to use / OFF control. FIG. 8A is a circuit diagram showing an example of the conventional MOS type voltage controlled current switch circuit. As shown in FIG. 8A, in the conventional example, PMOS transistors 110 and 111 forming a first current mirror circuit are provided.
And an NMOS transistor 112 forming a differential amplification pair
And 113, and NMOS transistors 112 and 1
The gate 13, the control voltage source 114 and the reference voltage source 11 for applying a respective control voltage V _C and the reference voltage V _R
5, a constant current source (current I) 116 connected between the common connection point of the sources of the NMOS transistors 112 and 113 and the ground point, a PMOS transistor 117,
An NMOS transistor 118 connected between the drain of the PMOS transistor 117 and the ground,
A constant voltage source 119 for applying a constant voltages V ₁ to the gates of the transistors 118 to form an inverter 120, a constant current source (current I) 119, a second current mirror circuit N
MOS transistors 122 and 124 and NMOS transistor 123 functioning as a voltage control current switch
Power supply terminal 125, output terminal 126, and ground terminal 1
27.

FIG. 8B shows a conventional example.
FIG. 9 is an operation waveform diagram showing current output characteristics of an output current corresponding to a change in a control voltage V _C of a control voltage source 114 applied to the gate of an NMOS transistor 112.

[0004] In FIG. 8 (a), in gradually Yuku raising process than the level of the control voltage V _C of the control voltage source 114 0V applied to the gate of the NMOS transistor 112, the level of the control voltage V _C, NMOS In a state lower than the level of the reference voltage V _R applied to the gate of the transistor 113, the NMOS transistor 1
12, the drain current of the NMOS transistor 112, that is, the voltage applied to the gate of the PMOS transistor 117 increases, and the drain current of the PMOS transistor 117 increases.
Reference numeral 17 denotes an OFF state. For this reason, the input level of the inverter 120 whose input side is connected to the drain of the PMOS transistor 117 becomes 0 V,
The output of the “H” level (V _DD ) inverter 120 is N
The signal is input to the gate of the MOS transistor 123. As a result, the NMOS transistor 123 is turned on, and NM
The drain voltage of OS transistor 123 drops to “L” level (0 V). Therefore, the NMOS transistor 124 receiving the input of the “L” level (0 V) at the gate
Is in the OFF state, and the output current I ₀ is not output from the output terminal 126. That is, the control voltage V _C is
When in the range of V _C ≦ V _R, the output current is zero. This operation state is as clearly shown in the operation waveform diagram of FIG.

If the level of the control voltage V _C increases beyond the level of the reference voltage V _R , the NMOS
The drain current of the transistor 112 tends to gradually increase, whereby the drain voltage of the NMOS transistor 112 decreases, and accordingly, the PMOS transistor 117 is turned on. As a result, the input level to the inverter 120 becomes “H” level (V _DD ), and the output level of the inverter 120 becomes “L” level (0 V) and is input to the gate of the NMOS transistor 123. In response, NMOS transistor 1
23 is in the OFF state, the drain voltage of the NMOS transistor 123 becomes “H” level (V _DD ), and is applied to the gates of the NMOS transistors 122 and 124. In response to this, the operation function of the second current mirror circuit causes the NMOS transistor 12 to operate.
4, the output current I ₀ is output to the outside via the output terminal 126. That is, the control voltage V _C is, V _C
> If in the range of V _R, the output current of the constant current I
Output to the outside as ₀ . This state is clearly shown in the operation waveform diagram of FIG.

[0006]

In the above-described conventional voltage-controlled current switch circuit, the control voltage V _C is changed to V _C
≦ V output current 0 if the range of _R, and the control voltage V _C is the case in the range of V _C> V _R, the output current is output constant current to the outside as I Thus, the output current is output or the output current is not output, and only the state is switched. After the output current is turned on by the switch function, the output current value is changed. Cannot be realized by changing the output voltage linearly in response to a change in the control voltage, or by setting the output current value to a specific current value and outputting it. Is disadvantageously limited.

The reason is that the NMOS transistor 112
And 113, the reference voltage V
_{On the} basis of the result of comparison and comparison between _R and the control voltage V _C , ON / OF of the NMOS transistor 123 functioning as a switch is performed.
F is controlled, the NMOS transistor 1
This is because the ON / OFF operation of 23 is directly linked to ON / OFF of the output current.

An object of the present invention is to turn on / off the output current after the control voltage exceeds the reference voltage, and when the output current is ON, the output current is changed linearly in accordance with the control voltage. It is an object of the present invention to realize a voltage-controlled current switch circuit that can be controlled so as to change the output and output.

[0009]

According to a first aspect of the present invention, a voltage controlled current switch circuit has a source individually connected to a high potential power supply, both gates are interconnected, and one gate is connected to a drain. And the first and second PMOS transistors forming the first current mirror circuit are connected to the high-potential power supply, respectively, and both gates are connected to each other to form one of the gates. Are connected to the drain to form a second current mirror circuit to form a second current mirror circuit, and the drains of the second and third PMOS transistors whose gates are connected to the drain have drains respectively. Are individually connected, and a predetermined reference voltage and a control voltage are individually applied to the gate,
First and second NMOS transistors having sources connected together to form a differential amplification pair;
The drain and the gate are individually connected to the constant current source connected between the common connection point of the sources of the NMOS transistors and the low potential power supply, and to the drains of the first and fourth PMOS transistors. And third and fourth NMOS transistors, both gates of which are connected to each other and a source commonly connected to the low potential power supply to form a third current mirror circuit; the high potential power supply and the fourth PMOS transistor And the drain connected to the fourth PM
The drain and the current output terminal of the OS transistor are individually connected, the gates are interconnected, and the source is connected to the low potential power supply to form fifth and sixth current mirror circuits. NMO
An S transistor, wherein the second and third PMOS transistors and the third and fifth NMOS transistors are both configured such that their drains and gates are connected.

In the voltage controlled current switch circuit according to the second invention, the sources are individually connected to the high-potential power supply, both gates are interconnected, and one gate is connected to the drain. The first and second PMOS transistors forming the first current mirror circuit, the sources are individually connected to the high potential power supply, the two gates are interconnected, and one gate is connected to the drain Third and fourth PMOS transistors to form a second current mirror circuit, and the second and third PMOS transistors each having a gate connected to a drain.
The drains of the S transistors are individually connected to the drains, the control voltage and the predetermined reference voltage are individually applied to the gates, and the sources are commonly connected to form a first and a second pair of differential amplifiers. The second N
MOS transistor and the first and second NMOSs
A constant current source connected between a common connection point of the sources of the transistors and a low potential power source;
The drain and gate of the S transistor are individually connected to the drain and the gate, both gates are interconnected, and the source is commonly connected to the low potential power supply to form a third current mirror circuit. A fourth NMOS transistor, a capacitor connected between the high potential power supply and the drain of the fourth PMOS transistor, and a drain connected to a drain and a current output terminal of the corresponding fourth PMOS transistor. , Each connected separately, the gates are interconnected,
A fifth and a sixth NMOS transistor having a source connected to the low potential power supply to form a fourth current mirror circuit;
The OS transistor and the third and fifth NMOS transistors are both configured such that their drains and gates are connected.

In the voltage controlled current switch circuit according to a third aspect of the present invention, the sources are individually connected to the high potential power supply, the two gates are interconnected, and one gate is connected to the drain. The first and second PMOS transistors forming the first current mirror circuit, the sources are individually connected to the high potential power supply, the two gates are interconnected, and one gate is connected to the drain Third and fourth PMOS transistors to form a second current mirror circuit, and the second and third PMOS transistors each having a gate connected to a drain.
The drains of the S transistors are individually connected to each other, a predetermined reference voltage and a control voltage are individually applied to the gates, and the sources are commonly connected to form a first and a second pair of differential amplifiers. The second N
MOS transistor and the first and second NMOSs
A constant current source connected between a common connection point of the sources of the transistors and a low potential power source;
The drain and gate of the S transistor are individually connected to the drain and the gate, both gates are interconnected, and the source is commonly connected to the low potential power supply to form a third current mirror circuit. A fourth NMOS transistor and a source are individually connected to the high-potential power supply, both gates are interconnected, and a drain and a current output terminal of the fourth PMOS transistor are respectively connected to a drain and a current output terminal. Are connected individually to form a fourth current mirror circuit, and the fifth and sixth PMOS transistors are connected to each other.
And at least a capacitor connected between the drain of the PMOS transistor and the ground potential.
The third and fifth PMOS transistors and the third NMOS transistor are both configured such that their drains and gates are connected.

In the first, second and third inventions, the first and second N forming the differential amplifier pair
When connecting the source of the MOS transistor and a common connection point between the constant current source, the first and second N
A predetermined resistor may be inserted and connected between the source of the MOS transistor and the common connection point.

Further, in the voltage controlled current switch circuit according to a fourth aspect of the present invention, the sources are individually connected to the high-potential power supply, both gates are interconnected, and one gate is connected to the drain. The first and second PMOS transistors forming the first current mirror circuit, the sources are both connected to the high potential power supply via a predetermined constant current source, and the predetermined reference voltage and the control voltage are individually applied to the gate. To form a differential amplifier pair
And a fourth PMOS transistor and a drain are individually connected to a drain of the corresponding first PMOS transistor and a drain of the third PMOS transistor, respectively. A gate is interconnected, and a source is connected. First and second NMOs connected to the low potential power supply to form a second current mirror circuit
An S transistor and a drain corresponding to the fourth P
MOS transistor drain and said second PMO
A third and a fourth NMOS transistor which are individually connected to the drain of the S transistor, have their gates interconnected, and have their sources connected to the low potential power supply to form a third current mirror circuit; , The sources are individually connected to the high potential power supply, and both gates are interconnected.
Fifth and sixth PMOS transistors each having a drain individually connected to a drain and a current output terminal of the PMOS transistor to form a fourth current mirror circuit.
An S transistor; and a capacitor connected between the drain of the fifth PMOS transistor and the ground potential. The first and fifth PMOS transistors and the second and third NMOS transistors The transistor is characterized in that both the drain and the gate are connected.

According to the fourth aspect of the present invention, when the sources of the third and fourth PMOS transistors forming the differential amplifier pair are connected to a common connection point between the constant current source, A predetermined resistor may be inserted and connected between the source of the third and fourth PMOS transistors and the common connection point.

In the voltage controlled current switch circuit according to a fifth aspect of the present invention, the emitters are individually connected to the high potential power supply, both bases are interconnected, and one base is connected to the collector. First and second PNP transistors forming a first current mirror circuit, emitters are individually connected to the high potential power supply, both bases are interconnected, and one base is connected to the collector. Third and fourth PNP transistors connected to form a second current mirror circuit, and the second and third PNP transistors having a base connected to a collector
The collectors of the PNP transistors are individually connected, a predetermined reference voltage and a control voltage are individually applied to the base, and the emitters are commonly connected to form a differential amplifier pair. And a second NPN transistor, and the first and second NPN transistors.
Collectors are individually connected to the constant current source connected between the common connection point of the emitters of the PN transistors and the low potential power supply, and the collectors of the first and fourth PNP transistors. A third and fourth N are interconnected with a base and have an emitter commonly connected to the low potential power supply to form a third current mirror circuit.
A PN transistor, the high-potential power supply, and the fourth PN
A capacitor connected to the collector of the P transistor;
A collector is individually connected to a collector and a current output terminal of the corresponding fourth PNP transistor, a gate is interconnected, and an emitter is commonly connected to the low-potential power supply to form a fourth current supply terminal. At least fifth and sixth NPN transistors forming a mirror circuit, wherein the second and third PNP transistors and the third and fifth NPN transistors both have a collector and an emitter connected to each other It is characterized by being done.

In the fifth aspect, when connecting the common connection point between the emitters of the first and second NPN transistors forming the differential amplifier pair and the constant current source, A predetermined resistor may be inserted and connected between the emitters of the first and second NPN transistors and the common connection point.

[0017]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, PMOS transistors 2 and 3 forming a current mirror circuit 1, PMOS transistors 5 and 6 forming a current mirror circuit 2, and NM forming a differential amplifier pair 7
The OS transistors 8 and 9, the gate of the NMOS transistor 8 and 9, a reference voltage source 10 and voltage source 11 applies a reference voltage V _R and the control voltage V _C, respectively, the source and the ground point of the NMOS transistors 8 and 9 A constant current source (current I) 12, NMOS transistors 14 and 15 forming a current mirror circuit 13, NMOS transistors 17 and 18 forming a current mirror circuit 16, a capacitor 19,
A power supply terminal 20, an output terminal 21, and a ground terminal 22 are provided.

FIG. 2A, FIG. 2B and FIG.
FIG. 5 is an operation waveform diagram showing characteristics of a current of each unit and an output current I ₀ corresponding to a change in the control voltage V _C of the control voltage source 11 applied to the gate of the NMOS transistor 9 in the present embodiment.

In FIG. 1, source currents of PMOS transistors 2 and 3 included in current mirror circuit 1 are denoted by I ₃ and I ₁ , respectively, and source currents of PMOS transistors 5 and 6 included in current mirror circuit 4 are denoted by I ₃ and I ₁ , respectively. Assuming that the output current at the output terminal 21 is I ₀ as I ₂ and I ₄ , the currents I ₀ , I ₁ , I ₂ , I ₃ , I ₄ , I ₅ and I ₆ shown in FIG. Each can be represented as follows.

Here, k = (μn · C _0X / 2) · (W / L) μn: electron mobility C _0x : oxide film capacity W: gate width of MOS transistor L: gate length of MOS transistor Expression) is a relational expression between the input voltage and the drain current in the differential amplification pair of the MOS transistor, and is described in “Semiconductor Circuit Design Technology: McGraw-Hill Company (November 12, 1987)
Days), p. 309 ". Also, PMOS
Transistors 2 and 3 and PMOS transistors 5 and 6 form current mirror circuits 1 and 4, respectively, and therefore currents I ₁ , I ₂ , I ₃ and I ₄
The following equation holds.

I ₁ = I ₃ ……………………………………………… (2) I ₂ = I ₄ ………………………… (3) NMOS transistor 8 forming differential amplifier pair 7
The following equation is established by the characteristics of (9) and (9).

I ₂ = I−I ₁ (4) Then, the following equation is obtained from the characteristics of the NMOS transistors 17 and 18 forming the current mirror circuit 16.

I ₆ = I ₄ −I ₅ = I ₀ (5) Furthermore, from the characteristics of the NMOS transistors 14 and 15 forming the current mirror circuit 13, If I ₄ > I ₅ , the following equation is obtained.

I ₅ = I ₃ (6) When I ₄ <I ₅ , the following equation is obtained by applying Kirchhoff's law.

I ₅ = I ₄ ... (7) By referring to the above equations, the output current I corresponding to the change in the input level of the control voltage V _C is obtained. A state of ₀ can be derived. FIG. 2A shows an operation waveform diagram of the currents I ₁ , I ₂ , I ₃ and I ₄ with respect to the control voltage V _C , and FIG. 2B shows the control voltage V _C. for _C, operation waveform diagram of a current I ₅ is shown, and FIG. (c)
The, the control voltage V _C with respect to the control voltage V _C, the operation waveform diagram of the reference voltage V _R and the output current I ₀ is shown.

[0027] In FIG. 1, below the level state of the level reference voltage V _R of the control voltage V _C, namely, in the state of V _C ≦ V _R, the equation (1) from I _1> and I _0/2 Therefore, from the equation (4), I ₁ > I _{2. Since} this state corresponds to the case of I ₄ <I ₅ from the equation (3), the equations (5) and (7) are used. As a result, I ₀ = 0, and the output current at the output terminal 21 is turned off.

The level of the control voltage V _C is equal to the reference voltage V
_{In a} level state exceeding the level of _R , that is, in a state of V _C > VR, since I ₁ <I _0/2 from the above equation (1), I ₁ <I ₂ from the equation (4). Also, (3)
According to the equation, since it corresponds to the case of I ₄ > I ₅ , I ₀ = I _{6 is obtained} by the equations (5) and (6), and the output terminal 21
Output current I ₀ in the a state is ON. The output current I _{0 at} that time is expressed by the following equation.

Here, the value of 2I / k is (V _C -V
The current value I of the constant current source 12 and the value of the constant k are set so as to be sufficiently larger than the value of _R ). That is, the value of k is set to be sufficiently smaller than the value of the constant current value I. Specifically, the transistor size of the NMOS transistors 10 and 11 forming the differential amplifier pair 7 is set to a sufficiently small value with respect to the current value I of the constant current source 12. That is, by increasing the value of the gate length L of the NMOS transistors 10 and 11 and setting the value of the gate width W to a small value, the above equation (8) is approximated as the following equation.

I ₀ = (V _C −V _R ) · (2Ik) ^1/2 (9) According to the above equation (9), the output current I ₀ is equal to the control voltage V _C.
Therefore, in the operating state where the NMOS transistor 18 is turned on and the output current I ₀ is output via the output terminal 21, the output current I ₀ is controlled by the control voltage in response to an input change of V _C is output linearly changes to.

Next, a second embodiment of the present invention will be described. FIG. 3A is a circuit diagram showing the embodiment. As shown in FIG. 3A, this embodiment has basically the same circuit configuration as that of the first embodiment, but has a structure in which a gate of a pair of NMOS transistors forming a differential amplifier pair is provided. reference voltage V _R and the control voltage V applied Te
_A circuit is configured such that _C is applied alternately to the gates of the pair of NMOS transistors.
That is, in FIG. 3A, the NMOS transistor 2
The control voltage V _C is applied to the gate of the transistor 7 by the control voltage source 46, and the reference voltage V _R is applied to the gate of the NMOS transistor 28 by the reference voltage source 47. By exchanging the gate inputs of the NMOS transistors forming such a differential amplifier pair, as shown in the operation waveform diagram of FIG. 3B, in the present embodiment, the control voltage V
Reversed the change of the output current I ₀ to _{the C} input, in the coverage level of the control voltage V _C is V _C ≦ V _R,
The NMOS transistor 36 is ON and the output terminal 3
8, the output current I ₀ is output to the outside. Then, the current value gradually decreases as the control voltage V _C increases, becomes 0 at the reference voltage V _R , and the output current I ₀ becomes O in the range of V _C > V _R.
FF state, and the output current I through the output terminal 38
₀ is never output to the outside.

That is, in this embodiment, the control voltage V
Within the scope _C level is V _C ≦ V _R, the output current I _0, it is possible to control so as to change linearly with respect to the control voltage V _C, the range of V _C> V _R Can function as a switch for stopping the output of the output current I ₀ . The contents of the operation are the same as those in the first embodiment.
In order to avoid duplication of the description, the description is omitted.

Next, a third embodiment of the present invention will be described. FIG. 4A is a circuit diagram showing the embodiment. As shown in FIG. 4A, in the present embodiment, the PMOS transistors 40 and 41 forming the current mirror circuit and the PM transistors forming the current mirror circuit are the same.
OS transistors 42 and 43; NMOS transistors 44 and 45 forming a differential amplification pair;
The gates of the transistors 44 and 45, reference voltage source 46 for applying a reference voltage V _R and the control voltage V _C, respectively
And a control voltage source 47, a constant current source (current I) 48 connected between the sources of the NMOS transistors 44 and 45 and the ground, and an NM forming a current mirror circuit.
The circuit configuration including the OS transistors 49 and 50 is exactly the same as the circuit configuration in the first embodiment. This embodiment is different from the first embodiment in that the current mirror circuit 16 of the output stage, which is arranged on the low potential side in the first embodiment, is shifted to the high potential side, and is shifted to the high potential side. As shown in FIG. 4, PMOS transistors 51 and 52 are replaced by moving the placed capacitor 19 to the lower potential side and replacing the MOS transistors forming the current mirror circuit of the output stage with NMOS transistors from PMOS transistors. It is formed by.

In FIG. 4A, when the level of the control voltage V _C is in the level range of V _C > V _R , I ₄ > I ₅ as described in the first embodiment, and Thereby, PMOS transistors 51 and 52
Are not supplied with a current to the current mirror circuit formed by the PMOS transistor 52. Therefore, the operation state is such that no output current is output from the PMOS transistor 52 to the outside via the output terminal 55. Conversely, the level of the control voltage V _C, when in the level range of V _c ≦ V _R, the first
As in the embodiment, I ₄ in FIG. 4 (a) <
I _5, and the thereby, the current mirror circuit formed by PMOS transistors 51 and 52 described above, an operating state in which current is supplied I ₅ over I ₄ (= I _0). Thus, the output current I ₀ is output from the output terminal 55 from the PMOS transistor 52 to the outside. This operation state is a Tori shown in the operation waveform diagram of FIG. 3 (b), in this embodiment, as in the second embodiment, the output to the input of the control voltage V _C current I ₀ changes in the reverse rotation, in the coverage level of the control voltage V _C is V _C ≦ V _R, NMOS transistor 52 is turned oN, through the output terminal 55, the output current I ₀ is output to the outside State. Then, the current value gradually decreases as the control voltage V _C increases, becomes 0 at the reference voltage V _R , and in a range of V _C > V _R , the output current I ₀ is in an OFF state. As a result, the output current I ₀ is not output to the outside via the output terminal 38.

Next, a fourth embodiment of the present invention will be described. FIG. 5A is a circuit diagram showing the embodiment. As shown in FIG. 5A, in the present embodiment, PMOS transistors 57 and 58 forming a current mirror circuit, a constant current source (current I) 59, and a PMOS transistor 60 forming a differential amplification pair 61 and PM
A reference voltage source 62 and a control voltage source 63 for applying a reference voltage V _R and a control voltage V _C to gates of the OS transistors 60 and 61, NMOS transistors 64 and 65 forming a current mirror circuit, and a current mirror circuit NMOS transistor 6 constituting
6 and 67, PMOS transistors 68 and 70 similarly forming a current mirror circuit, a capacitor 69,
The power supply terminal 71, the output terminal 72 and the ground terminal 73 are provided.

As is apparent from comparison with FIG. 4A, the present embodiment is different from the third embodiment in that a pair of current mirrors arranged on the high potential side in the third embodiment is different from the third embodiment. The circuit is shifted to the low potential side, and the current mirror circuit and the constant current source arranged on the low potential side are shifted to the high potential side, and these current mirror circuits and the MOS transistors forming the differential amplifier pair are: N
That is, the MOS transistor and the PMOS transistor are formed by replacing each other.

In FIG. 5A, PMOS transistors 57 and 58 forming a current mirror circuit, a constant current source 59, PMOS transistors 60 and 61 forming a differential amplifier pair, a reference voltage source 62 and a control voltage source 6
3. NMOS transistors 64 and 65 forming a current mirror circuit, and NMOS transistors 66 and 6
The operation of the circuit including 7 and the like is the same as in the first, second, and third embodiments. Therefore, the operation of the present embodiment is exactly the same as that of the third embodiment in which the current mirror circuits formed by the PMOS transistors 68 and 70 are arranged equivalently, and the level of the control voltage V _C is V _c > V _In the range of _R , the PMO
No current is supplied to the current mirror circuit formed by the S transistors 68 and 70, and therefore no output current is output from the PMOS transistor 70 to the outside via the output terminal 72. Also, the control voltage V
_C level is when in the level range of V _c ≦ V _R, a current is supplied to the current mirror circuit formed by the PMOS transistors 68 and 70, an output terminal 7
2, the output current I ₀ is output from the PMOS transistor 70.
Is output to the outside. This operation state is as shown in the operation waveform diagram of FIG. 4B, and as in the second embodiment, the output current I _{0 with} respect to the input of the control voltage V _C.
Reversed the change of the level of the control voltage V _C is V _C ≦ V _R
, The NMOS transistor 70 is
N, and the output current I ₀ is output to the outside via the output terminal 72. Then, the current value gradually decreases as the control voltage V _C increases, becomes 0 at the reference voltage V _R , and in the range of V _C > V _R , the output current I ₀
Is in the OFF state, and the output current I ₀ is not output to the outside via the output terminal 72.

Next, a fifth embodiment of the present invention will be described. FIG. 6A is a circuit diagram showing the embodiment. As shown in FIG. 6A, in the present embodiment, PNP transistors 74 and 75 forming a current mirror circuit, and PNP transistors
Transistors 76 and 77, NPN transistors 78 and 79 forming a differential amplifier pair, and bases of NPN transistors 78 and 79 are respectively provided with reference voltage V _R.
And a control voltage source 81 for applying a control voltage V _C , a constant current source (current I) 82, and NPN transistors 83 and 8 forming a current mirror circuit.
4, capacitance 85, and NP constituting a current mirror circuit
It comprises N transistors 86 and 87, a power supply terminal 88, an output terminal 89, and a ground terminal 90.

This embodiment is a circuit in which all the MOS transistors in the above-described first embodiment are replaced by bipolar transistors.
The operation is the same as that of the first embodiment, and a description thereof will be omitted to avoid duplication. Thus, M
It goes without saying that configuring another embodiment by replacing the OS transistor with a bipolar transistor is also applicable to the second, third and fourth embodiments.

[0040] Note that the operation state in the present embodiment is a Tori shown in operation waveform diagram of FIG. 6 (b), as in the first embodiment, the level of the control voltage V _C is V _C
≦ V NPN transistor 87 is in the _R in which range becomes OFF, no output current I ₀ through the output terminal 89 is output to the outside. When the level of the control voltage V _C is in the range of V _C > V _R , the NPN transistor 87 is turned on, and the output current I ₀ is output via the output terminal 89.
Is output to the outside. Then, the current value is an operating state where the control voltage V _C is slide into increased accompanied not linearly to increase.

Next, a sixth embodiment of the present invention will be described. FIG. 7A is a circuit diagram showing the embodiment. As shown in FIG. 7A, this embodiment is different from the first embodiment shown in FIG. 1 in that the source sides of the NMOS transistors 95 and 96 forming a differential amplification pair are evident. And resistors 99 and 100, respectively.
Are connected, and a constant current source 101 is inserted and connected between a common connection point of the resistors 99 and 100 and a ground point. For a circuit configuration other than this difference, FIG.
Is exactly the same as in the first embodiment.

In FIG. 7A, the operation of this embodiment is completely the same as the operation of the first embodiment.
The description is omitted to avoid duplication,
The only difference in the operation function is that by appropriately setting the resistance values of the resistors 99 and 100 individually connected to the sources of the NMOS transistors 95 and 96 forming the differential amplification pair, The insertion corrects the gain of the differential amplifier pair, and the current I ₁ corresponding to the difference voltage (V _C -V _R ) between the control voltage V _C and the reference voltage V _R.
And a current variation of the current I ₂ is corrected, with respect to the output current I ₀ which is output from the output terminal 108 to the outside, it is that the level range of linear control possible control voltage V _C is increased. That is, the gain of the differential amplifier pair is corrected by the insertion of the resistor, and the value of the difference voltage (V _C -V _R ) is compressed to a smaller value.
This is because the degree of appropriateness of the approximation condition when deriving the equation is increased.

The operation state in the present embodiment is shown in FIG.
As shown in the operation waveform diagram of (b), as in the case of the first embodiment, the level of the control voltage V _C is V _C ≦.
NMOS transistors in the range is V _R 106
Is turned off, and the output current I ₀ is output via the output terminal 108.
Is not output to the outside. Further, when the level of the control voltage V _C is in the range of V _C > V _R , the NPN transistor 106 is turned on, and the output current I ₀ is output to the outside via the output terminal 108. And the current value is
As the control voltage V _C increases, the control voltage V _C increases according to the current output characteristic having a higher degree of linear approximation.

[0044]

As described above, according to the present invention, in response to an input change of the control voltage, the output current is turned ON / OF with the reference voltage level point at the control voltage level as a boundary.
F, and in a state where the output current is ON, in conjunction with the current switch function, a current control is performed such that an output current whose current value is linearly controlled is output in response to a control voltage input. There is an effect that can be.

The reason for this is that the output current characteristic corresponding to the input voltage of the differential amplifier pair and the function of receiving the input of the output current of the differential amplifier pair and outputting an equivalent current are output. In addition to operating as a current switch by combining with a current mirror circuit acting as a current mirror circuit, linear control of an output current by a control voltage is enabled.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram in the first embodiment.

FIG. 3 is a diagram showing a second embodiment and operation waveforms of the present invention.

FIG. 4 is a diagram showing a third embodiment and operation waveforms of the present invention.

FIG. 5 is a diagram showing a fourth embodiment and operation waveforms of the present invention.

FIG. 6 is a diagram showing a fifth embodiment and operation waveforms of the present invention.

FIG. 7 is a diagram showing a sixth embodiment and operation waveforms of the present invention.

FIG. 8 is a circuit diagram and an operation waveform diagram showing a conventional example.

[Explanation of symbols]

1, 4, 13, 16 Current mirror circuit 2, 3, 5, 6, 23 to 26, 40 to 43, 51, 5
2, 57, 58, 60, 61, 68, 70, 91-9
4, 110, 111, 117 PMOS transistor 7 Differential amplification pair 8, 9, 14, 15, 17, 18, 27, 28, 32,
33, 35, 36, 44, 45, 49, 50, 64 to 6
7, 95, 96, 102, 103, 105, 106, 1
12, 113, 118, 122 to 124 NMOS transistor 10, 30, 46, 62, 80, 97, 115 Reference voltage source 11, 29, 47, 63, 81, 98, 114 Control voltage source 119 Constant voltage source 12, 31 , 48, 59, 82, 101, 116, 12
1 Constant current source 19, 34, 53, 69, 85, 104 Capacity 20, 37, 54, 71, 88, 107, 125 Power supply terminal 21, 38, 55, 72, 89, 108, 126 Output terminal 22, 39, 56, 73, 90, 109, 127 Ground terminal 74-77 PNP transistor 78, 79, 83, 84, 86, 87 NPN transistor 120 Inverter

Claims (8)

(57) [Claims] A first source connected to the high-potential power supply, a first gate connected to the high-potential power supply, and one gate connected to the drain to form a first current mirror circuit; A second PMOS transistor and a source whose sources are individually connected to the high-potential power supply, both gates are interconnected, and one gate is connected to the drain to form a second current mirror circuit. Third and fourth PMOS transistors, and the second and third PMOS transistors having a gate connected to the drain.
The drains of the MOS transistors are individually connected to each other, a predetermined reference voltage and a control voltage are individually applied to the gate, and the sources are commonly connected to form a first and a second pair of differential amplifiers. Second
An NMOS transistor, a constant current source connected between a common connection point of sources of the first and second NMOS transistors and a low potential power supply, and a drain of the first and fourth PMOS transistors. A third and a fourth NMOS transistor each having a drain and a gate individually connected and both gates interconnected, and a source commonly connected to the low potential power supply to form a third current mirror circuit; A capacitance connected between the high-potential power supply and the drain of the fourth PMOS transistor, and a drain connected to a drain and a current output terminal of the corresponding fourth PMOS transistor, respectively, A gate is interconnected and a source is connected to the low potential power supply to form a fourth current mirror circuit. A fifth and sixth NMOS transistor to be formed, wherein the second and third PMOS transistors and the third and fifth NMOS transistors are both configured such that their drain and gate are connected. A voltage controlled current switch circuit characterized by the above-mentioned. 2. A first and a second source, each having a source connected to a high-potential power supply, two gates being interconnected, and one gate being connected to a drain to form a first current mirror circuit. A second PMOS transistor and a source whose sources are individually connected to the high-potential power supply, both gates are interconnected, and one gate is connected to the drain to form a second current mirror circuit. Third and fourth PMOS transistors, and the second and third PMOS transistors having a gate connected to the drain.
The drains of the MOS transistors are individually connected to each other, the control voltage and a predetermined reference voltage are individually applied to the gates, and the sources are commonly connected to form the first and second differential amplifier pairs. Second
An NMOS transistor, a constant current source connected between a common connection point of sources of the first and second NMOS transistors and a low potential power supply, and a drain of the first and fourth PMOS transistors. A third and a fourth NMOS transistor each having a drain and a gate individually connected and both gates interconnected, and a source commonly connected to the low potential power supply to form a third current mirror circuit; A capacitance connected between the high-potential power supply and the drain of the fourth PMOS transistor, and a drain connected to a drain and a current output terminal of the corresponding fourth PMOS transistor, respectively, A gate is interconnected and a source is connected to the low potential power supply to form a fourth current mirror circuit. A fifth and sixth NMOS transistor to be formed, wherein the second and third PMOS transistors and the third and fifth NMOS transistors are both configured such that their drain and gate are connected. A voltage controlled current switch circuit characterized by the above-mentioned. 3. A first and a second current mirror circuit, wherein the sources are individually connected to the high potential power supply, both gates are interconnected, and one gate is connected to the drain to form a first current mirror circuit. A second PMOS transistor and a source whose sources are individually connected to the high-potential power supply, both gates are interconnected, and one gate is connected to the drain to form a second current mirror circuit. Third and fourth PMOS transistors, and the second and third PMOS transistors having a gate connected to the drain.
The drains of the MOS transistors are individually connected to each other, a predetermined reference voltage and a control voltage are individually applied to the gate, and the sources are commonly connected to form a first and a second pair of differential amplifiers. Second
An NMOS transistor, a constant current source connected between a common connection point of sources of the first and second NMOS transistors and a low potential power supply, and a drain of the first and fourth PMOS transistors. A third and a fourth NMOS transistor each having a drain and a gate individually connected and both gates interconnected, and a source commonly connected to the low potential power supply to form a third current mirror circuit; Sources are individually connected to the high potential power supply, both gates are interconnected, and the fourth
Fifth and sixth PMOS transistors each having a drain individually connected to a drain and a current output terminal of the PMOS transistor to form a fourth current mirror circuit.
An S transistor; and a capacitor connected between the drain of the fifth PMOS transistor and the ground potential. The second, third, and fifth PMOs
A voltage controlled current switch circuit, wherein the S transistor and the third NMOS transistor are both configured such that a drain and a gate are connected. 4. When connecting a common connection point between the sources of the first and second NMOS transistors forming the differential amplification pair and the constant current source, the first and second NMOS transistors are connected to each other. 4. The voltage controlled current switch circuit according to claim 1, wherein a predetermined resistor is inserted and connected between the source of the NMOS transistor and the common connection point. 5. A first and a second source, each of which is individually connected to a high-potential power supply, both gates are connected to each other, and one gate is connected to a drain to form a first current mirror circuit. A second PMOS transistor and a source are both connected to the high potential power supply via a predetermined constant current source, and a predetermined reference voltage and a control voltage are individually applied to a gate to form a differential amplification pair. A third PMOS transistor and a fourth PMOS transistor, the drains of which are individually connected to the drain of the corresponding first PMOS transistor and the drain of the third PMOS transistor, the gates are interconnected, and the source is Are connected to the low potential power supply to form a second current mirror circuit. A drain is connected to a drain of the corresponding fourth PMOS transistor and a drain of the second PMOS transistor, respectively; a gate is interconnected; and a source is connected to the low potential power supply. The third and fourth NMOS transistors forming the third current mirror circuit are connected to the high-potential power supply, and the sources are individually connected to each other.
Fifth and sixth PMOS transistors each having a drain individually connected to a drain and a current output terminal of the PMOS transistor to form a fourth current mirror circuit.
An S transistor; and a capacitor connected between a drain of the fifth PMOS transistor and the ground potential; the first and fifth PMOS transistors; and the second and third NMOS transistors. A voltage-controlled current switch circuit, wherein each of the transistors has a drain and a gate connected to each other. 6. When connecting a common connection point between the sources of the third and fourth PMOS transistors forming the differential amplifier pair and the constant current source, the third and fourth PMOS transistors are connected to each other. 6. The voltage controlled current switch circuit according to claim 5, wherein a predetermined resistor is inserted and connected between the source of the PMOS transistor and the common connection point. 7. The first and second emitters are individually connected to a high potential power supply, both bases are interconnected, and one base is connected to a collector to form a first current mirror circuit. A second PNP transistor and an emitter are individually connected to the high potential power supply, both bases are interconnected, and one base is connected to the collector to form a second current mirror circuit. Third and fourth PNP transistors, and the second and third PNP transistors having a base connected to the collector.
The collectors of the NP transistors are individually connected to each other, a predetermined reference voltage and a control voltage are individually applied to the base, and the emitters are commonly connected to form a first and second differential amplifier pair. Second
An NPN transistor, a constant current source connected between a common connection point of the emitters of the first and second NPN transistors and a low potential power supply, and a collector of the first and fourth PNP transistors. Third and fourth NPN transistors, each having a collector individually connected and both bases interconnected, and an emitter commonly connected to the low potential power supply to form a third current mirror circuit; A capacitor connected between a potential power supply and a collector of the fourth PNP transistor, and a collector connected individually to a collector and a current output terminal of the corresponding fourth PNP transistor, and a gate connected Interconnected with each other, and an emitter commonly connected to the low potential power supply to form a fourth current mirror circuit. 5th and 6th NPN transistors, wherein the second and third PNP transistors and the third and fifth NPN transistors are both formed by connecting a collector and an emitter. Voltage controlled current switch circuit. 8. When connecting the common connection point between the emitters of the first and second NPN transistors forming the differential amplification pair and the constant current source, the first and second NPN transistors are connected to each other. 8. The voltage controlled current switch circuit according to claim 7, wherein a predetermined resistor is inserted and connected between the emitter of the NPN transistor and the common connection point.