JP3011235B2 - Binary signal multiplexing device with code conversion function and binary signal separation device with code conversion function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system using time division multiplexing, and more particularly to a multiplexing / demultiplexing apparatus having an encoding function for duobinary modulation and demodulation.

[0002]

2. Description of the Related Art Recently, in a high-speed optical fiber communication system, a system combining optical duobinary modulation and direct detection reception has been proposed as a communication system which is hardly affected by chromatic dispersion of an optical fiber serving as a transmission line.
No. 1 discloses this. This system will be described with reference to FIG.

In FIG. 7, a binary input data signal 10
Is converted into a ternary duobinary signal by the duobinary encoding circuit 11. In the duobinary encoding circuit 11, first, code conversion is performed by a precoder 12 composed of an exclusive-OR circuit (EX-OR) 1 and a one-bit delay unit (ie, one time slot delay unit) 2, and then another one is performed. 2 composed of one 1-bit delay unit 2 and an adder (ADD) 13
A ternary duobinary signal is generated by the ternary ternary conversion circuit 14.

[0004] The ternary duobinary signal is split into a first signal and a second signal in a modulator 37. The branched first signal is supplied to an amplitude adjustment circuit 15 and a bias adjustment circuit 16.
And applied to the first terminal of the optical modulator 17. The branched second signal passes through an inverting circuit (INV) 18 and another amplitude adjusting circuit 15 and is applied to a second terminal of the optical modulator 17. An optical modulator 17 is a Mach-Zehnder type optical intensity modulator, which applies the first and second signals to two optical waveguides to modulate light from a laser diode (light source) 19 to generate an optical duobinary signal. .

At this time, the amplitude of the above two signals is applied as a half-wavelength voltage of the optical modulator 17 and the bias is adjusted to adjust the three levels of the duobinary signal (“0”, “3” of the ternary signal).
"1" of the value signal and "2" of the ternary signal) 21, 22,
And 23 are assigned to the transmission characteristics 24 of the modulator as shown in FIG. As a result, the three levels of the electric signal are assigned to the three states of light, and the spectrum of the modulated light is narrowed.

In the receiver, the intensity of the modulated light, that is, FIG.
(“0” of the detection signal and “1” of the detection signal) 25 and 26 are detected and converted into an electric signal.

In this transmission system, a ternary optical duobinary signal is detected only by intensity, so that a code sequence changes between a transmitter and a receiver. To compensate for this change, transcoding at the transmitter or receiver is required.

FIG. 9 shows a system in which a precoder 12 for code conversion is arranged on the transmitter side in a system having an optical duobinary transmitter and a direct detection receiver. In addition, in all of the following expressions, "/" indicates an exclusive OR (EX-OR) operator for convenience of expression description.

In FIG. 9, an input signal a (i) is converted by a precoder 12 into a signal b (i) represented by the following equation.

B (i) = a (i) · b (i-1) (1) Here, i in the equation indicates the time slot number of the signal.

When b (i) is passed through a binary / ternary conversion circuit 14, it is converted into a duobinary signal c (i) represented by the following equation.

C (i) = b (i) + b (i−1) = a (i) · b (i−1) + b (i−1) (2) Here, INV in all the following equations [] Indicates a logical inversion operation for convenience of description of an expression.

When c (i) is passed through an optical transmission section 30 composed of an optical modulator and a direct detector, an output signal d (i) represented by the following equation is obtained.

D (i) = INV [| c (i) −1 |] = INV [| a (i) · b (i−1) + b (i−1) −1 |] (3) || in the equation represents an absolute value operation. Here, FIG.
According to the table shown in FIG. 0, since INV [A + B-1] = AB (AB) B = A, equation (3) is transformed as follows, and a correct code can be obtained in the receiver. I understand.

D (i) = {a (i) · b (i−1)} · b (i−1) = a (i) (3 ′) As shown in FIG. 11, the precoder 12 is connected to the receiver. , The code can be transmitted correctly. In this configuration, the output signal e (i) is given by the following equation for the input signal a (i).

E (i) = d (i) · e (i−1) = INV [| a (i) + a (i−1) −1 |] · e (i−1) = ｛a (i) · A (i-1)｝ · e (i-1) (3 ') Here, if A = BC, if A · C = B is used, equation (4) becomes Is converted to

E (i) · e (i−1) = a (i) · a (i−1) (4 ′) From equation (4 ′), e (i) and a (i) are the same signal. Yes, it can be seen that signals can be received correctly.

In high-speed optical fiber communication, a low-speed signal is time-division multiplexed to generate a high-speed signal, which is then transmitted using light, and time-division-separated in a receiver to reproduce the low-speed signal. When the optical duobinary system is applied to such a system, conventionally, code conversion is performed by the precoder 12 after data multiplexing in the transmitter of FIG. 9 or separation is performed after code conversion by the deprecoder 12 in the receiver of FIG. .

That is, when the precoder 12 is placed on the transmitter side as shown in FIG. 9, N low-speed signals s _k (i) are multiplexed bit by bit at the preceding stage of the precoder 12, and the high-speed signal a ( get i).

A (N × i + k) = s _k (i) (5) where k is a subscript for identifying low-speed signals. Thereafter, the signal is converted by the precoder 12 to obtain a signal b '(i) shown in the following equation.

B ′ (N × i + k) = a (N × i + k) · b ′ (N × i + k−1) = s _k (i) · b ′ (N × i + k−1 (6) On the other hand, when the precoder 12 is placed on the receiver side as shown in FIG. 11, after the signal d (i) is encoded by the precoder 12 to generate the signal e (i), the signal e (i) is To perform time-division separation to obtain an output low-speed signal u _k (i) represented by the following equation.

U _k (i) = e (N × i + k) = d (N × i + k) · e (N × i + k−1) = d (N × i + 1) · u _N ( i-1), d (N × i + k) · uk _-1 (i) (k = 2,..., N) (7)

[0023]

In the duo-binary modulation system, when the bit rate of a signal to be transmitted increases, an extremely high-speed operation is required for an exclusive OR circuit used in an encoder or a decoder. However, the operating speed of the exclusive OR circuit is currently limited to about 10 Gb / s, and it is difficult to process data at a higher speed.

Further, a delay circuit for one bit length is required in the encoder and the decoder, but a transmission line is usually used for this. However, when the bit rate increases, the element length is shortened in order to shorten the delay time, and the accuracy of the element length is also strict.

That is, there is a problem that the characteristics of the elements used in the signal encoding circuit prevent the transmission speed of the system from increasing.

Therefore, an object of the present invention is to provide an encoding function which is not restricted by the operating speed of the exclusive OR circuit, the length and the precision of the delay element by performing encoding at the stage of a low-speed signal before time-division multiplexing. A multiplexing device provided with

Another object of the present invention is to provide an encoding function which is not restricted by the operating speed of the exclusive OR circuit, the length and the precision of the delay element by encoding the signal after the time division separation. To provide a separation device.

[0028]

According to a first aspect of the present invention, a binary signal having a code conversion function, supplied with first and second binary signals having mutually equal bit rates. A multiplexing device, comprising: first and second exclusive OR circuits each having first and second input terminal means and one output terminal means; one multiplexing circuit; A delay unit that delays by the number of bits, wherein the first input terminal means of the first and second exclusive OR circuits are supplied with the first and second binary signals, respectively, The second input terminal means of the second exclusive OR circuit comprises the first exclusive OR circuit.
And the second input terminal means of the first exclusive-OR circuit is connected to the output terminal means of the second exclusive-OR circuit via the one-bit delay unit. Connected to output terminal means, the multiplexing circuit is connected to the output terminal means of the first and second exclusive OR circuits, and outputs the bit signals of the first and second exclusive OR circuits. A binary signal multiplexing device having a code conversion function characterized in that the signal is time-division multiplexed for each signal.

According to a second aspect of the invention, a code is supplied with first, second,... And Nth (N is an integer greater than 2) binary signals having mutually equal bit rates. A first, second,..., And N-th exclusive-OR circuit each having first and second input terminal means and one output terminal means And a delay unit for delaying the binary signal by one bit, and the first input of the first, second,..., And Nth exclusive OR circuits The terminal means is supplied with the first, the second,..., And the N-th binary signal, respectively, and is connected to the n-th (n: n) of the second,. The second input terminal means of the exclusive-OR circuit of the second exclusive-OR circuit and the Nth exclusive-OR circuit (variable between both) includes the (n-1) th exclusive-OR circuit And the second input terminal means of the first exclusive OR circuit is connected to the output terminal means of the Nth exclusive OR circuit via the one-bit delay device. , And the multiplexing circuit is connected to the output terminal means of the first, second,..., And N-th exclusive OR circuits, and the first, second,. Wherein the output signal of the exclusive OR circuit is time-division multiplexed bit by bit, and a binary signal multiplexing device having a code conversion function is obtained.

According to the third aspect of the present invention, the input binary signal is converted into first and second binary signals having mutually equal bit rates.
One separation circuit for time division separation into value signals,
A first and a second exclusive OR circuit having first and second input terminal means and one output terminal means;
A delay unit that delays by the number of bits, wherein the first input terminal means of the first and second exclusive OR circuits are supplied with the first and second binary signals, respectively, The second input terminal means of a second exclusive OR circuit is connected to the output terminal means of the first exclusive OR circuit, and the second input terminal means of the first exclusive OR circuit Is connected to the output terminal means of the second exclusive OR circuit via the one-bit delay device, and outputs an output signal of the output terminal means of the first and second exclusive OR circuits to a device output. A binary signal separation device having a code conversion function characterized by being output as a signal is obtained.

According to the fourth aspect of the present invention, the input binary signals are converted into first, second,.
And Nth (N is an integer of 3 or more) binary signals in a time-division manner, and a first and a second circuit each having first and second input terminal means and one output terminal means. 2, ...,
, An N-th exclusive-OR circuit, and a delay unit for delaying the binary signal by one bit, wherein the first, second,.
, And the N-th binary signal are supplied to the first input terminal means of the N-th exclusive-OR circuit, respectively, and the second,. The second input terminal means of the n-th exclusive-OR circuit of the N-th exclusive-OR circuit (where n is variable between 2 and N (including both)) may include (n−1) ) Is connected to the output terminal means of the exclusive OR circuit, and the second input terminal means of the first exclusive OR circuit is connected to the Nth exclusive OR circuit via the 1-bit delay unit. The code conversion function is connected to the output terminal means and outputs an output signal of the output terminal means of the first, second,..., And Nth exclusive OR circuits as a device output signal. Is obtained.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a binary signal multiplexing apparatus having an encoding function according to a first embodiment of the present invention. The binary signal multiplexing apparatus includes similar parts indicated by similar reference numerals. It shows that the signal obtained by this configuration is equal to the signal given by equation (6). In FIG. 1, signals s ₁ (i) to s
When _N (i) is supplied to the N exclusive OR circuits 1, exclusive output signals t ₁ of the sum circuit 1 (i) ~t _N (i) is given by the following equation.

T ₁ (i) = s ₁ (i) · t _N (i−1), t _k (i) = s _k (i) · t _k−1 (i) (k = 2,..., N (8) The signal b ″ (i) obtained by multiplexing these t ₁ (i) to t _N (i) by the time division multiplexer 3 is given by the following equation.

B ″ (N × i + 1) = t ₁ (i) = s ₁ (i) · t _N (i−1) = s ₁ (i) · b ″ (N × (i−1 ) + N) = s ₁ (i) · b ″ (N × i), b ″ (N × i + k) = t _k (i) = s _k (i) · t _k−1 (i) = S _k (i) · b ″ (N × i + k−1) (k = 2,..., N) (9) From equations (6) and (9), b ′ (i) and b ′ '(i) indicate the same signal, indicating that the present invention works correctly.

FIG. 2 shows a binary signal separating apparatus having an encoding function according to a second embodiment of the present invention. The present binary signal separation device includes similar parts indicated by similar reference numerals. It shows that the signal obtained by this configuration is equal to u _k (i) in Expression (7) obtained by the conventional technique. In FIG.
N low-speed signals v _k (i) obtained by time-division separating the input signal d (i) by the time-division separator 4 are given by the following equations.

V _k (i) = d (N × i + k) (10) When v _k (i) is supplied to N exclusive OR circuits 1, the output signal u ′ _k ( i) is given by the following equation.

U ′ ₁ (i) = v ₁ (i) · u ′ _N (i−1) = d (N × i + 1) · u ′ _N (i−1), u ′ _k (i) = v _k (i) · u ′ _k−1 (i) = d (N × i + k) · u ′ _k−1 (i) (k = 2,..., N) (11) Equation (7) and ( From equation (11), it can be seen that u _k (i) and u ′ _k (i) are the same signal, and the present invention works correctly.

FIG. 3 shows an optical duobinary transmission / reception system with a transmission rate of 20 Gbps provided in a transmitter using a binary signal multiplexing apparatus having an encoding function according to a third embodiment of the present invention. The two 10 Gbps signals 31 are input to the first input terminals of the first and second exclusive OR circuits 34, respectively. Each of the exclusive OR circuits 34 has 10 Gbps
GaAs-IC (NEC I)
C, NLG4103). The output of the first exclusive OR circuit 34 is branched, one of which is connected to the first input terminal of the 2: 1 multiplexing circuit 35 and the other is connected to the second exclusive OR circuit 34.
Is input to the second input terminal. The output of the second exclusive OR circuit 34 is also branched, one of which is connected to the second input terminal of the 2: 1 multiplexing circuit 35 and the other of which is the one-bit delay unit 3.
After passing through No. 3, the signal is input to the second input terminal of the first exclusive OR circuit 34. The delay amount of the 1-bit delay unit 33 is 1
00p (pico) s.

The 2: 1 multiplexing circuit 35 converts the 20 Gbps signal into a duobinary signal by a 5 GHz band low-pass filter 36 corresponding to a binary / ternary conversion circuit. The duobinary signal is input to the optical modulator 37 to modulate light having a wavelength of 1.55 μm from the laser diode 38. The optical modulator 37 is the optical modulator 37 of FIG.
Similarly, it is composed of a Mach-Zehnder modulator 17 using lithium niobate, an inverting circuit 18, an amplitude adjusting circuit 15, and a bias adjusting circuit 16, and converts a ternary signal of light 3 shown in FIG.
Assigned to state. The modulated light is detected by the direct detection light receiver 39 as a signal “0” when light is emitted and a signal “1” when light is quenched. The detection signal is a 1: 2 separation circuit 4
0 separates into two 10 Gbps signals 41 and 42,
Reproduce.

The one-to-two data separation circuit 40 is also a SiGe-
It is an IC using an HBT and has an ability to process a 20 Gbps signal.

As a result of generating an optical duobinary signal by the configuration of the present embodiment, it was confirmed that an optical spectrum width of 10 GHz was obtained at the output of the optical transmitting section, and the optical duobinary signal was obtained. Here, when the code error rates of the output signals 41 and 42 of the 1: 2 separation circuit 40 were measured using a pseudo random code, it was confirmed that code transmission was performed without error.

From the above, it has been found that the present invention correctly operates as an encoding circuit for duobinary optical transmission.
By the way, in the above description, it is limited that the photodetector detects "0" at the time of light emission and "1" at the time of light extinction. On the other hand, when using a receiver whose logical assignment is reversed, one of the first input, the second input, and the output of each of the exclusive OR circuits 34 may be logically inverted.
This will be described.

When the logical assignment of the optical receiver is "1" when light is emitted and "0" when light is extinguished, the logic of the detection signals 41 and 42 is inverted. Therefore, if a logical inversion circuit is provided before the first input terminal of the exclusive OR circuit 34 to invert the input signals 31 and 32 in advance, a correct code can be obtained at the output of the receiver.

The exclusive OR operator is given by INV [A] · B =
It has the characteristic of A INV [B]. Therefore, if the second input of the exclusive OR circuit 34 in FIG. 3 is inverted, the same effect as that obtained by inverting the first input can be obtained, and a correct sign can be obtained.

When the output of the exclusive OR circuit 34 is inverted, a signal obtained by inverting the output when the second input is inverted is input to the 2: 1 multiplexing circuit 35. As a result, the multiplexed signal is also logically inverted and input to the low-pass filter 36 corresponding to a binary-ternary conversion circuit. Then, in the output of the binary / ternary conversion circuit, “0” before inversion becomes “2”, “2” before inversion becomes “0”, and “1” does not change. However, as can be seen from FIG. 8, the switching of “0” and “2” does not change the sign after light detection. Therefore, inverting the output of the exclusive OR circuit 34 is equivalent to inverting the second input, and a correct sign is obtained.

In the present embodiment, the detection logic of the optical receiver was inverted, and the second output of the GaAs-IC was a logically inverted output. It was confirmed that the data was correctly transmitted without a code error between the transmitter and the receiver.

When three or more multi-signals are encoded and multiplexed according to the present invention, the exclusive OR circuit connected to the lower side of FIG. In the case of 1, there is a possibility that the timing of the logical operation is shifted and a correct operation cannot be obtained.

FIG. 4 shows a multiplexer having a code conversion function according to a fourth embodiment of the present invention in which a delay circuit is added to compensate for the propagation delay. In this multiplexer, the second to Nth input signals s _k (i) are
Before inputting to the exclusive OR circuit 53, a delay is given by the delay circuit 51. Since the signal after passing through the (k-1) exclusive OR circuits 53 is input to the second input of the k-th exclusive OR circuit 53, a delay of (k-1) D is given. Use to adjust the signal phase. D is an exclusive OR circuit 53
Is the propagation delay between the input and the output. The delay amount of the one-bit delay unit 50 between the output of the N-th exclusive OR circuit 53 and the second input of the first exclusive OR circuit 53 is (T-ND)
(T is one time slot length), and a one-bit delay is given in consideration of the propagation delay of the circuit. Further, the delay circuits 52 are also provided at the outputs of the first to (N-1) -th exclusive OR circuits 53, and the delay amount of the k-th delay circuit is (N−k).
By setting D, the phases of the N signal inputs to the N: 1 multiplexing circuit could be aligned, and as a result, data multiplexing was correctly performed.

FIG. 5 shows an optical duobinary transmission / reception system in which an optical receiver is provided with a demultiplexer having a code conversion function according to a fifth embodiment of the present invention. This embodiment is also an optical duobinary transmission / reception system having a transmission rate of 20 Gbps as in FIG. 3, but a separating device having a code conversion function is provided on the receiver side. The two 1OGbps signals 31 are input to the 2: 1 multiplexing circuit 35 and multiplexed. 20Gbp after multiplexing
The s signal is converted to a duobinary signal by a low-pass filter 36 having a band of 5 GHz corresponding to a binary / ternary conversion circuit, and then applied to an optical modulator 37, whereupon the laser diode 3
Modulates light at a wavelength of 1.55 microns from 8. After the modulated light is detected by the direct detection light receiver 39 as “0” when light is emitted and “1” when light is extinguished, the 1: 2 separation circuit 40
To separate and reproduce two 10 Gbps signals.

The two signals are input to the first input terminals of the first and second exclusive OR circuits 34, respectively.
The output of the first exclusive OR circuit 34 is branched, and one is inputted to the second input terminal of the second exclusive OR circuit 34 and the other is outputted as the first data 41. Also,
The output of the second exclusive OR circuit 34 is also branched, one of which is 1
After passing through the bit delay unit 33, the first exclusive OR circuit 3
4 is input to a second input terminal, and the other is output as second data 42. The delay amount of the one-bit delay unit 33 is 100 p (pico) s.

According to the configuration of the present embodiment, an optical duobinary signal having an optical spectrum width of 10 GHz at the output of the optical transmitting unit is confirmed, and a code error rate is measured using a pseudo random code. As a result, both signals are correctly transmitted. I confirmed that. Also in this embodiment, when an optical receiver that detects light emission as “1” and light extinction as “0” is used, the first or second input of the two exclusive OR circuits 34 before the first input or the second input is performed. The logical inversion may be performed at any one position before the input or after the output.

FIG. 6 shows a separating apparatus having a code conversion function according to a sixth embodiment of the present invention. This embodiment is a separation apparatus having a code conversion function for handling three or more multi-signals. By providing a delay circuit 51 at the input of the exclusive-OR circuit 53, the exclusive-OR circuit 53 adjusts the phase of two signals. And the delay circuit 52 of the output section provides the N output signals with the same phase.

1: Exclusive OR is applied to the second to N-th data of the data separated into N pieces by the N separation circuit 55 after the delay circuit 51 gives a delay of (k-1) D. Input to the circuit 53. k-th exclusive OR circuit 5
3 is provided with a delay circuit 5 for delaying (N−k) D.
2 to match the phase of the output signal u _k (i). The delay amount of the one-bit delay unit 50 connected between the output of the N-th exclusive OR circuit 53 and the second input of the first exclusive OR circuit 53 is (T-ND) (T is one time slot). A one-bit delay is given as the data length. As a result, a separation device that outputs data with the same phase without the problem of the phase shift at the time of calculation by the exclusive OR circuit 53 is configured.

In the above-described embodiments of FIGS. 3 and 5, the number of input data is set to two, but it is not limited to this, and it is easily understood that a configuration in which three or more data are demultiplexed can be adopted. . Although the data rate is set to 10 Gbps, the data rate is not limited to this as long as the circuit of the system operates.

Further, all processing is described as being performed using electric signals. However, the processing is not limited to electricity, but may be performed as optical signals, or a combination of electric signals and optical signal processing using an electro-optical interface. It may be realized.

Each circuit component is described as an example of the embodiment, and is not limited to them. For example, an exclusive OR operation is performed on an IC other than GaAs, such as an IC using Si, a mechanical switch, a digital signal processor or a programmable logic device, a software operation using a CPU of a computer, or an optical switch such as an optical-optical switch or an optical interferometer. Any circuit that performs an exclusive OR operation, such as a circuit using, may be used. Also,
As the delay circuit, a microstrip line or a coplanar line, which is a normal transmission line, is used.
It is sufficient that a predetermined delay is given while maintaining a certain signal waveform such as a waveguide, an optical fiber, and optical space propagation. The SiGe-IC mentioned as a multiplex circuit is an example,
It can be easily imagined that it can be realized by an IC using aAs or Si, a mechanical switch, or an optical multiplexer using an optical multiplexer. The same applies to the separation circuit, as long as binary multiplexed data can be separated, and a mechanical switch, an electric-one optical switch, an optical-one optical switch, an optical nonlinear loop mirror, or the like can be used.

Although the present invention has been described as being limited to the use in transmitting an optical duobinary signal, the scope of application is not limited to this, and the code may be changed in the same manner after demodulation. Can be applied as is. For example, a duobinary signal is directly allocated to three intensity levels of light, transmitted and detected, and then a detection method is performed, in which the detected electric signal is subjected to non-linear processing to be folded back at a center value to reproduce the signal, or a DPSK modulated light is subjected to delay detection. And so on.

[0059]

According to the present invention, a binary signal multiplexing apparatus and a binary signal demultiplexing apparatus having an encoding function which is not limited by the operation speed of the exclusive OR circuit, the length and the precision of the delay element can be realized. . Further, by performing delay compensation in consideration of the propagation delay time of the exclusive OR, a stable operation could be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multiplexer having a code conversion function according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a separation device having a code conversion function according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a system in which a multiplexing device having a code conversion function is provided in an optical transmitter according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a multiplexer having a code conversion function according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a system in which an optical receiver includes a demultiplexer having a code conversion function according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram of a separation device having a code conversion function according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram of a conventional optical duobinary transmitter.

FIG. 8 is a diagram for explaining code assignment of optical duobinary modulation.

FIG. 9 is a block diagram illustrating an optical duobinary transmission system including an encoder (precoder) on a transmitter side.

FIG. 10 is a logical table showing logical operations used in optical duobinary.

FIG. 11 is a block diagram showing an optical duobinary transmission system including an encoder (precoder) on the receiver side.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Exclusive OR circuit 2 1-bit delay device 3 Time division multiplexer 4 Time division separator 10 Input data signal 11 Duo binary encoding circuit 12 Precoder 13 Adder 14 Binary ternary conversion circuit 15 Amplitude adjustment circuit 16 Bias adjustment circuit Reference Signs List 17 optical modulator 18 inverting circuit 19 laser diode 30 optical transmission unit 33 1-bit delay unit 34 exclusive OR circuit 35 2: 1 multiplexing circuit 36 low-pass filter 37 optical modulator 38 laser diode 39 optical receiver 40 1: 2 separation circuit 50 1-bit delay device 51 (for input phase matching) delay circuit 52 (for output phase matching) delay circuit 53 exclusive OR circuit 54 N: 1 multiplexing circuit 55 1: N separating circuit

Claims (16)

(57) [Claims] 1. A binary signal multiplexing device with code conversion function, supplied with first and second binary signals having mutually equal bit rates, each comprising a first and a second input. First and second exclusive OR circuits having terminal means and one output terminal means (34)
A multiplexing circuit (35); and a delay unit (33) for delaying the binary signal by one bit, and the first input terminal of the first and second exclusive OR circuits. Means are supplied with the first and second binary signals, respectively; the second input terminal means of the second exclusive OR circuit is the output terminal means of the first exclusive OR circuit Wherein the second input terminal means of the first exclusive OR circuit is connected to the output terminal means of the second exclusive OR circuit via the one-bit delay device, Is connected to the output terminal means of the first and second exclusive OR circuits, and time-division multiplexes the output signals of the first and second exclusive OR circuits bit by bit. A binary signal multiplexing apparatus having a code conversion function. 2. The code conversion function according to claim 1, wherein said first input terminal means of each of said first and second exclusive OR circuits comprises a logical inversion circuit. Binary signal multiplexing device provided. 3. The code conversion function according to claim 1, wherein said second input terminal means of each of said first and second exclusive OR circuits comprises a logical inversion circuit. Binary signal multiplexing device provided. 4. The method of claim 1, wherein the first and second bit rates have equal bit rates.
A binary signal multiplexing device provided with a code conversion function, to which a second,..., And N-th (N is an integer of 3 or more) binary signals are supplied, each having a first and a second input terminal , An Nth exclusive OR circuit (1, 53) having a means and one output terminal means, one multiplexing circuit (3), and one bit of the binary signal. Delay device for delaying (2, 50)
, And the first input terminal means of the first, the second,..., And the N-th exclusive-OR circuit comprises the first, the second,
, And the N-th binary signal are supplied, respectively, and the n-th (n is variable between 2 and N (including both)) among the second,. The second input terminal means of the exclusive OR circuit of
1) connected to the output terminal means of the exclusive OR circuit, wherein the second input terminal means of the first exclusive OR circuit is connected to the Nth exclusive OR circuit via the 1-bit delay unit. , And the multiplexing circuit is connected to the output terminal means of the first, second,..., And Nth exclusive OR circuits, and the first, second, , And a time-division multiplexing of the output signal of the N-th exclusive-OR circuit for each bit, and a binary signal multiplexing apparatus having a code conversion function. 5. The first, the second,..., And the N-th
The first input terminal means of each of the exclusive OR circuits of
5. The binary signal multiplexing apparatus having a code conversion function according to claim 4, further comprising a logic inversion circuit. 6. The first, the second,..., And the N-th
The second input terminal means of each of the exclusive OR circuits of
5. The binary signal multiplexing apparatus having a code conversion function according to claim 4, further comprising a logic inversion circuit. 7. The second input terminal means of each of the second,..., And Nth exclusive OR circuits includes an input delay circuit (51), except for the Nth exclusive OR circuit. The output terminal means of all the exclusive OR circuits have output delay circuits (5
5. The input delay circuit and the output delay circuit according to claim 4, wherein the input delay circuit and the output delay circuit have a delay amount determined to compensate for a propagation delay between input and output of the exclusive OR circuit. 6. A binary signal multiplexing device having a code conversion function. 8. The code conversion function according to claim 7, wherein the delay unit has a delay amount determined to provide a one-bit delay in consideration of the propagation delay. Binary signal multiplexer. 9. A separation circuit (40) for time-division separating an input binary signal into first and second binary signals having mutually equal bit rates, and first and second input terminals, respectively. First and second exclusive OR circuits having means and one output terminal means (34)
And a delay unit (33) for delaying the binary signal by one bit, wherein the first input terminal means of the first and second exclusive OR circuits comprises: 2, the second input terminal of the second exclusive-OR circuit is connected to the output terminal of the first exclusive-OR circuit, and the first exclusive-OR circuit is connected to the first exclusive-OR circuit. The second input terminal means of the OR circuit is connected to the output terminal means of the second exclusive OR circuit via the one-bit delay device, and the first and second exclusive OR circuits are provided. A binary signal separation device having a code conversion function, wherein the output signal of the output terminal means is output as a device output signal. 10. The code conversion function according to claim 9, wherein said first input terminal means of each of said first and second exclusive OR circuits comprises a logical inversion circuit. Binary signal separation device provided. 11. The code conversion function according to claim 9, wherein said second input terminal means of each of said first and second exclusive OR circuits comprises a logical inversion circuit. Binary signal separation device provided. 12. A separation circuit for time-division-separating an input binary signal into first, second,..., And N-th (N is an integer of 3 or more) binary signals having equal bit rates. 4,
55), a first, second,..., And N-th exclusive OR circuit (1, 53) each having first and second input terminal means and one output terminal means; Delay device for delaying one bit of signal (2, 50)
, And the first input terminal means of the first, the second,..., And the N-th exclusive-OR circuit comprises the first, the second,
, And the N-th binary signal are supplied, respectively, and the n-th (n is variable between 2 and N (including both)) among the second,. The second input terminal means of the exclusive OR circuit of
1) connected to the output terminal means of the exclusive OR circuit, wherein the second input terminal means of the first exclusive OR circuit is connected to the Nth exclusive OR circuit via the 1-bit delay unit. .., And outputting the output signal of the output terminal means of the first, second,..., And Nth exclusive OR circuits as a device output signal. Binary signal separation device with function. 13. The first input terminal means of each of the first, second,..., And N-th exclusive-OR circuits includes a logical inversion circuit.
A binary signal separation device provided with a code conversion function according to (1). 14. The apparatus according to claim 12, wherein said second input terminal means of each of said first, second,..., And Nth exclusive-OR circuits comprises a logic inversion circuit.
A binary signal separation device provided with a code conversion function according to (1). 15. The second input terminal means of the second,..., And the Nth exclusive OR circuit each include an input delay circuit (51), except for the Nth exclusive OR circuit. The output terminal means of all the exclusive OR circuits have output delay circuits (5
13. The method according to claim 12, wherein the input delay circuit and the output delay circuit have a delay amount determined to compensate for a propagation delay between input and output of the exclusive OR circuit. A binary signal separation device having a code conversion function. 16. The code conversion function according to claim 15, wherein the delay unit (50) has a delay amount determined to provide a one-bit delay in consideration of the propagation delay. Binary signal separation device.