JP3004166B2 - Functional simulation netlist and back annotation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation apparatus and a back annotation method capable of performing a logic simulation in consideration of a variation in delay time due to capacitive coupling between wirings.

[0002]

2. Description of the Related Art In the design of a semiconductor integrated circuit, logic design and layout design are generally performed in a divided manner, and timing information (such as wiring length) finally obtained from a layout is obtained.
Is fed back to the logic simulation to perform logic verification including accurate timing.
This is called back annotation.

[0003] Logic design is to create a logic simulation netlist that describes connection information between logic cell libraries used for logic simulation. The logic cell library is one-to-one with the actual logic cells (eg, inverter, NAND, NOR, etc.) after layout.
Is necessary to execute the logic simulation.
It is composed of a logic expression and information indicating the logic propagation delay time of the logic cell obtained from the layout. In the logic simulation netlist, the connection between the logic cell libraries is called a node connection, and in the layout, the node connection indicates the wiring between the logic cells wired by an automatic placement and routing tool or the like.

In a logic simulation in an early stage of logic design, accurate timing information cannot be obtained because there is no definitive information on layout. The logic simulation at this stage is executed using a virtual wiring delay time assuming a delay due to wiring between logic cells by an empirical method.

Conventionally, in the timing verification after the layout is determined, the actual wiring delay time is calculated using the wiring length of the node connection obtained from the automatic placement and routing tool and the like, and the timing information of the logic simulation netlist is corrected. A logic simulation was being performed. Here, the calculation of the actual wiring delay time is performed independently for each node connection, and the wiring resistance and wiring capacitance of the node connection of interest, the driving capability of the logic cell driving the node connection of interest, and the input side It is calculated using the input capacity of the cell and the like.
Further, regarding the wiring capacitance, in the actual layout, the wirings constituting the node connection are wired at various intersections and adjacent to each other, so that various sizes of coupling capacitance exist between the wirings. These coupling capacitances have been neglected as the coupling capacitances because they are treated as grounding capacitances or the wiring capacitances are simply determined by multiplying the wiring length by the average capacitance per unit wiring length.

[0006]

However, as the miniaturization of semiconductor integrated circuits progresses, the spacing and width of the wirings both decrease, and the ratio of the coupling capacitance between the wirings to the total wiring capacitance increases. However, the influence of the capacitive coupling between the wirings on the delay time of the wirings has become so large that it cannot be ignored. Now, the first wiring of interest is adjacent to the second wiring.
Has a large coupling capacitance with the second wiring, the amount of charge charged to the coupling capacitance changes due to the transition of the potential of the second wiring. That is, the delay time of the first wiring changes due to a change in the logic state of the second wiring (transition of potential). In particular,
Since the bus line-like wirings are adjacent to each other over a long distance, the coupling capacitance is large, and the influence on the delay time is large. In addition, in wirings adjacent to each other, nodes which are irrelevant in design logic may interfere with each other, and when a timing failure due to capacitive coupling occurs, it is difficult to analyze a failure on an actual device. .

The present invention has been made in view of the above, and has as its object to provide a logic simulation apparatus and a back annotation method capable of realizing highly accurate timing verification in a logic simulation. I do.

[0008]

In order to achieve the above-mentioned object, the following has been found as a result of further study on the effect of the capacitive coupling between wirings connecting logic cells on the delay time.

The logic of the signal is defined by the potential of the wiring, and the propagation of the logic is performed by charging and discharging the capacitance of the wiring. That is, the delay time of logic propagation is determined by the speed of charge / discharge of the wiring. Wirings that are physically adjacent to each other and have capacitive coupling between each other have different transient charge amounts of charge to the coupling capacitance depending on the initial state of each logic, the transition direction, and the transition time. Influence the delay time. Also, the variation of the delay time due to this effect can be calculated in advance based on the initial state, the transition direction, and the transition time of the wiring.

The present invention has been made on the basis of the above-described findings. In a logic simulation, it is possible to easily realize a variation in delay time due to capacitive coupling between wirings connecting logic cells. This is to improve the accuracy of the timing verification.

[0011] Specifically, a solution taken by the invention of claim 1 is that a netlist having a logic cell library and a node connection between the logic cell libraries is created by logic design.
Logic simulation equipment using this netlist.
Intended for location, provided at a plurality of nodes connected corresponding to a plurality of wires is present capacitive coupling, selectively delayed by the control input the nodes connected to the logic output of that logical cell library to drive <br/> A plurality of delay time adding means for adding time ;
The delay time provided at one of the plurality of node connections
Is the logical output of the other nodes that logical cell library to drive the connection which the configuration and a Eru Den capacitive coupling virtual connection with the control input to the adding means.

The invention according to claim 2 is, specifically, claim 1
The arrangement of the invention, the delay time adding means includes a table of correction values of the delay time, and the capacitive coupling tentative
Based on the transition direction and transition time of a logic output which is transmitted as said control input by virtual connection, by selecting the correction value of the delay time from the table, adds a configuration for determining a delay time pressure with Things.

[0013] A solution means specifically taken by the invention of claim 3 is directed to a back annotation method for giving a delay time of a real wiring after layout to a logic simulation,
Extracting a capacitance related to the node connection for each node connection from the layout; and, for each node connection corresponding to one wiring having a capacitive coupling between other wirings, the capacitance due to the capacitance coupling. Calculating the strength of the capacitive coupling based on the coupling capacitance, and for each node connection where the strength of the capacitive coupling exceeds a predetermined threshold value, a logic cell library provided at the node connection and driving the node connection A delay time adding means for selectively adding a delay time to a logic output by a control input, and a logic output of a logic cell library driving a node connection corresponding to the other wiring as the control input to the delay time adding means. Adding a capacity-coupled virtual connection to be conveyed to the logic simulation netlist.

More specifically, the invention of claim 4 is directed to a back annotation method for giving a delay time of a real wiring after layout to a logic simulation, and for each node connection in the layout information, an electrostatic capacitance related to the node connection. With respect to the step of extracting the capacitance and the connection of each node corresponding to one wiring having a capacitive coupling between the other wiring, the output impedance (R
d) and the coupling capacitance (C
c) calculating a time constant (Rd × Cc) which is a product of (c) and a capacitance ratio (Cc / Ct) which is a ratio of the coupling capacitance (Cc) to the total capacitance (Ct) of the one wiring. And for each node connection whose time constant (Rd × Cc) exceeds a predetermined first threshold or whose capacitance ratio (Cc / Ct) exceeds a predetermined second threshold, A delay time adding means for selectively adding a delay time to a logic output of a logic cell library driving the node connection by a control input, and a logic output of a logic cell library driving a node connection corresponding to the other wiring. Adding a capacitively coupled virtual connection to be transmitted to the delay time addition means as the control input to a logic simulation netlist.

[0015]

The structure of the action] of claim 1 the invention, the delay time adding means, because it is provided in a node connected to be driven by the logical cell library, the initial state of the logic output of the logic cell library This transition direction And the transition time. Further, the delay time adding means can obtain the initial state, the transition direction, and the transition time of the logic output of another logic cell library by the capacitive coupling virtual connection. Thus, the delay time adding means, it is possible to determine the variation in the delay time due to the influence of the capacitive coupling existing between the one wiring and another wiring, the capacitive coupling to the logic output of the logical cell library A delay time considering the influence can be added.

By using a logic simulation apparatus having such a delay time adding means and a capacitance coupling virtual connection, it is possible to easily realize a variation in delay time due to capacitance coupling between wirings connecting logic cells in a logic simulation. it can.

According to the configuration of the second aspect of the present invention, a correction value of the delay time corresponding to the variation of the delay time is obtained in advance,
By using the delay time correction value table, the delay time adding means can be easily realized.

In addition, according to the configuration of the third aspect of the present invention, delay time adding means is not provided for all node connections in which capacitive coupling exists, but only for node connections in which the strength of capacitive coupling exceeds a predetermined threshold value. A delay time adding means can be provided. Thereby, the size of the logic simulation netlist can be reduced to a realistic size.

According to the configuration of the fourth aspect of the present invention, as the strength of the capacitive coupling, a time constant, which is a product of the impedance of the logic cell and the coupling capacitance, and a capacitance ratio, which is a ratio of the coupling capacitance to the total capacitance of the wiring. And ask. The time constant represents the absolute magnitude of the change in the delay time due to the capacitive coupling, and the capacitance ratio represents the relative magnitude of the change in the delay time due to the capacitive coupling in the wiring. Therefore, the threshold value of the time constant is set to a value such that a desired absolute accuracy is obtained with respect to the delay time, and the threshold value of the capacitance ratio is set such that a desired relative accuracy is obtained with respect to the delay time. By setting appropriate values, it is possible to obtain a logic simulation netlist in which a delay time with a desired accuracy is taken into consideration.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A logic simulation apparatus using a logic simulation netlist according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a logic simulation netlist according to a first embodiment of the present invention. In FIG. 1, the logic simulation netlist is 10
There are six logic cell libraries a to 10f.
The left terminal of the logic cell library is an input terminal, and the right terminal is an output terminal. The connection between the logic cell libraries determined by the logic design is made by the node connection of the design logic of 11a to 11e. Node connections 11b and 11
c is a wiring physically adjacent to the node connection 11b
There is a coupling capacitance 12 between and. Since the capacitive coupling 12 exists between the node connections 11b and 11c, the node connections 11b and 11c are provided with delay time adding means 13a and 13b, respectively. In order to transmit the initial state, the transition direction, and the transition time of the logic of the logic cell library 10e to the delay time adding means 13a, a capacity coupling virtual connection 14a independent of the design logic is provided. Similarly, a capacitance coupling virtual connection 14b irrelevant to the design logic is provided to transmit the initial state, transition direction, and transition time of the logic of the logic cell library 10c to the delay time adding means 13b. The capacitive coupling virtual connection connects the node connection on one end of the coupling capacitor to the control input terminal of the delay time adding means provided at the node connection on the other end. For example,
The logic output terminal of the logic cell library 10e is connected to the control input terminal 15a of the delay time adding means 13a by a capacitive coupling virtual connection 14a. Similarly, the logic output terminal of the logic cell library 10c is connected to the control input terminal 15b of the delay time adding means 13b by the capacitance coupling virtual connection 14b.

FIG. 2 is a diagram showing a circuit corresponding to the logic simulation netlist of the first embodiment shown in FIG. In FIG. 2, 20a to 20f are inverters, and 21a to 21c are wirings. Wiring 21b, 21c
Are connected adjacent to each other, and a coupling capacitance 22 exists between the wirings 21b and 21c. The wirings 21b and 21c correspond to the node connections 11b and 11c shown in FIG. 1, respectively.

3 (a), 3 (b), 3 (c), 3 (d) and 3 (e), the initial state, transition direction and transition of the logic of the logic cell library 10e will be described. Is transmitted to the delay time adding means 13a and the logic cell library 10c
How the initial state of the logic, the transition direction, and the transition time are transmitted to the delay time adding means 13b to correct the delay time fluctuation due to capacitive coupling will be described.

FIG. 3A is an equivalent circuit corresponding to a portion of the circuit shown in FIG. 2 which is composed of inverters 20c and 20e and wirings 21b and 21c. In FIG. 3A, output nodes of inverters 36 and 37 are shown as nodes Na and Nb, respectively. Cc indicates a coupling capacitance, and Ca and Cb indicate capacitances at the nodes Na and Nb excluding the coupling capacitance Cc, respectively. Also, Rpa, Rna
Indicates the equivalent on-resistance (output impedance) of the transistor forming the inverter 36, and Rpb and Rnb indicate the equivalent on-resistance of the transistor forming the inverter 37.

Now, consider a case where nodes Na and Nb simultaneously transition from arbitrary initial states to H and H, respectively. Assuming that the input ramp of the inverter is sufficiently faster than the ramp of the output waveform (a circuit in which capacitive coupling is a problem generally has a large load capacitance, and this assumption holds), the N-channel transistor constituting the inverter is quickly turned off. State, and the P-channel transistor is considered to be almost on during the state transition of the output node, and its equivalent circuit can be approximated by the circuit shown in FIG. By giving the potential before the state transition as the initial state of the nodes Na and Nb, the time dependence of the potentials of the nodes Na and Nb can be solved, and the delay time can be obtained. The time dependency V (t) of the potentials of the nodes Na and Nb is given by: V (t) = K1 × exp (a × t) + K2 × exp (b × t) +
K3 (where K1, K2, K3, a and b are constants). Similarly, equivalent circuits when the nodes Na and Nb simultaneously transition to L, L, H, L, L, and H are respectively represented by FIGS. 3C, 3D, and 3E. You. If the nodes Na and Nb do not transition at the same time, the transition of FIG.
(B) The delay time can be calculated by switching the equivalent circuits of FIGS. 3 (c), 3 (d) and 3 (e). In the equivalent circuits of FIGS. 3B to 33E, the wiring resistance is omitted. More precisely, Cc, Ca, and Cb are divided into several π-type RC networks in consideration of wiring resistance. In particular, in the case of a long wiring exceeding several tens of mm, high-precision calculation can be performed by treating the wiring as a transmission line in consideration of the wiring's self-inductance and mutual inductance in addition to the wiring resistance and the wiring capacitance.

In summary, it can be seen that the equivalent circuit is determined by the logic transition direction, and the initial value required to solve the transient characteristics of the equivalent circuit is determined by the initial state of the logic before the transition. In this way, by specifying the initial state of logic, the transition direction, and the transition time, the delay time of the node connection where the capacitive coupling exists can be obtained. The actual calculated value of the delay time can be easily obtained by transient analysis using a SPICE circuit simulator or the like.

FIGS. 4 (a), 4 (b), 4 (c) and 4 (d) are diagrams showing a change in delay time due to a difference in transition time between the logics of the inverters 36 and 37. In the figure, 38 is the input of the inverter 36, 39 is the inverter 3
7 denotes an input and 40 denotes an output of the inverter 37.
This shows how the delay time between the input and the output of the inverter 37 changes according to the input of the inverter 36. When the logic transitions of the inverters 36 and 37 are in the same direction, the delay time is minimized (Tpd (min) in FIG. 4A).
When the logic transitions of the inverters 36 and 37 are in opposite directions, the delay time is maximized (Tpd (ma in FIG. 4C).
x)). If there is a phase difference between the transition times of the logics of the inverters 36 and 37, or if the logic of the inverter 36 does not make a transition, the delay time is an intermediate value between Tpd (max) and Tpd (min) ( Tpd (med) in FIG.
Tpd (typ) in FIG. 4 (d)).

The delay time adding means 13a, 13b in FIG. 1 has a table of delay time correction values calculated in advance using the logic transition direction and the transition time difference as indices. In the delay time adding means 13a, the capacitive coupling virtual connection 14a
The correction value of the delay time is determined by the initial state, the transition direction, and the transition time of the logic of the logic cell library 10e transmitted by the logic cell library 10e and the output of the logic cell library 10c. Further, in the delay time adding means 13b, the correction value of the delay time is determined by the initial state, the transition direction, and the transition time of the logic of the logic cell library 10c transmitted by the capacitive coupling virtual connection 14b, and the output of the logic cell library 10e. It is determined. These delay time correction values are obtained by using a SPICE circuit simulator or the like before executing the logic simulation.

Table 1 shows an example of a table of correction values for delay time.

[0030]

[Table 1]

In Table 1, for example, a transition from logic H to logic L is indicated as “H → L”. The transition time difference is represented by the logic transition time of the node Na as Tna and the node Nb.
Is given by Tna−Tnb, where Tnb is the transition time of the logic. In Table 1, a delay time correction value is given using the node name, the transition direction, and the transition time difference as indices. The correction value of the delay time with respect to the transition time difference not inscribed in Table 1 is obtained by the interpolation method.

In the present embodiment, the delay time adding means 13a and 13b have the delay time correction values as a table. Instead of the tables, the delay time correction values are provided in real time during the logic simulation. The calculating means for calculating may be provided on the logic simulation netlist.

FIG. 5 is a diagram showing a configuration of a logic simulation netlist according to the second embodiment of the present invention. In FIG. 5, the logic simulation netlist is 60
a to 60 g of seven logic cell libraries are provided.
The node connection 61b is capacitively coupled to the two node connections 61a and 61c, respectively. Node connections 61a and 61b
A coupling capacitance 62a exists between the node connections 61b and 61c, and a coupling capacitance 62b exists between the node connections 61b and 61c.
In order to express two capacitive couplings, two delay time adding means 63a and 63b are provided in the node connection 61b. The control input terminal 65a of the delay time adding means 63a is connected to a capacitive coupling virtual connection 64a for transmitting the initial state, transition direction, and transition time of the logic of the logic cell library 60a. The control input terminal 65b of the delay time adding means 63b is connected to a capacitive coupling virtual connection 64b for transmitting the initial state, transition direction, and transition time of the logic of the logic cell library 60f.

FIG. 6 is a diagram showing a circuit corresponding to the logic simulation netlist of the second embodiment shown in FIG. 6, 70a to 70g are inverters, and 71a to 71c are wirings. Wiring 71a, 71c
Are connected adjacent to the wiring 71b, a coupling capacitance 72a exists between the wirings 71a and 71b, and a coupling capacitance 72b exists between the wirings 71b and 71c. The wirings 71a, 71b, 71c correspond to the node connections 61a, 61b, 61c shown in FIG. 5, respectively.

FIG. 7 is a diagram showing a configuration of a logic simulation netlist according to the third embodiment of the present invention. In FIG. 7, the logic simulation netlist is 80
It has three logic cell libraries a to 80c.
The node connection 81b corresponding to the center wiring among the three parallel wirings is provided with delay time adding means 83b, and the node connections 81a and 81c corresponding to the wirings on both sides are provided with delay time adding means 83a and 83c, respectively. Is provided.
The delay time adding means 83b has two control input terminals 85a,
85b, the initial state, the transition direction, and the transition time of the logic of the logic cell library 80a are obtained by the capacitive coupling virtual connection 84a connected to the control input terminal 85a, and connected to the control input terminal 85b. The initial state, transition direction, and transition time of the logic of the logic cell library 80c are obtained by the capacitance coupling virtual connection 84b.

As in the logic simulation netlists of the second and third embodiments, a plurality of delay time adding means is provided for one node connection, or a delay time adding means having a plurality of control input terminals is provided. Thus, capacitive coupling having an arbitrary connection structure can be expressed.

As described above, according to the first, second and third embodiments, by providing the delay time adding means and the capacitive coupling virtual connection on the logic simulation netlist used in the logic simulation, the capacitive coupling is achieved. Can be easily realized in consideration of the timing simulation.

Next, an example of the back annotation method for creating the logic simulation netlist of the first, second and third embodiments will be described with reference to the drawings.

FIG. 8 is a flowchart showing a back annotation method according to this embodiment. In FIG. 8, 5
Reference numeral 7 denotes a logic simulation netlist before back annotation, and reference numeral 41 denotes a layout in which arrangement and wiring are performed based on the logic simulation netlist 57.

In step S1, layout parameter extraction (Layout ParameterExtaraction; LP)
E) By the process 42, data relating to the wiring resistance, the wiring capacitance, etc., associated with the connection of the nodes wired from the layout 41 is extracted. The extracted data is collated with the corresponding node connection name on the logic simulation netlist 57 by the collation processing 43, and a comparison table 44 between the node connection name-logic cell driving capacity Rd-total wiring capacitance Ct-coupling capacitance Cc.
Is converted to An example of the control table 44 is shown in (Table 2).

[0041]

[Table 2]

Table 2 shows a plurality of node connections.
At each node connection, the driving capability Rd of the logic cell that drives the node connection (equivalent to the output impedance)
, A total wiring capacitance Ct of the node connection, a plurality of coupling capacitances Cc, and a node name of a capacitance coupling destination of each coupling capacitance Cc. As described above, the comparison table 44 includes information necessary for forming the capacitive coupling between the wirings on the logic simulation netlist.

Next, in step S2, the control table 4
In the calculation processing 45 using the time constant 4, the time constant τ
= Rd × Cc, and the capacity ratio r = Cc / Ct. The time constant τ indicates the absolute magnitude of the change in the delay time due to the capacitive coupling, and the capacitance ratio r indicates the relative magnitude of the change in the delay time due to the capacitive coupling at the node connection. I have. The larger the value of both parameters, the greater the effect of capacitive coupling.

In general, it is difficult to handle all coupling capacitances due to restrictions on the size of the logic simulation netlist, simulation time, and the like. Therefore, it is necessary to selectively handle a coupling capacitance having a large effect. The threshold value τth of τ and the threshold value rth of r are used as conditions for this selection. In the judgment processing 46, the comparison table 44 is changed to τ>τthorr>.
rth (that is, the variation of the delay time due to the coupling capacity is τ
The node connection where th [ns] or more or the ratio of the variation in the delay time due to the coupling capacity to the total delay time is rth or more) is divided into the comparison table 47, and the other node connections are divided into the comparison table 56. I do.

In step S 3, a table calculation process 48 for calculating the correction value of the delay time in the table of the delay time adding means using the comparison table 47 for each node connection.
And a netlist creation process 49 for creating a logic simulation netlist including the delay time adding means and the capacity coupling virtual connection. Based on the results obtained by executing the table calculation processing 48 and the netlist creation processing 49, a delay time adding means-capacity coupling virtual connection netlist 50 including information on the delay time associated with the capacitive coupling is created.

Each process in step S4 is the same as in the conventional back annotation method. Delay time calculation processing 55 for calculating the delay time associated with the wiring for each node connection using the comparison table 56, and delay time update processing for updating the information on the delay time in the logic simulation netlist 57 based on the calculation result 54 to obtain a logic simulation netlist 53 in which back-annotation has been performed on node connections without capacitive coupling.

In step S5, a netlist synthesizing process 51 for synthesizing the logical simulation netlist 53 and the delay time adding means-capacitive coupling virtual connection netlist 50 is performed, and the logical simulation netlist back-annotated with respect to the coupling capacitance. 5
Get 2.

As described above, according to the back-annotation method of this embodiment, it is possible to back-annotate the capacitive coupling between wirings in the logic simulation netlist. In addition, as the back-annotated logic simulation netlist, the necessary minimum one can be obtained because the effect due to the capacitive coupling is selectively taken into the node connection according to the strength of the capacitive coupling.

In the present embodiment, the node connection considering the effect of the coupling capacitance is determined using the time constant r and the capacitance ratio τ. However, the node connection is determined using the value calculated by another strength calculation method. You may choose. For example, τ = (Rd + Rw) × Cc may be used without omitting the node connection wiring resistance Rw. Further, when a material having a very low resistance is considered as a material for the wiring, a resistance due to a self-inductance may be used instead of the wiring resistance. Mutual inductance can be one factor that causes a delay time to fluctuate due to interaction between wires. However, since a large mutual inductance involves a large coupling capacitance, a node connection with a large mutual inductance can be extracted in the present embodiment.

The important point of the back annotation method of the present embodiment is that the strength of the capacitive coupling is evaluated, and the delay time adding means is selectively provided at the node connection where the strength of the capacitive coupling is large.

[0051]

As described above, according to the logic simulation apparatus of the first aspect of the present invention, in the logic simulation, the capacitance coupling between the wirings connecting the logic cells is performed by the delay time adding means and the capacitance coupling virtual connection. Can easily realize the variation of the delay time. Therefore, it is possible to realize highly accurate timing verification in the logic simulation.

According to the logic simulation apparatus of the second aspect of the present invention, the delay time adding means can be easily realized by using the table including the delay time correction values obtained in advance.

Further, according to the back annotation method of the third aspect of the present invention, in the logic simulation netlist, only the node connection where the strength of the capacitive coupling exceeds a predetermined threshold among the node connections having the capacitive coupling is delayed. Time adding means can be provided. Thereby, the size of the logic simulation netlist can be reduced to a realistic size.

According to the back annotation method of the present invention, the threshold value of the time constant is set to a value that can provide a desired absolute accuracy with respect to the delay time, and the threshold value of the capacitance ratio is set as the threshold value. By setting a value such that a desired relative accuracy with respect to the delay time is obtained, a logic simulation netlist in which a delay time with a desired accuracy is considered can be obtained.

As described above, according to the present invention, highly accurate timing verification can be realized in a logic simulation. As a result, it is not necessary to increase the margin at the time of timing design as in the related art, and it is possible to reduce the number of gates, reduce the chip area, reduce power consumption, reduce costs, and the like. Further, as the semiconductor process technology advances in the direction of miniaturization, the effect of the coupling capacitance between wirings on the delay time increases, so that the effectiveness increases.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing a configuration of a logic simulation netlist according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit corresponding to a logic simulation netlist of the first embodiment.

FIG. 3A is a circuit diagram showing a transistor-level circuit corresponding to the logic simulation netlist of the first embodiment, and FIG. 3B is a circuit diagram showing a node N of the circuit shown in FIG.
FIG. 4 is a circuit diagram showing an equivalent circuit when a and Nb transition to H and H, respectively. FIG. 5C is a circuit diagram showing an equivalent circuit when nodes Na and Nb transition to L and L, respectively. (d) is a circuit diagram showing an equivalent circuit when nodes Na and Nb transition to H and L, respectively, and (e) is a circuit diagram showing an equivalent circuit when nodes Na and Nb transition to L and H, respectively. It is.

FIG. 4A is a timing chart showing a delay time when logic transitions of two inverters in the circuit of FIG. 3A according to the first embodiment are in the same direction, and FIG. It is a timing chart which shows the delay time when the logic transition time of two inverters has a phase difference, and (c) is a timing chart which shows the delay time when the logic transitions of two inverters are mutually opposite directions. FIG. 6D is a timing chart showing a delay time when the logic of one inverter does not transition.

FIG. 5 is a conceptual diagram showing a configuration of a logic simulation netlist according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a circuit corresponding to a logic simulation netlist of the second embodiment.

FIG. 7 is a conceptual diagram showing a configuration of a logic simulation netlist according to a third embodiment of the present invention.

FIG. 8 is a flowchart illustrating a back annotation method according to the first, second, and third embodiments.

[Explanation of symbols]

10a to 10f, 60a to 60g, 80a to 80c Logical cell library 11a to 11e, 61a to 61c, 81a to 81c Node connection 13a, 13b, 63a, 63b, 83a to 83c Delay time adding means 14a, 14b, 64a, 64b, 84a, 84b Capacitive coupling virtual connection

Claims (4)

(57) [Claims] A logic cell library;Live logical cell
Between RariNode connection andLogical design of netlist
Created and used this netlistLogical simulation
SolutionIn the device,  Capacitive coupling existspluralEquivalent to wiringpluralnode
Provided in the connection,TheDrive node connectionTheoryScience cellula
For library logic output,Selectively delayed by control input
Add a breakpluralDelay time adding means, The delay time provided at one of the plurality of node connections
In the additional means, the other Drive node connectionTheorySercelli
The logic output of the library,As the control inputTetsudenCapacity
Logic simulation characterized by having a virtual connection
Optionapparatus. 2. The delay time adding means has a table including a delay time correction value, and transmits the delay time as the control input by the capacitive coupling virtual connection.
It was based on the transition direction and transition time of the logic output, by selecting the correction value of the delay time from among the table, to claim 1, characterized in that to determine the delay time for pressurizing with The described logic simulation equipment
Place . 3. A back-annotation method for providing a delay time of a real wiring after layout to a logic simulation, comprising: extracting a capacitance related to the node connection from the layout for each node connection; Calculating, for each node connection corresponding to one wiring having a capacitive coupling between them, a strength of the capacitive coupling based on a coupling capacitance which is a capacitance due to the capacitive coupling; and A delay time adding means for selectively adding a delay time by a control input to a logic output of a logic cell library provided at the node connection and driving the node connection, for each node connection exceeding the threshold value; The logic output of the logic cell library driving the node connection corresponding to the above is transmitted to the delay time adding means as the control input. Adding to the logic simulation netlist with the capacitively coupled virtual connection. 4. A back-annotation method for giving a delay time of a real wiring after layout to a logic simulation, the method including, for each node connection, extracting a capacitance related to the node connection from a layout; For each node connection corresponding to one wiring in which a capacitive coupling exists between the output impedance (Rd) of the logic cell driving the one wiring and the coupling capacitance (Cc), which is the capacitance due to the capacitive coupling. A time constant (Rd × Cc), which is a product, and a capacitance ratio (Cc / Cc), which is a ratio of the coupling capacitance (Cc) to the total capacitance (Ct) of the one wiring.
Ct), and for each node connection whose time constant (Rd × Cc) exceeds a predetermined first threshold or whose capacitance ratio (Cc / Ct) exceeds a predetermined second threshold. Delay time adding means provided at the node connection for selectively adding a delay time by a control input to a logic output of a logic cell library driving the node connection, and logic for driving a node connection corresponding to the other wiring Adding a capacitively coupled virtual connection for transmitting a logic output of a cell library as the control input to the delay time adding means to a logic simulation netlist.