JP3000499B2 - DA conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
The present invention relates to a DA conversion circuit using an OS type semiconductor.

[0002]

2. Description of the Related Art A conventional charge-redistribution type D / A converter using a capacitor array, as described in the following document, charges and discharges a capacitor array corresponding to an input digital data pattern on a 1: 1 basis. Get analog output. Since the accuracy of the analog output is limited by the specific accuracy of the capacitor used, a conversion accuracy better than the specific accuracy cannot be obtained.

[0003] McCreary, JL and Gray, PR: "AL
L-MOS charge redistributionanalog-to-digital conve
rsion techniques-Part I ", IEEE J. Solid StateCi
rcuirts, SC10, 6, pp. 371-379 (1975)

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to make the conversion accuracy of a DA converter better than the specific accuracy of a capacitor which is a component thereof.

[0005]

According to the present invention, the capacitors used in the DA converter are sequentially replaced with time, and the outputs are averaged later.

[0006]

According to the present invention, the ratio accuracy of the capacitors can be averaged.

[0007]

1 shows a first embodiment of a DA converter according to the present invention.
This will be described with reference to FIGS. In FIG. 1, 2
The DA conversion data of the base numbers b _0, b _{1, and} b ₂ are first input to the decoding circuit 1. FIG. 3 shows the relationship between the inputs b _0, b _1, b _{2 of the} decoding circuit 1 and the outputs x _1, x _2, x ₃ . The output terminal of the decoding circuit 1 is connected to the multiplexer 2. Input x ₁ multiplexer _2, x 2, x ₃ ... and the output y _1, y _2, y
₃ are related to the control clocks CLKa, CLKb, CL
The phase changes as shown in FIG. 4 depending on phases 0 to 7 created by Kc. The control clocks CLKa, CLKb,
FIG. 2 shows the relationship between CLKc and the phase.

The output of the multiplexer 2 is a clock φ
The remaining single inputs of the AND gates 3 to 9 having 1 as the single input are obtained. Switches 10 to 16 are controlled by outputs of AND gates 3 to 9. One end of each of the switches 10 to 16 is connected to the first reference
It is connected to a position to become GND potential. Switch 10
The other end of 16 is connected to one end of DA capacitors 26 to 32. One ends of the DA capacitors 26 to 32 are connected to one ends of the switches 17 to 23 at the same time. The other ends of the switches 17 to 23 are connected to a reference voltage application terminal 35 serving as a second reference potential . The clock φ2 is commonly input to the control terminals of the switches 17 to 23.

The other ends of the DA capacitors 26 to 32 are commonly connected to an inverting input terminal of an operational amplifier 37.
The inverting input terminal of the operational amplifier 37 simultaneously supplies the clock φ2
Of the switch 24 controlled by the
3 is connected to one end. The other end of the switch 24 and the other end of the output capacitor 33 are connected to output terminals of an operational amplifier 37, respectively. The output terminal of the operational amplifier 37 is simultaneously connected to one end of the switch 25 controlled by the clock φ1. The other end of the switch 25 is an output terminal 36
And one end of the output capacitor 34. The other end of the output capacitor 34 is connected to the GND potential.

The capacitors 26 to 32 and the switch 10
To 23 and AND gates 3 to 9
Called converter 38. The circuit shown in FIG. 1 operates by two-phase clocks φ1 and φ2 which do not overlap each other as shown in FIG. In the circuit diagram of FIG.
The operational amplifier 37 connected to the D potential and the operational amplifier 37
Capacitor 33 connected between inverting input terminal and output
And the switch 24 connected in parallel with the capacitor 33
The configured circuit constitutes a so-called charge transfer circuit,
Charge of the capacitors 26 to 32 of the D / A converter 38
It has a function of transferring to the capacitor 33. Operational amplifier 37
A switch 25 connected between the output and the output terminal 36;
Capacitor 3 connected between force terminal 36 and GND potential
4 is a so-called sample-and-hold circuit.
And the output voltage value of the operational amplifier 37 during the period of φ1
Has the function of sampling and holding during periods other than φ1
You. Hereinafter, the operation at clock φ2 and clock φ1 will be described respectively.
explain. During the period φ2, the switch 24 is closed and the capacitor is closed.
The capacitor 33 is short-circuited and the electric charge becomes zero. Operational amplifier 37
Is short-circuited between the inverted input terminal and the output. Operational amplifier 37
Since the non-inverting input terminal is connected to the GND potential,
The input and output terminals of the operational amplifier 37 are
It becomes the GND potential. One end of each of the capacitors 26 to 32 is φ
Reference voltage mark through switches 17 to 23 which are closed for 2 periods
It is connected to an additional terminal 35. The other end is connected to operational amplifier 37
Since they are connected, the capacitors 26 to 32
Charged to pressure. During the period of φ1, the switch 24 is open,
Switches 17 to 23 are also opened, and switch 25 is closed. S
Opening and closing of the switches 10 to 16 is performed by the output Y of the multiplexer 2.
Switches 10 to 16 are closed, depending on the state of 1 to Y7
Then, the capacitors connected to the switches 10 to 16
One ends of 26 to 32 are connected to the GND potential. Capacity
The other ends of the inverters 26 to 32 are connected to the inverting input terminal of the operational amplifier 37.
Although connected, the operational amplifier 37 has a capacitor 33
And negative feedback is applied, the potential of the inverting input terminal is
Since it is a so-called virtual ground, the voltage of the non-inverting input terminal
Equal, that is, equal to the GND potential. Capacitor 26
Where one end is closed between switches 10 to 16
Is connected to the SGND potential at both ends.
Discharge because it becomes. The current at the time of discharge
Pass through to the output of the operational amplifier 37,
Charge is transferred to the capacitor 33 according to the law. Opea
The output voltage of the amplifier 37 is supplied to the
The battery 34 is charged. The voltage of the capacitor 34, that is, the output terminal
The voltage value of the capacitor 36 is the operational value of the capacitor 34.
If the amplifier 37 has a chargeable capacity value, the operational amplifier 37
It becomes equal to the output voltage value. Here, switches 10 to 16
Is connected to the GND potential.
Only fixed charge / discharge voltage values differ
Yes, no problem in operation. Switch 25 and capacitor 3
In the sample and hold circuit composed of
Then, the switch 25 is closed and the operation as the DA conversion result is performed.
The output of the amplifier 37 charges the capacitor 34 and
Output from the output terminal 36. During periods other than φ1,
Since the switch 25 is open, the capacitor 34
The voltage in the period of 1 is held. Therefore, the period of φ2
During this time, the output of the operational amplifier 37 is at the GND potential.
Does not appear at the output terminal 36,
The charge charged by the capacitor 34 appears in the element 36, and D
Only the A conversion result is output. The capacitor 34
Because it is a capacitor for holding, the capacitance value is the leakage current
A practical value can be adopted in consideration of the influence of the above. In addition, this implementation
In the example, the charge transfer circuit is composed of an operational amplifier 37 and a capacitor.
33 and a switch 24. This circuit is common
Circuit, for example, an operational amplifier 37, a switch 25,
The capacitor 34 is removed, and the switch 24 and the capacitor are simply
With the capacitor 33 connected in parallel,
The terminal connected to the capacitors 26-32 at the end is the output end
Although the output voltage value is different even if the
It is possible. Next, the circuit operation of the local DA conversion circuit 38 will be described.
This will be described in detail. First, the switch 24 is turned on while the clock φ2 is “1”, so that the electric charge of the capacitor 33 is reset to 0 by discharging, and the switches 17 to 23 are turned off.
Is turned on and the capacitors 26 to 32 are connected to the reference voltage application terminal 3
5 is charged to the voltage value V _REF applied to. Next, during the period when the clock φ1 is “1”, the output Y of the multiplexer 2 is output.
The outputs of the AND gates 3 to 9 become "1" corresponding to the output which was "1" among 1 to Y7. Switches 10-1
6, the output becomes "1" at the AND gates 3 to 9, so only the corresponding switch is turned on, and the capacitors 26 to
The corresponding capacitor of the 32 discharges. Assuming that the values of the capacitors ₂₆ to ₃₃ are respectively C _{26 to} C ₃₃ , an output V _out is generated at the output terminal 36 as in the following equation.

[0011]| Vout | = V_REF・ (Y1 · C₂₆+ Y2 · C₂₇+ Y3 · C₂₈+ Y4 · C₂₉+ Y5 · C₃₀+ Y6 · C₃₁+ Y7 · C₃₂  ) / C₃₃… (1)(C ₃₄ Is the switch 2
5 is turned off to discharge to the output terminal 36,
It is a capacitor for performing pull hold, and | Vou
It does not affect the value of t |
I) For example, Y1 = "0", Y2 = "0", Y3 =
“0”, Y4 = “1”, Y5 = “1”, Y6 = “1”,
If Y7 = "0", the corresponding AND gate6, 5,
4 becomes "1" and the corresponding switches 13, 1
4 and 15 are turned on and capacitors 29, 30 and 31 are discharged
I do. Therefore, the output is given by equation (1).| Vout | = V_REF・ (0 ・ C₂₆+0・ C₂₇＋0 ・ C₂₈+1・ C₂₉  + 1 · C₃₀+ 1 · C₃₁＋0 ・ C₃₂) / C₃₃  = V_REF・ (C ₂₉ + C₃₀+ C₃₁) / C₃₃… (2)

On the other hand, one input b ₀ -b ₂ of the decoding circuit
And the outputs X1 to X7 are uniquely determined as shown in FIG. For example, b ₀ = “1”, b ₁ = “1”, b ₂ =
When it is “0”, the inputs x _{1 to} x _{7 of the} multiplexer 2
From FIG. 3, x ₁ = “0”, x ₂ = “0”, x ₃ =
_{"0", x 4 = "} 0", x 5 = "1", x 6 = "1",
x ₇ = “1”. Outputs Y1 to Y of multiplexer 2
7 are the clock signals CLKa, CLKb,
It changes sequentially according to the temporal relationship with CLKc, phase 0 to phase 7. In phase 0, CLKa = "0" and CLKb =
“0”, CLKc = “0” period, and phase 1 is CLK
a = “1”, CLKb = “0”, and CLKc = “0”. When the relationship between the number of phases and CLKa, CLKb, CLKc is expressed by an equation, the number of phases = CLKa · 1 + CLKb · 2 + CLKc · 4 (3) Number of phases and inputs x _{1 to} x _{7 of} multiplexer 2
FIG. 4 shows the relationship between the outputs and the outputs y _{1 to} y ₇ of the multiplexer 2.

As can be seen from FIG.₁= “0”, x_Two
= “0”, x_Three= “0”, x_Four= “0”, x_Five=
“1”, x₆= “1”, x₇= “1”, phase 1
If x₁= Y₁, X_Two= Y_Two... x₇= Y₇What
And y₁= “0”, y_Two= “0”, y _Three= “0”, y_Four
= “0”, y_Five= “1”, y₆= “1”, y₇= “1”
Then, in the case of the next phase 2, similarly from FIG.₁=
y₇, X_Two= Y₁, X_Three= Y_Two... x₇= Y₆What
And y₁= “0”, y_Two= “0”, y_Three= “0”, y_Four
= “1”, y_Five= “1”, y₆= “1”, y₇= “0”
Becomes That is, x over time_nAnd y_nThe relationship is strange
Wrong. However, the number of “1” included in X1 to X7 and Y1
Since the number of “1” s included in Y7 is the same,₂₆~ C
₃₂Are identical, then the same b₀~ B_TwoSame out for
Force value.

However, in general, the values of C _{26 to} C ₃₂ are different even though the design values are the same due to manufacturing variations and the like. Therefore, the output value for the same b ₀ ~b ₂ varies with time. Output value smoothing by a filter or the like of this change is the average of the values of C ₂₆ -C _32. Hereinafter, a description will be given using numerical examples.

The input of the decoding circuit 1 is b ₀ = "1", b
₁ = "1", when b ₂ = "0", the output of the decoding circuit 1, that is, the input X1~X7 multiplexer circuit 2 in accordance with FIG. 3, x ₁ = "0", x ₂ = "0", x ₃ =
_{"0", x 4 = "} 0", x 5 = "1", x 6 = "1",
x ₇ = “1”.

V_REF= 1v, C₃₃= 1, C₂₆= 1.0
5, C₂₇= 1.15, C₂₈= 0.9, C₂₉= 1.0, C
₃₀= 1.1, C₃₁= 0.85, C₃₂= 0.95
And when the phase is 0, outputs Y1 to Y7 of the multiplexer 2
Is, according to FIG. 4, x₁= Y₁, X _Two= Y_Two, X_Three= Y
_Three... x₇= Y₇Becomes What is “1” is
y_Five,y_6,y₇Therefore, the output V at the time of phase 0 is obtained from the equation (1).
_out(0) is V_out(0) = C₃₀+ C₃₁+ C₃₂= 1.1 + 0.8 + 0.95 = 2.85 Since the phase changes from phase 0 to phase 7 with the passage of time,
Inputs X1 to X7 of the multiplexer 2 and Y of the multiplexer 2
The relationship of 1 to Y7 changes according to FIG. Details below
State.

The input of the multiplexer 2 becomes "1".
Is, as mentioned earlier, x_Five,x_6,x₇It is. phase
When 0, the input / output relationship of the multiplexer 2 is in accordance with FIG.
Yes, x₁= Y₁, X_Two= Y_Two, X_Three= Y_Three... x₇=
y₇So "1" is y_Five,y_6,y₇And phase
When 1, the input / output relationship is x₁=
y₁, X_Two= Y_Two, X_Three= Y_Three... x₇= Y₇So
"1" is y _Five,y_6,y₇And in phase 2
The above-mentioned input-output relationship follows from FIG.₁= Y ₇, X_Two
= Y₁, X_Three= Y_Two... x₇= Y₆So it ’s “1”
Is y_Four,y _Five,y₆In the case of phase 3, the aforementioned entry
The output relation is x according to FIG.₁= Y₆, X_Two= Y₇, X
_Three= Y₁... x₇= Y_FiveTherefore, "1" is y
_3,y_Four,y _FiveBecomes

Similarly, the input / output relationship for each phase is determined. If the equation (1) is applied, the outputs V _out (1) to V _out (5) in the phases 1 to 5 are as follows: V _out (1) = C ₃₀ + C ₃₁ + C ₃₂ = 1.1 + 0.8 + 0. 95 = 2.85 V _out (2) = C ₂₉ + C ₃₀ + C ₃₁ = 1.0 + 1.1 + 0.8 = 2.90 V _out (3) = C ₂₈ + C ₂₉ + C ₃₀ = 0.9 + 1.0 + 1.1 = 3.00 V _out (4) = C ₂₇ + C ₂₈ + C ₂₉ = 1.15 + 0.9 + 1.0 = 3.05 V _out (5) = C ₂₆ + C ₂₇ + C ₂₈ = 1.05 + 1.15 + 0.9 = 3. When 10 V _out (0) to V _out (5) are averaged, the expected value of V _out = 2.96 V _out is 3.0, so the error is −0.04. When the phase is fixed, that is, when the averaging is not performed, the error becomes the maximum value -0.15 when the phase is 1, the minimum value is 0 when the phase is 3, and the error decreases except for the output of the phase 3. I have. In this example, the average value is calculated six times, but the error decreases as the average number increases.

FIG. 5 shows an example of a circuit for realizing the logic of FIG. 4, which is the multiplexer 2 of FIG. There are various other possible circuits for implementing the logic of FIG. Here, an example is shown to show that the logic of FIG. 4 can be easily realized. M in FIG.
The OS transistors 70 to 118 are used as switches. That is, when the gate voltages of the MOS transistors 70 to 118 are "1", the source and drain of each MOS transistor are conductive, and the switches are turned on. When the gate voltage is "0", the source and drain are conductive. Without this, the switch is turned off. AND gates 119 to 125 decode the states of clock signals CLKa to CLKc to create respective phases. FIG. 2 shows the relationship between each phase and clock signals CLKa to CLKc.
When both the clock signals CLKb and CLKc are “0”, only the output of the AND gate 119 becomes “1”, and the phase becomes 0 and 1, respectively. When the output of the AND gate 119 becomes "1", the MOS transistors 70 to 76 are turned on.
A _{1 = y 1, x 2 =} y 2, x 3 = y 3 ··· x 7 = y 7.

Next, CLKa = "0", CLKb =
When "1" and CLKc = "0", the AND gate 1
Only the output of 25 becomes “1” and becomes phase 2. Andge
When the output of the gate 125 becomes "1", the MOS transistor
Since the parameters 77 to 83 are turned on, x ₁= Y₇, X_Two=
y₁, X_Three= Y_Two... x₇= Y₆Becomes Similarly, CL
Each of the phases corresponds to the state of Ka, CLKb, and CLKc.
One of the AND gates 119 to 125 becomes "1".
Connected to each of the AND gates 119 to 125
The OS transistor is turned on to implement the logic of FIG.

[0021]

As described above, when the present invention is used, the variation in the DA conversion output caused by the variation in the capacitance value of the capacitor due to the manufacturing process can be averaged. Assuming that the specific accuracy of the capacitor is A (%), the average number of times is N, and the number of capacitors used is M, the accuracy of the DA converter is expressed as 1 / M / 1 / NA. If the averaging is not performed, the specific accuracy of the capacitor becomes the accuracy of the D / A converter as it is, but the averaging improves the D / A conversion accuracy up to N times. In particular, a so-called oversampling type D that assumes output averaging
This is effective for the A conversion circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of a DA converter according to the present invention.

FIG. 2 shows operation timings of FIGS. 1 and 5;

FIG. 3 shows an input / output relationship diagram of a decoding circuit 1;

FIG. 4 shows an input / output relationship diagram of the multiplexer 2.

FIG. 5 shows an implementation circuit diagram of the multiplexer 2.

[Explanation of symbols]

 Reference Signs List 1 decoding circuit 2 multiplexer 3-9 AND gate 10-25 switch 26-34 capacitor 35 reference voltage application terminal 36 output terminal 37 operational amplifier 38 local DA converter 70-118 MOS transistor 119-125 AND gate 126-128 inverter

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-30024 (JP, A) JP-A-4-152715 (JP, A) JP-A-2-309819 (JP, A) JP-A-63-1988 262921 (JP, A) JP-A-60-236329 (JP, A) JP-A-3-117703 (JP, A)

Claims (1)

(57) [Claims] 1. A charge redistribution DA conversion circuit, comprising: a decoding circuit for decoding digital input data to obtain a decoded signal; and an n-bit input terminal for receiving an n-bit signal to be used among the decoded output. And an n-bit output terminal for extracting the decoded output, and n × n switching elements provided in a matrix so as to switch between the input terminal and the output terminal. The terminal inputs an n-bit control signal that changes with the passage of time, and the correspondence between the input terminal and the output terminal is sequentially and uniformly switched over a predetermined circulation cycle with the passage of time, and the decoded output is output. a multiplexer configured to output from the output terminal, a plurality of output terminals of said multiplexer Each Re one end
And input the first clock signal to the other end.
A plurality of gate circuits, each controlled by the plurality of gate circuits, and one
A plurality of first switch circuits each having an end connected to a first reference voltage; and one end being connected to the other end of each of the plurality of first switch circuits.
A plurality of capacitors , the other ends of which are all connected to one output terminal; and one end connected to one end of each of the plurality of capacitors .
And the other end is connected to a second reference voltage, and the second clock
A DA conversion circuit comprising: a plurality of second switch circuits that operate in response to a clock signal .