JP2996942B2 - Receive error measurement system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception error measuring system, and more particularly to a hierarchization method in which a plurality of time slot data are multiplexed and different combinations of PSK modulation schemes and coding rates are allowed in units of time slots. Multiplexed frame data according to the transmission method is transmitted channel coding and PSK
The present invention relates to a reception error measurement system for a receiver that receives and demodulates a modulated transmission signal, decodes the decoded signal, and restores multiplexed frame data according to the original hierarchical transmission scheme.

[0002]

2. Description of the Related Art There is a time division multiplex system as a system for communicating a plurality of independent data at one carrier frequency. FIG.
The upper part of the figure shows the structure of multiplexed frame data on the transmission side. Data 1 to 4 are four independent data. On the transmitting side, the multiplexed frame data is subjected to transmission line coding (adding an error correction code or interleaving to enable error correction on the receiving side) and PSK modulation to generate a transmission signal, and the carrier frequency is set. After conversion, it is transmitted on radio waves. On the receiver side, after receiving the transmission radio wave and creating an intermediate frequency signal, PSK demodulation and decoding of the original multiplexed frame data are performed.
The desired independent data is extracted and used.

In time-division multiplex communication, usually, a plurality of independent data are all transmitted at the same coding rate and the same modulation scheme, and the rate of occurrence of a reception error in multiplexed frame data received and restored by a receiver is equal to the frame rate. It does not change anywhere within. Therefore, when the measurement of the reception error of division multiplex communication, as shown in FIG. 14, merely receives the data D _i of each bit position i of the restored multi-frame data RMD,
Same bit position i of multiplexed frame data SMD of transmission source
Is compared with the bit data D _i ′, and the number of mismatched bits is counted.

[0004] Independent data may have different uses, such as data that is transmitted in a large amount in a short time even if there is some error, and data that is transmitted almost without error even if it takes time. In digital satellite TV broadcasting, high-quality programs are the former, and normal-quality programs are the latter. Digital satellite T
In V broadcast, TS (Transport Stream) multiplexed frame data configured by multiplexing 48 time slot data (one time slot corresponds to one packet of MPEG2) shown in FIG. Each program data is allocated to one to a plurality of continuous time slots. The TS multiplexed frame data is allowed to have a combination of different modulation schemes and coding rates in units of time slots (however, the same program data has the same modulation scheme and coding rate), and is called a hierarchical transmission scheme. Different combinations of modulation schemes and coding rates mean different C / Ns required for transmission.

The first one byte of each time slot data is a synchronization signal, the next 187 bytes is a main signal, and the following k bytes are later replaced with an error-correcting outer code or time-adjusted for adding a burst signal. Additional data for 8PSK as a combination of modulation scheme and coding rate
(Trellis coded 8PSK) modulation (coding rate 2/3),
QPSK modulation (coding rate 1/2, 2/3, 3/4, 5 /
6, 7/8) and BPSK modulation (coding rate 1/2) are applicable. In a TS multiplex frame, TC8P
Program data is allocated in the order of a larger number of phases, such as SK, QPSK, and BPSK, and in order of a higher coding rate.

[0006] Program data for TC8PSK modulation is allocated in units of one slot.
As for the SK modulation program data, every time n slots are allocated, (mn) pieces of data are used as dummy slots for time adjustment that are not actually transmitted. Similarly, three BPSK modulation program data are set as dummy slots every time one slot is allocated. FIG. 15 shows that slots # 1 to # 2
Up to 4 for TC8PSK modulation, slots # 25, # 2
7, # 29, # 31, # 33, # 35, # 37, # 39
Is for QPSK modulation (coding rate 1/2), slot # 4
1 and # 45 are examples for BPSK modulation (coding rate 1/2).

FIG. 16 shows a transmission / reception system using a hierarchical transmission system. On the transmission side, the TS multiplexed frame data is input to an encoder (transmission path encoder) 1, where a part of the additional data of each slot is replaced with an outer code error correction code, scrambled (energy spreading processing), , A superframe identification signal indicating the beginning of a superframe composed of eight consecutive frames, and a transmission and multiplexing configuration (TMCC) indicating a transmission multiplex configuration in units of one superframe.
Slot # 1 in the transmission control (transmission multiplex control signal)
Replacement of leading bytes ranging from # 1 to # 12, interleaving, addition of inner code error correction, BPSK mapping of leading bytes of slots # 1 to # 12 (coding rate 1/2), in order from slot # 1 (excluding dummy slots) ), PSK mapping for 203 symbols and BPSK mapping for four symbols of the burst signal (coding rate ２) according to each modulation scheme of the main signal are repeated, and I and Q symbol streams are output.

[0008] The transmitter 2 orthogonally modulates the carrier with the I and Q symbol streams, and then performs frequency conversion and power amplification.
Transmission is performed from the transmission antenna 3. FIG. 17 shows a configuration example of a transmission frame after PSK modulation in the hierarchical transmission scheme.
On the other hand, the receiver 4 catches a transmission radio wave with the reception antenna 5 and performs RF amplification and frequency conversion with the reception circuit 6 to obtain an intermediate frequency signal of the reception signal. Then, the demodulation circuit 7 demodulates the I and Q symbol streams from the intermediate frequency signal by quadrature detection. And a decoder (transmission path decoder)
8, the procedure is completely opposite to that of the encoder 1 on the transmitting side.
PSK demapping, frame synchronization detection, superframe identification signal detection, TMCC decoding, inner code error correction,
Each process of deinterleaving, descrambling, and outer code error correction is performed to restore the original TS multiplex frame data. Then, a desired program data portion is extracted from the TS multiplexed frame data restored with reference to the TMCC information, and the image signal / audio signal is restored.

[0009]

As described above, in the hierarchical transmission system that allows a combination of different modulation systems and coding rates in one carrier frequency, even if the same program data is used,
The transmission quality differs depending on what combination of modulation scheme and coding rate is used for transmission. Same C / N
BPSK modulation (coding rate 1/2) <Q
PSK modulation (coding rate 1/2) <QPSK modulation (coding rate 2/3) <... <QPSK modulation (coding rate 7/8) <
The reception error amount increases in the order of TC8PSK modulation (coding rate 2/3). It is also known that even with the same combination of modulation scheme and coding rate, the reception error amount tends to increase in the first slot immediately after the combination of modulation scheme and coding rate changes from the immediately preceding slot. In addition, it is known that the reception error amount tends to increase in the first frame immediately after the transmission multiplex configuration has changed from the immediately preceding superframe.

However, by using the same method as the conventional reception error measurement system shown in FIG. 14, the transmitted TS multiplexed frame data and the received TS multiplexed frame data are collated mechanically on a bit basis, whereby the hierarchical transmission system is realized. When the reception error amount of the corresponding receiver is measured, the existence of a combination of different modulation schemes and coding rates in the TS multiplexed frame data is ignored, and the significance of the measured error amount becomes unclear. That is, even if the measured error amount is large, it cannot be said that the reception performance of the BPSK-modulated (coding rate 1/2) program data is poor, and even if the measured error amount is small, the TC8PSK modulation ( Coding rate 2 /
3) The reception performance of the performed program data is not good.
Furthermore, the presence or absence of an increase in reception errors in the first slot immediately after the combination of the modulation scheme and the coding rate changes from the immediately preceding slot, and the first frame immediately after the transmission multiplex configuration changes from the immediately preceding superframe. The presence or absence of an increase in reception errors cannot be accurately grasped.

It is an object of the present invention to provide a reception error measurement system capable of accurately grasping the reception performance of a receiver compatible with the hierarchical transmission system.

[0012]

In the reception error measuring system according to the first aspect of the present invention, a plurality of time slot data are multiplexed, and different combinations of the PSK modulation method and the coding rate are used for each time slot. A transmission signal in which the multiplexed frame data according to the permissible hierarchical transmission scheme is subjected to transmission path coding and PSK modulation is received / demodulated, decoded, and the original multiplexed frame data according to the hierarchical transmission scheme is restored and output. A reception error measurement system for the receiver (40), wherein the verification data storage means stores verification multiplexed frame data by a hierarchical transmission method in which predetermined verification data is assigned to time slot data. 11) and a multiplexed frame data output means for sequentially reading out and outputting the multiplexed frame data from the collation data storage means (11). (15) and, for each unit data of the multiplexed frame data for collation, measurement target position identification data indicating whether the unit data is a measurement target position, and a measurement target position assigned to the same frame configuration as the multiplexed frame data for collation. The multiplexed frame data output from the multiplexed frame data output means (15) and the multiplexed frame data output from the multiplexed frame data output means (15), which stores the multiplexed frame data for identification, are subjected to transmission path coding and PSK modulation to receive the measured object. Machine (4
0), and the data storage unit (1) for each unit data of the multiplexed frame data output from the receiver under test (40).
The detecting means (16) for detecting the corresponding data position in the data storage means (1) and the measurement target position identification data, and the detection means (16) of the measurement target position identification data storage means (14). A unit for comparing the data position detected by the detection unit (16) in the measurement object position identification data readout unit (14) for reading out the measurement target position identification data of the detected data position; Verification data reading means (11) for reading data for use, and measurement target position identification data read by measurement target position identification data reading means (14) among multiplexed frame data sequentially output from the measurement target receiver. Is compared with each unit collation data read by the collation data reading means (11) for each unit data indicating the measurement target position, The measurement to the measuring means (17), and comprising the.

According to the first aspect of the present invention, the multiplexed frame data for collation by the hierarchical transmission system in which predetermined collation data is allocated to the time slot data is stored in the collation data storage means (11). For each unit data of the multiplexed frame data for collation, the multiplexed frame for measurement target position identification, which is allocated to the same frame configuration as the multiplexed frame data for collation, The data is stored in the data storage means (14) for identifying the position to be measured. The multiplexed frame data is sequentially read out from the collation data storage means (11), and is subjected to transmission path coding and PSK modulation by the signal processing means (20, 30) and input to the receiver under measurement (40). For each unit data of the multiplexed frame data sequentially output from the receiver under measurement (40), the detection means (1
In 6), the corresponding data positions in the collation data storage means (11) and the measurement target position identification data storage means (14) are detected, and the measurement target position identification data reading means (14).
Then, the identification data and the unit collation data at the data position detected by the detection means (16) are read by the collation data reading means (11). Of the multiplexed frame data output from the receiver under test (16), the target position identification data read by the target position identification data reading means (14) is compared with each unit data indicating the target position. Data reading means (1
The error amount is measured by collating with each unit collation data read in 1).

In the hierarchical transmission system, the transmission quality of each independent data is allowed to differ, and each independent data unit is actually used by the receiver. on the other hand,
Even if the data are independent of each other, the transmission quality is the same if the combination of the modulation scheme and the coding rate is the same.
Therefore, if the reception error amount is measured for each combination of the modulation scheme and the coding rate, it becomes possible to measure the reception performance in accordance with the actual use situation of the receiver. Each time slot data constituting the multiplex frame data is a minimum unit in which a modulation scheme and a coding rate are determined. Therefore, when it is desired to know the reception performance of data transmitted by a combination of a certain modulation scheme and a coding rate, for example, the corresponding 1
By measuring the error amount for all or a part of one time slot, or measuring the error amount for all or a part of each time slot over a plurality of time slots, the desired reception can be accurately performed. The performance can be grasped.

Further, even with the same combination of the modulation scheme and the coding rate, the reception error amount is likely to increase in the first slot immediately after the combination of the modulation scheme and the coding rate changes from the immediately preceding slot. The reception error amount is likely to increase in the first slot of the first frame immediately after the transmission multiplex configuration changes from the superframe. Therefore, for example, all or some data of the first slot immediately after the change of the combination of the modulation scheme and the coding rate is extracted from the immediately preceding slot to measure the reception error amount, or the transmission multiplexing is performed from the immediately preceding superframe. By extracting all or part of the data corresponding to the combination of the desired modulation method and coding rate in the first frame immediately after the change in the configuration and measuring the reception error amount, the error can be reduced in the part where the error tends to increase. It is possible to accurately determine whether the amount has increased more than expected.

Also, for each unit data of the collation multiplex frame data, the measurement object position identification data indicating whether or not the data is the measurement object position is allocated to the same frame configuration as the collation multiplex frame data. The multiplexed frame data for measurement is stored in the multiplexed frame data storage means for identification of the target to be measured, and for each unit data of the multiplexed frame data output from the receiver under measurement, When indicating the position to be measured, the data is compared with the matching data stored at the corresponding data position in the matching data storage means. The reception error amount can be measured only for the target, and no complicated timing circuit is required.

According to a second aspect of the present invention, in the receiving error measuring system, the operation means for selecting the multiplexing structure of the multiplexed frame data for collation or the collation data to be assigned to each time slot data. (12) and a change unit (13) for changing the storage content of the comparison data storage unit (11) in accordance with the selection operation of the operation unit (12).

Thus, if the user performs an operation of multiplexing the multiplexed frame data for collation or selecting collation data to be allocated to each time slot data by the operation means (12), the collation data storage means (11 Since the stored contents of ()) are changed, it is also possible to perform error measurement in which the multiplex configuration or the collation data is arbitrarily changed.

According to a third aspect of the present invention, there is provided the reception error measuring system according to the first aspect, wherein the operation of selecting a measurement target position for the multiplexed frame data for collation stored in the collation data storage means (11) is performed. Operating means (12) to perform, and a change operation by the operating means (12),
Changing means (13) for changing the storage content of the data storage means (14) for identification of the measurement target position.

Thus, when the user performs an operation of selecting a measurement target position for the multiplexed frame data for verification stored in the verification data storage means (11) by the operation means (12), the measurement target position identification is performed according to the operation. Since the storage contents of the use data storage means (14) are changed, the reception error amount can be measured for an arbitrary specific portion in the multiplexed frame data. For example, 1 corresponding to a combination of a desired PSK modulation scheme and a coding rate in multiplexed frame data.
Or, it is easy to target a part or all of the data over a plurality of slots, or to target a part or all of the data of the slot immediately after the combination of the PSK modulation method and the coding rate is changed in the multiplexed frame data. Can be.

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

In claims 1 to 3 , the signal processing means comprises:
Either one or both of the noise level and the signal level of the PSK modulated signal obtained by transmission line encoding and PSK modulation of the multiplexed frame data may be adjustable.

[0030]

Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a schematic configuration of a reception error measurement system intended for a digital satellite TV broadcast receiver using a hierarchical transmission system. 10 repeatedly generates TS superimposed frame data SMD for 8 superframes (= 64 frames), extracts data of a desired specific part from the TS superimposed frame data RMD input from the receiver under test, and generates the data by itself. A reception error measuring device that measures a reception error amount by comparing the corresponding portion of the TS multiplexed frame data, and a signal processing device 20 that inputs the TS multiplexed frame data and performs transmission path coding, PSK modulation, frequency Performs conversion and outputs a PSK modulated signal. Reference numeral 30 denotes a pseudo C / N setting device.
The noise level and the signal level are arbitrarily adjusted by adding a variable level white noise to the SK modulated signal or by changing the level of the PSK modulated signal after adding the white noise, and then output the signal as a measurement signal. .

Reference numeral 40 denotes a receiver under measurement, which is a pseudo C /
The measurement signal input to the antenna terminal via the N setting device 30 is RF-amplified and converted into an intermediate frequency signal by the receiving circuit 41, and is quadrature-detected by the demodulation circuit 42 to perform PSK demodulation. Get. And
The transmission line is decoded by the decoder 43 to restore the original TS multiplex frame data. The reconstructed TS multiplexed frame data RMD is sequentially received in units of 1 byte.
Output to 0. Receiver circuit 4 of receiver under test 40
1. Due to the operation error of the demodulation circuit 42 and the decoder 43,
The restored TS multiplex frame data RMD is the TS multiplex frame data SMD generated by the reception error measurement device 10.
Does not exactly match. The restored TS multiplexed frame data RMD is delayed by a certain time from the TS multiplexed frame data SMD generated by the reception error measuring device 10.

In the reception error measuring apparatus 10, reference numeral 11 denotes the reference TS multiplex frame data RD (see FIG. 2) for eight superframes in which predetermined reference data is allocated to the main signal of each time slot data. A first memory for storing one byte per address in order from an address. In accordance with a user's multiplex configuration and selection operation of collation data on an operation panel 12, a controller 13 of a microcomputer configuration stores the first memory 11 in the first memory 11. The contents are changed by rewriting. Numeral 14 stores the TS multiplexed frame data TD for measurement target position identification for eight superframes to which measurement target position identification data indicating whether or not a measurement target position is assigned to the time slot data, one bit per address sequentially from the top address. The content of the second memory 14 is changed by rewriting by the controller 13 of the microcomputer in accordance with the operation of selecting the desired measurement target position with respect to the verification TS multiplex frame data RD on the operation panel 12. Is done.

Reference numeral 15 denotes the first super frame S of the reference TS multiplex frame data RD from the first memory 11 during measurement.
This is an output circuit that cyclically reads from F1 to the eighth superframe SF8 and sequentially outputs the SMD to the signal processing device 20 in byte units. The first memory 11 and the output circuit 15 constitute multiplexed frame data generating means for collation.

The reference TS multiplex frame data RD stored in the first memory 11 has substantially the same configuration as that of FIG. 15, but k bits from the 189th byte of each slot data.
The byte additional data includes an outer code error correction code. The first byte of slots # 1 to # 12 has been replaced with a frame synchronization signal, TMCC, and superframe identification signal. Each super frame SF1 to SF8
FIG. 3 shows an example (for one frame) of the verification TS multiplex frame data in the case where each has the same transmission multiplex configuration. Slots # 1 to # 24 of each verification TS multiplex frame data
Is for TC8PSK modulation (coding rate 2/3), slot #
25 to # 32 are for QPSK modulation (coding rate 3/4), and slots # 33 to # 40 are for QPSK modulation (coding rate 1 /
2) Slots # 41 to # 48 are for BPSK modulation (coding rate １ ／).

The assignment of the collation data to each time slot of the collation TS multiplex frame data RD is performed by, for example,
As shown in FIG. 2, a number “15 ₁₀ ” is assigned to the main signal data of all the time slots except the dummy slot of the superframe SF1 in units of one byte, and the main signal of all the time slots except the dummy slot of the superframe SF2 is allocated. A number “25 ₁₀ ” is assigned to data in units of 1 byte, a number “35 ₁₀ ” is assigned in units of 1 byte to main signal data of all time slots except the dummy slot of superframe SF3, and a dummy slot of superframe SF4 is assigned. The number “45 ₁₀ ” is assigned to the main signal data of all the time slots except for the dummy slot of the superframe SF5, and the number “55” is assigned to the main signal data of all the time slots except the dummy slot of the superframe SF5 in the unit of one byte.
₁₀ ", and the number" 65 ₁₀ "is assigned to the main signal data of all the time slots except the dummy slot of the superframe SF6 in 1-byte units, and the main signal data of all the time slots except the dummy slot of the superframe SF7. , A number “75 ₁₀ ” is assigned in units of 1 byte, and a number “85 ₁₀ ” is assigned in units of 1 byte to main signal data of all time slots except the dummy slot of the superframe SF8.

The TS multiplexed frame data TD for identification of the position to be measured stored in the second memory 14 indicates whether or not the unit data is the position to be measured for each byte of the multiplexed frame data RD for verification. The measurement target position identification data (flag data) is compared with the collation multiplex frame data RD
As shown in FIG. 4, each frame has 48 slot data # 1 to # 48 each composed of (188 + k) bits, as shown in FIG.

The assignment of the measurement target position identification data to each time slot of the measurement target position identification TS multiplexed frame data TD corresponds to one of the TDs corresponding to the measurement target position.
This is performed by setting the bit data to 1 ₂ and the 1-bit data corresponding to the non-measurement target position to 0 ₂ . For example, when it is desired to measure all the bits from the 2nd byte to the 188th byte in the slots # 25 to # 27 in all the superframes of the verification TS multiplex frame data RD in the first memory 11, TS for target position identification
# 25 to # of all frames of the multiplexed frame data TD
For the 27 slots, 1 ₂ is set from the 2nd bit to the 188th bit, and 0 ₂ is set for all other bits.

Numeral 16 denotes a data position detection circuit, which is used to check the TS multiplexed frame data RMD output from the receiver under test 40 in the first memory 11 for each data in byte units of the restored TS multiplexed frame data RMD. The corresponding data position in the data RD and the corresponding data position in the TS multiplexed frame data TD for measuring target position identification in the second memory 11 are detected, and the first and second readings are performed in the first memory 11 and the second memory 14. Output as addresses AD1 and AD2. Specifically, first and second read address counters are prepared separately for the first memory 11 and the second memory 14, and the numerical value of the main signal data of each time slot of the TS multiplexed frame data RMD is read, and the numerical value is read. "8
By detecting the timing that changed from “5” to “15”, the start timing of the first superframe is detected,
Initialize the first and second read address counters.

The first and second read address counters are incremented each time data is output from the receiver under measurement 40 in order of one byte at a time. The value of the first read address counter is the first read address AD
1 and the value of the second read address counter is output as the second read address AD2. First
When the first read address AD1 is input, the read control circuit (not shown) of the memory 11 reads and outputs the corresponding data of the collation TS multiplexed frame data RD in units of one byte, and outputs the read control signal (not shown) of the second memory 14. Upon input of the second read address AD2, the circuit reads and outputs the corresponding data in the TS multiplex frame data TD for measuring target position identification in bit units.

Reference numeral 12 denotes an operation panel for selecting a multiplex configuration of the reference TS multiplex frame data RD and selecting reference data to be assigned to each slot of the RD, and for selecting a desired measurement target for the reference TS multiplex frame data RD. Select a position or specify a measurement cycle. Reference numeral 13 denotes a controller having a microcomputer configuration. The controller 13 converts the multiplex configuration of the reference TS multiplex frame data RD selected on the operation panel 12 and the reference TS multiplex frame data RD having data contents corresponding to the reference data allocated to each slot of the RD. Generate first
Write to the memory 11. Also, depending on the measuring points for matching TS multiplex frame data RD selected by the operation panel 12, the same data structure as the collation TS multiplex frame data RD, the bit is 1 _second measuring points, the non-analyte T for position identification of the measurement object with the position bit set to 0 ₂
S-multiplexed frame data is generated and written to the second memory 14. Further, the measurement cycle selected on the operation panel 12 is set in a measurement circuit described later.

Reference numeral 17 denotes a measuring circuit, which has been restored by the receiver under test 40 in accordance with the condition selected by the operation panel 12.
A specific part of the S multiplex frame data, for which the measurement of the reception error amount is desired, is compared with a corresponding part of the TS multiplex frame data stored in the first memory 11 on a bit basis to determine whether a bit error has occurred. Detect and calculate the total number of bits of the measurement target, the number of error bits in the measurement target, and the number of error bits / total number of bits for each measurement period. Reference numeral 18 denotes a display for displaying the content measured by the measurement circuit 17.

FIG. 5 shows a specific configuration example of the measuring circuit 17. CLK is a clock synchronized with a 1-byte TS multiplexed frame data output from the receiver under measurement 40 and is generated by a timing circuit (not shown). 50
Takes a logical product of the measured position identification data and the CLK 1-bit units which are output from the second memory 14, the AND circuit for outputting only CLK when measured position identification data is 1 _2, 51 each measurement After the count value is initialized to zero at the start of the measurement cycle for each cycle, the AND circuit 50
Continue integrating the clock CLK' is time to 8 ₁₀ outputted from the integrating counter for measuring the total number of bits until the end of the measuring period once, 1 byte output from the first memory 11 is 52 Of the collation data and the data of 1 byte unit output from the receiver under test 40 are compared to see if the same bit position matches, and the number of mismatched bits is measured and output. Measurement circuit, 5
3 initializes the count value to zero at the start of the measurement cycle for each measurement cycle, and then outputs the clock C from the AND circuit 50.
This is an integration counter that integrates the output value of the mismatched bit number measurement circuit 52 every time LK ′ is output, and obtains the total number of error bits up to the end of one measurement cycle.

Reference numeral 54 denotes a measurement cycle T by the controller 13.
Is set, and when a measurement start command is received, CLK is counted from zero and timed, and when T is reached,
An arithmetic instruction is output to an arithmetic processing circuit to be described later, and subsequently, the integration counters 51 and 53 are temporarily cleared. Thereafter, the timer itself measures the time T again. Reference numeral 55 denotes an arithmetic processing circuit. The count values of the integration counters 52 and 54 at the timing of receiving the command are input, the number of error bits / total number of bits is calculated, the error rate for one measurement cycle is calculated, and the number of error bits / The total number of bits is displayed together with the number of error bits and the total number of bits.

Second memory 14, data position detection circuit 1
5. The measurement circuit 16 extracts the data of the desired specific portion from the multiplexed frame data restored by the receiver under measurement, and compares the extracted data with the corresponding portion of the multiplexed frame data generated by the multiplexed frame data generating means. Measuring means for measuring the error amount is configured.

The signal processing device 20 comprises an encoder (transmission path coding circuit) 21 and a transmitter 22. The encoder 21 receives a signal from the receiving error measuring device 10 during measurement.
When the S-multiplexed frame data SMD is input, scrambling is performed except for the first byte of each slot, and further, interleaving, inner code error correction addition, and BPSK (coding rate 1/2) mapping of the first byte of slots # 1 to # 12 are performed. , In order from slot # 1 (excluding dummy slots),
PSK for 203 symbols corresponding to each modulation method of main signal
Mapping and BPSK mapping for four symbols of a burst signal are repeated to generate I and Q symbol streams. After orthogonally modulating the carrier with the I and Q symbol streams, the transmitter 22 performs frequency conversion to a predetermined RF frequency and amplifies it to output a PSK modulated signal (see FIG. 17).

In the pseudo C / N setting device 30, reference numeral 31 denotes a white noise generator for generating white noise WN;
Is a level adjuster that varies the level of the white noise WN, 33 is an adder that adds the PSK modulated signal and the white noise WN, and 34 is a level that varies the level of the output signal of the adder 33 and outputs it as a measurement signal. It is a regulator. The noise level of the measurement signal can be set to a desired measurement condition by adjusting the level adjuster 32, and the level of the measurement signal can be set to the desired measurement condition by adjusting the level adjuster 34. Can be. The measurement signal output from the pseudo C / N setting device 30 is output to the receiver under measurement 40.

Next, the operation of the measurement system shown in FIG. 1 will be described. The noise level of the measurement signal and the signal level are adjusted to desired measurement conditions by adjusting the level adjusters 32 and 34 of the pseudo C / N setting device 30 in advance. (1) Measurement target: QPSK (coding rate 1/2) modulation part when the transmission multiplexing structure does not change in the middle Select the multiplexing structure as shown in FIG. Also, for each superframe, the main signal data of each slot of each frame is compared with the collation data "15 ₁₀ " as shown in FIG.
"25 ₁₀ ", "35 ₁₀ ", "45 ₁₀ ", "55 ₁₀ ",
When the allocation of “65 ₁₀ ”, “75 ₁₀ ”, and “85 ₁₀ ” is selected, the controller 13 generates the corresponding verification TS multiplex frame data RD and writes it to the first memory 11.

In the operation panel 12, as a measurement target position for the verification TS multiplex frame data RD, slot # 3 is set for every frame of all superframes.
When the second to 188th bytes of # 3, # 35, # 37, and # 39 are selected, the controller 13 has the same frame configuration as that of the RD, and, as shown in FIG. # 33, # 3
Only the second to 188th bits of # 5, # 37, and # 39 are set to 1 _2, and the other is set to 0 ₂ to generate TS multiplexed frame data TD for measurement target position identification, which is written to the second memory 14. . When, for example, 10 seconds is selected as the measurement cycle T on the operation panel 12, the controller 13 sets the timer 55 of the measurement circuit 17.

When a measurement start operation is performed on the operation panel 12, the controller 13 gives an output start command to the output circuit 15, and the output circuit 15 that has received the command outputs the reference TS multiplex frame data for 64 frames from the first memory 11. Is read cyclically, and output to the signal processing device 20 as an SMD in byte units. The signal processing device 20 performs channel coding, PSK modulation, frequency conversion and amplification, and performs a pseudo C / N setting device 30.
Output to The measurement signal adjusted to the desired noise level and signal level by the pseudo C / N setting device 30 is input to the antenna terminal of the receiver under measurement 40 and the reception circuit 41
The RF amplification and conversion to the intermediate frequency signal are performed. And
The demodulation circuit 42 demodulates the I and Q symbol streams from the intermediate frequency signal by quadrature detection. Further, the decoder 43 performs PSK demapping, frame synchronization detection, superframe identification signal detection, TMCC decoding,
Each process of inner code error correction, deinterleaving, descrambling, and outer code error correction is performed, and the original TS multiplex frame data is restored.
D is output in byte units.

The data position detection circuit 16 of the reception error measuring apparatus 10 detects the corresponding data position in the first memory 11 for each byte unit of the TS multiplexed frame data RMD output from the receiver under test 40. And
The read address AD1 is output to output the corresponding collation data from the first memory 11 to the measurement circuit 17 in 1-byte units. In parallel with this, the TS multiplexed frame data RMD output from the receiver 40 under measurement is output. , The corresponding data position in the second memory 14 is detected, the read address AD2 is output, and the corresponding measurement target position identification data is output from the second memory 14 as 1
Output to the measurement circuit 17 in bit units.

When the measurement start command is given by the controller 13, the timer 54 of the measurement circuit 17 clears the integration counters 51 and 53 once, counts the CLK, measures T, and starts the first measurement cycle. . The mismatch bit number measuring circuit 52 and the integrating counter 53
Each time the 1-bit measurement target position identification data output from the second memory 14 becomes “1 ₂ ”, the first memory 11
The total number of error bits in which the 1-byte unit of collation data output from the MPU and the 1-byte unit of the TS multiplexed frame data RMD output from the receiver under test 40 are collated in units of bits and are not matched _NE is required. Further, the total number of bits N _T collated by the mismatch bit number measuring circuit 52 and the integration counter 53 is obtained by the integration counter 51. The arithmetic processing circuit 55 includes a timer 54
Ends the timing of T, and when an operation command is given, BER
= N _E / N _T is calculated, and N _E , N _T , BE are displayed on the display 18.
Display R. When one measurement is completed in this way, the timer 54 clears the integration counters 51 and 53 once, then counts CLK and measures T again, so that the same processing is performed for the next measurement cycle. Repeated. Thus, the amount of reception error when receiving data transmitted by a combination of QPSK modulation and a coding rate of 1/2 can be determined.

If the measurement target is the QPSK (coding rate 3/4) modulation portion in FIG. 3, the operation panel 12 sets all the superframes as the measurement target positions for the verification TS multiplex frame data RD. For every frame,
When the second to 188th bytes of slots # 25 to # 27 and # 29 to # 31 are selected, the controller 13
Has the same data structure as RD, and for all the frames of the eight superframes, as shown in FIG.
188 from the second bit of # 25 to # 27 and # 29 to # 31
The bit data is set to 1 ₂ only for the bit and 0 for the other bits.
_The TS multiplexed frame data TD for measurement target position identification set to 2 is generated and written to the second memory 14. If measurement is performed in this state, the amount of reception error when data transmitted by a combination of QPSK modulation and a coding rate of 3/4 is received can be determined.

If the measurement target is the BPSK (coding rate 1/2) modulation portion in FIG. 3, the operation panel 12 sets all the superframes as the measurement target positions for the verification TS multiplex frame data RD. For every frame,
When the second to 188th bytes of the slots # 41 and # 45 are selected, the controller 13 has the same data configuration as that of the RD, and for all the frames of the eight superframes, as shown in FIG. Only the second to 188th bits of 45 are set to 1 _2, and the other is set to 0 ₂ to generate TS multiplexed frame data TD for identification of the position to be measured, which is written to the second memory 14. If measurement is performed in this state, the reception error amount when data transmitted by a combination of BPSK modulation and a coding rate of ２ is received can be determined.

If the object to be measured is the 8PSK (coding rate 2/3) modulated portion in FIG. 3, the operation panel 12 sets all the superframes as the positions to be measured with respect to the verification TS multiplex frame data RD. For every frame,
When the second to 188th bytes of the slots # 1 to # 24 are selected, the controller 13 has the same data configuration as that of the RD and has the slots # 1 to # 24 for all of the eight superframes as shown in FIG. Only the 2nd to 188th bits of 24 are set to 1 _2, and the others are set to 0 ₂
TS multiplexed frame data T for identifying the position to be measured
D is generated and written to the second memory 14. If measurement is performed in this state, the amount of reception error when data transmitted by a combination of 8PSK modulation and a coding rate of 2/3 is received can be determined.

In this way, the amount of reception error can be measured for each combination of the PSK modulation method and the coding rate. In the hierarchical transmission scheme, the transmission quality of each independent data is allowed to differ, and each independent data unit is actually used by the receiver. On the other hand, even if the data is independent of each other, the transmission quality is the same if the combination of the modulation scheme and the coding rate is the same. Therefore, if the reception error amount is measured for each combination of the modulation scheme and the coding rate, it becomes possible to measure the reception performance in accordance with the actual use situation of the receiver.

Note that even with the same combination of modulation scheme and coding rate, the amount of reception error tends to increase in the first slot immediately after the combination of modulation scheme and coding rate changes from the immediately preceding slot. Therefore, it is desirable to measure separately. (2) Measurement target: First slot portion immediately after switching to TC8PSK (coding rate 2/3) modulation in the case where the transmission multiplexing structure does not change in the middle Measurement on the verification TS multiplex frame data RD by the operation panel 12 The target position is 1 from the second byte of slot # 1 for all frames of all superframes.
Selecting 0 byte, the controller 13 is the same data structure as RD, for all the frames of eight superframes, as shown in FIG. 9, 10 bit from the second bit of the slot # 1 is all 1 ₂ Then, TS multiplexed frame data TD for identification of the position to be measured is set to 0 ₂ and written to the second memory 14. If the measurement is performed in this state, the reception error amount exceeds the expectation for the head portion of the first slot immediately after the change from the combination of the coding rate of 1/2 in BPSK modulation to the combination of the coding rate of 2/3 in TC8PSK modulation. It can be seen whether or not has become larger.

Similarly, when the second to tenth bytes of slot # 25 are selected as the measurement target position, Q
The reception error amount is found for the leading part of the first slot part immediately after the change to PSK (coding rate 2/3) modulation,
When the second to tenth bytes of slot position # 33 are selected as the measurement target position, QPSK (coding rate 1 /
2) The reception error amount is known for the first portion of the first slot portion immediately after the change to the modulation, and BPSK (coding rate 1/2) is obtained when the second to tenth bytes of the slot position # 41 are selected as the measurement target positions. The reception error amount can be determined for the head of the first slot immediately after the modulation.

Next, a case where the transmission multiplexing configuration changes in the middle will be described. When the transmission multiplex configuration changes on the way, the reception error amount tends to increase immediately after the change, particularly in the first superframe or the first frame. Therefore, it is desirable to measure this point separately. (3) Target: T immediately after the transmission multiplex configuration changes on the way
C8PSK (coding rate 2/3) modulation part The first to fourth of eight superframes on the operation panel 12
Each frame of the superframes SF1 to SF4 selects the same transmission configuration as in FIG. 3, and each frame of the fifth to eighth superframes SF5 to SF8 selects the configuration as shown in FIG. The data for use is selected in the same manner as in FIG. In FIG. 10, the slots # 1 to # 20 of the verification TS multiplex frame data RD are TC8P
For SK modulation (coding rate 2/3), slots # 21 to # 4
0 is for QPSK modulation (coding rate 1/2), slot # 4
1 to # 48 are for BPSK modulation (coding rate 1/2). The controller 13 generates the corresponding TS multiplexed frame data for comparison RD and writes it to the first memory 11.

On the operation panel 12, as the measurement target positions for the verification TS multiplex frame data RD, two of # 1 to # 20 of the first frame of the fifth super frame SF5 are set.
When the 188th byte to the 188th byte is selected, the controller 13 has the same data configuration as that of the RD and starts from the second bit of # 1 to # 20 of the first frame of the fifth superframe SF5 among the eight superframes. Only the 188th bit is set to 1 _2, and the rest is set to 0 ₂ to generate TS multiplexed frame data TD for measuring target position identification, and write it to the second memory 14 (see FIG. 11). When, for example, 10 seconds is selected as the measurement cycle T on the operation panel 12, the controller 13 sets the measurement circuit 17.

When a measurement start operation is performed on the operation panel 12, the controller 13 gives an output start command to the output circuit 15, and the output circuit 15 which has received the command outputs the reference TS multiplex frame data for 64 frames from the first memory 11. Is read cyclically, and output to the signal processing device 20 as an SMD in byte units. The signal processing device 20 performs channel coding, PSK modulation, frequency conversion, and amplification. The PSK modulated signal output from the signal processing device 20 is a pseudo C / N setting device 30.
After the noise level and the signal level have been adjusted, the signal is input to the receiver under test 40 as a measurement signal. The receiver under test 40 outputs the restored TS multiplexed frame data RMD to the reception error measuring device 10.

The data position detection circuit 16 of the reception error measuring device 10 detects the corresponding data position in the first memory 11 for each byte unit of the TS multiplexed frame data RMD output from the receiver under test 40. And
The read address AD1 is output to output the corresponding data from the first memory 11 to the measuring circuit 17 in byte units. In parallel with this, each of the TS multiplexed frame data RMD output from the receiver under test 40 is output. For the data in byte units, the corresponding data position in the second memory 14 is detected, the read address AD2 is output, and the corresponding data from the second memory 14 is measured in 1-bit units in the
7 is output.

When the measuring cycle T starts, the measuring circuit 17
Every time the 1-bit unit measurement target position identification data input from the second memory 14 becomes “1 ₂ ”, the 1-byte unit verification data input from the first memory 11 and the receiver under test 40 simultaneously. Is collated on a bit-by-bit basis with data in 1-byte units input from. Then, the total number of bits N _T collated with the total number of error bits N _E that did not match is counted from zero. Then, when T has elapsed, BER = N _E / N _T is calculated, and the display 18 displays N _E , N _T , and BER. When one measurement is completed, the same processing is repeated again for the next T period. As a result, is the reception error amount larger than expected when receiving data transmitted by the combination of TC8PSK and the coding rate of 2/3 in the first superframe immediately after the transmission multiplex configuration has changed halfway? I understand whether or not.

Note that the same reference TS multiplex frame data RD as in (3) is selected, and # 25, # 27, and # 27 of the first frame of the fifth superframe SF5 are selected as measurement target positions for the reference TS multiplex frame data RD. # 29, #
When the second to 188th bytes of # 31, # 33, # 35, # 37, and # 39 are selected, the controller 13
Has the same data structure as RD, and among the eight superframes, # 25, # 27, # 29, # 31, # 33, # 35, # of the first frame in the fifth superframe SF5
Only the second bit to the 188th bit of 37 and # 39 are set to 1 _2, and the other bits are set to 0 _2.
The S-multiplexed frame data TD is generated and written to the second memory 14 (see FIG. 12). If measurement is performed in this state, QPSK in the first frame in the first superframe immediately after the transmission multiplex configuration changes in the middle, coding rate 1/2
It can be determined whether or not the reception error amount at the time of receiving the data transmitted by the combination is larger than expected.

Also, the same reference TS multiplex frame data RD as in (3) is selected, and the measurement target position for the reference TS multiplex frame data RD is set as the measurement target position of # 41 and # 45 of the first frame of the fifth superframe SF5. When the second to 188th bytes are selected, the controller 13
Has the same data configuration as RD, and among the eight superframes, the second to 188th bits of # 41 and # 45 of the first frame of the fifth superframe SF5 are all set to 1 _2, and the other are set to 0 ₂ TS for identifying target position
The multiplex frame data TD is generated and written into the second memory 14 (see FIG. 13). If measurement is performed in this state, reception when data transmitted by a combination of BPSK and a coding rate of で in the first frame of the first superframe immediately after the transmission multiplex configuration is changed halfway is received. It is determined whether the error amount is larger than expected.

In the above-described embodiment, in order to be able to detect the start timing of the first superframe, the measurement data allocated to the main signal of each superframe is represented by numerical values “15 ₁₀ ” and “25 ₁₀ ”. , "35 ₁₀ ",
"45 ₁₀ ", "55 ₁₀ ", "65 ₁₀ ", "75 ₁₀ ",
“85 ₁₀ ”, but this is only an example.
Different numerical values may be assigned to all four frames, or through 64 frames, from the first bit of the second byte of the first slot of the first frame to the last bit of the last slot of the last 64th frame in the 188th byte (on the way,
A predetermined M-sequence PN code is assigned to the dummy slot, the leading byte portion and the additional data portion of each slot). Position detection circuit 16
Alternatively, the start timing of the first superframe may be detected by capturing a fixed pattern having a length of 1000 bits after the second byte of the first slot of the first superframe.

Further, the transmitter 22 of the signal processing device 20
After the SK modulation, the frequency is converted to the RF frequency. However, the frequency is converted to the IF frequency, and the pseudo C / N
The output of the setting device 30 is used as the demodulation circuit 42 of the receiver under measurement.
, The measurement of the reception error amount may be performed.

[0067]

According to the present invention, the reception error amount is measured for each combination of the modulation scheme and the coding rate, or only the portion immediately after the combination of the modulation scheme and the coding rate is changed to extract the reception error quantity. , Or by extracting only the portion immediately after the change of the transmission multiplex configuration and measuring the reception error amount, it is possible to measure the reception performance according to the actual use situation of the receiver.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a reception error measurement system according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram of storage contents of a first memory in FIG. 1;

FIG. 3 is an explanatory diagram showing an example of TS multiplexed frame data for verification.

FIG. 4 is an explanatory diagram showing an example of TS multiplexed frame data for measuring target position identification.

FIG. 5 is a block diagram illustrating a specific configuration example of a measurement circuit.

FIG. 6 is an explanatory diagram showing an example of TS multiplex frame data for measurement target position identification.

FIG. 7 is an explanatory diagram showing an example of TS multiplexed frame data for measuring target position identification.

FIG. 8 is an explanatory view showing an example of TS multiplexed frame data for measuring target position identification.

FIG. 9 is an explanatory diagram showing an example of TS multiplexed frame data for measuring target position identification.

FIG. 10 is an explanatory diagram showing an example of TS multiplexed frame data for verification.

FIG. 11 is an explanatory diagram illustrating an example of TS multiplexed frame data for measuring target position identification.

FIG. 12 is an explanatory diagram showing an example of TS multiplex frame data for measuring target position identification.

FIG. 13 is an explanatory diagram showing an example of TS multiplex frame data for measuring target position identification.

FIG. 14 is an explanatory diagram of a conventional reception error measurement method.

FIG. 15 is an explanatory diagram of TS multiplexed frame data according to the hierarchical transmission scheme.

FIG. 16 is an explanatory diagram of a transmission / reception system using a hierarchical transmission scheme.

FIG. 17 is an explanatory diagram showing a configuration example of a transmission frame after PSK modulation.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 reception error measuring device 11 first memory 12 operation panel 13 controller 14 second memory 15 output circuit 16 data position detecting circuit 17 measuring circuit 18 display 20 signal processing device 30 pseudo C / N setting device 40 receiver to be measured

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Kenichi Shiraishi 1-14-6 Dogenzaka, Shibuya-ku, Tokyo stock inside Kenwood Corporation (72) Inventor Soichi Shinshiro 1-14-6 Dogenzaka, Shibuya-ku Tokyo (56) References JP-A-11-196058 (JP, A) “Demonstration experiment of BS digital broadcasting transmission system”, IEICE Technical Report, February 19, 1998, Vol. 97, No. 555, p35-p39

Claims (3)

(57) [Claims] 1. A multiplexed frame data composed of a plurality of time slot data and multiplexed frame data by a hierarchical transmission scheme in which a combination of a PSK modulation scheme and a coding rate that are different for each time slot is allowed is transmitted. A reception error measurement system for a receiver that receives and demodulates a modulated transmission signal, decodes the decoded transmission signal, restores the multiplexed frame data according to the original hierarchical transmission method, and outputs the data. And a multiplexed frame data output means for sequentially reading out and outputting the multiplexed frame data from the collated data storage means, wherein the multiplexed frame data is stored in the hierarchical transmission system in which predetermined data for comparison are assigned to the multiplexed frame data. Indicates whether or not the unit data is the position to be measured for each unit data of the multiplexed frame data for comparison. Measurement target position identification data storage means storing the measurement target position identification multiplex frame data in which the measurement target position identification data is allocated to the same frame configuration as the collation multiplex frame data, and the multiplex output from the multiplex frame data output means. Signal processing means for transmitting frame coding and PSK modulation to input to the receiver under test; and data storage means for verification for each unit data of the multiplexed frame data output from the receiver under test. Detecting means for detecting a corresponding data position in the target position identification data storage means; and a measurement target position for reading the measurement target position identification data of the data position detected by the detection means in the measurement target position identification data storage means. The identification data readout means and the data position detected by the detection means in the collation data storage means. A collation data reading means for reading the position collation data; and a measurement target position identification data read out by the measurement target position identification data reading means of the multiplexed frame data output from the measurement target receiver. Measuring means for measuring an error amount by comparing each of the unit data shown with each of the unit matching data read by the matching data reading means. 2. An operation unit for selecting a multiplex configuration of multiplexed frame data for comparison or collation data to be assigned to each time slot data, and changing the storage content of the collation data storage unit according to the selection operation by the operation unit. 2. The reception error measuring system according to claim 1, further comprising: a change unit configured to perform the change. 3. An operation means for selecting a measurement target position with respect to the multiplexed frame data for verification stored in the data storage means for verification, and storing the data storage means for identification of the measurement target position in accordance with a change operation by the operation means. 2. The receiving error measuring system according to claim 1, further comprising: changing means for changing contents.