JP2995757B2 - Adaptive equalizer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive equalizer that adaptively equalizes a transmission path whose characteristics are unknown or fluctuates with time using a non-recursive digital filter.

[Prior Art] FIG. 5 shows a conventional adaptive equalizer of this kind. Digital input signal X _K input from the signal input terminal 1, the shift register circuit 21 that operates according to the data clock input from the data clock input terminal 4, the variable coefficient circuit
Acyclic digital filter consisting of 22 and adder 23
Is approximated equalized with transmission line 10, is input as an output Y _K to the amplitude value determination circuit 12. The amplitude value determining circuit 12, the output Y _K of the digital filter 10 is binarized by a predetermined threshold value, and outputs the decision value output terminal 2 as a digital pulse signal transmitted to the determination value _K.

The judgment value _K is input to the coefficient control circuit 9 via the switch 19. In this coefficient control circuit 9,
The determination value _K, after A / D conversion by the D / A conversion circuit 25, obtains a difference between the converted value and the filter output Y _K at summing circuit 26, and outputs the difference e _K to the delay circuit 27 . On the other hand, the judgment value
_K is input to the shift register circuit 51, and the multiplication circuits 29, 3
After being multiplied by the error e _K from the delay circuit 27 at 0,31, it is accumulated in the accumulation circuit 32, 33. The accumulated value is provided to the variable coefficient circuit 22 as an output of the coefficient control circuit 9.

On the other hand, in this circuit, in order to control the coefficient of the acyclic digital filter 10 having the variable coefficient parameter, the training pulse generation circuit 18 is used especially in the initial coefficient value convergence process.
And by connecting this to the coefficient control circuit 9 by switching the switch 19, a method of quickly and reliably converging the coefficient value is adopted.

Various adaptive algorithms for adjusting the coefficient parameter are known. In the case of FIG. 5, the absolute value of the intersymbol interference is obtained as an evaluation function indicating the goodness of the filter approximation. In order to minimize the coefficient, the coefficient parameter is sequentially corrected by the maximum gradient method. The modification algorithm of the coefficient C _{j at} the m-th time is as follows.

Here, alpha is corrected gain, _Kj is the difference between the output value Y _K D / A conversion value and the digital filter 10 minutes just past determination value, e _K is determined value _K j. During training, a training pulse generation circuit is used as the determination value _K.
An output value _K of 18 is used.

The configuration shown in FIG. 5 is a so-called ZF method, but the algorithm for coefficient parameter correction is not limited to this, and the LMS method or another correction algorithm may be used.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional adaptive equalization circuit, it is necessary to have a dedicated training pulse generation circuit in a form completely independent of the equalizer, and the system configuration Due to the high exclusiveness, there is a problem that the adaptive algorithm for sequentially correcting the coefficient parameters cannot be easily changed.

The present invention has been made in view of such a problem, and has as its object to provide an adaptive equalizer that does not need to include a dedicated training pulse generation circuit and that can easily change an adaptive algorithm.

[Means for Solving the Problems] An adaptive equalizer according to the present invention is an adaptive equalizer that adaptively approximates a transmission path by a non-recursive digital filter having a variable coefficient parameter. A judgment circuit for judging the amplitude value of the output, a shift register for holding the output of the judgment circuit, and selecting one of the output of the judgment circuit and the output of the last stage of the shift register; A first data select circuit for outputting one of the input data to each stage of the shift register, a plurality of second data select circuits for selecting one of input data to each stage of the shift register, and an output of the digital filter. And a coefficient control circuit for controlling a coefficient value and an output value of the digital filter with the input of the output of each of the second data select circuits as inputs. The shift register includes a plurality of storage circuits that can be preset as initial values, and sequentially shifts data in each storage circuit in a fixed direction in synchronization with a data clock.

Note that the shift register is constituted by, for example, a plurality of storage circuits that can be preset as initial values,
A device for sequentially moving data of each storage circuit in a fixed direction in synchronization with a data clock is provided.

[Operation] In the present invention, a training pulse is generated by a preset value of a shift register, the training pulse is circulated through a first data select circuit, and the training pulse is selected by a second data select circuit. Then, by giving the result to the coefficient control circuit, the operation at the time of training can be performed. Further, by selecting the output of the determination circuit by the first data select circuit, it becomes possible to selectively output the determination value at an arbitrary timing to the coefficient control circuit via the second data select circuit.

Thus, according to the present invention, a special circuit for generating a training pulse is not required, and the data of the first data select circuit and the selection value of the second data select circuit are changed with respect to the change of the adaptive algorithm. Is set arbitrarily, the modularity of the coefficient control circuit is enhanced, the versatility of the system is improved, and the system can be flexibly adapted to changes in the system.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of the adaptive equalizer according to the first embodiment of the present invention.

Digital input signal X _K input from signal input terminal 1
Is an n-stage shift register circuit 2 that operates according to the data clock input from the data clock input terminal 4.
1, which is input to a non-recursive digital filter 10 including a tap coefficient circuit 22 and an addition circuit 23. Output Y _K of the digital filter 10 is inputted to the amplitude value determining circuit 12. Amplitude determining circuit 12, the output Y _K of the digital filter 10 is binarized by a predetermined threshold value, and outputs the determination value _K from the decision value output terminal 2.

Further, the determination value _K is input to the input terminal B of the data select circuit 14. The output of the data select circuit 14 is input to a shift register circuit 13 including a P-stage presettable storage circuit 24. The output delayed by P stages by the shift register circuit 13 is fed back to the input terminal A of the data select circuit 14.

Which of the terminals A and B is to be selected is determined by a mode selection signal supplied from the mode selection signal input terminal 3 to the selection terminal S of the data selection circuit 14.

The output of each stage of the shift register circuit 13 are respectively input to the P number of input terminals A ₁ to A _P of M data select circuit 15 ₁ to 15 _M. Among the data select circuit 15 ₁ to 15 _M each input terminal A ₁ to A _P of, the choice of which terminals is determined by the selection signal input to the data select circuit select signal input terminal 5 ₁ to 5 _M .

Then, the output of the data select circuit 15 ₁ to 15 _M output and nonrecursive digital filter 10 is input to the coefficient control circuit 9.

Next, the operation of the adaptive equalizer according to the present embodiment configured as described above will be described.

In this circuit, a training operation mode for performing initial training for convergence of coefficient parameters and a determination reference operation mode for determining actual received data can be selected by an input signal to the mode selection signal input terminal 3.

In training operation mode, the shift register circuit
The preset data circulates through P13 at a period P times the period of the data clock input to the data clock signal input terminal 4. Therefore, the data select circuit 15 _i (i
= 1 to M; the same applies hereinafter) to the input terminals A _{1 to} A _P , the data of the training pulse values a _{K to} a _{K-P + 1} are continuously input while being shifted one by one. In the data select circuit 15 _i ,
Was selected by the selection signal input from the connected data select circuit select signal input terminal 5 _i to the input data bus _Pi required register values in each stage, and outputs the desired register values.

On the other hand, in the judgment reference operation mode, the output of the judgment circuit 12
_K is input to the shift register circuit 13, and the past data _K to _{K-P + 1} for P stages of sequentially input data are held. Thereafter, the same operation as during the training operation is performed. Any data among the outputs _K to _{K-P + 1} of _i is output. That is, the data select circuit 15
The output value of _i is as follows.

In training operation mode a _{Kl + 1} (l = _{1 to} P) In judgment reference operation mode _{K-l + 1} (l = _{1 to} P) (where l is selected by _Pi bus input of input terminal 5 _i ) Coefficient control In the circuit 9, these data select circuits 15
_1-15 on the basis of the output Y _K of the output data and the digital filter 10 of the _M, and controls the coefficient parameter and the output value of the digital filter 10.

FIG. 2 is a timing chart showing the operation of the adaptive equalizer of FIG.

Filter input waveform X _K is processed by the digital filter 10, is equalized as the filter output waveform Y _K. The output Y _K is determined then by the decision circuit 12, as a determination value _K binarized as shown.

In training operation mode, shift register 13
The expected value of _K will be preset. Therefore, the input A ₁ (l = 1~P) of each data select circuit 15 ₁ to 15 _M, the digital data for each sample as shown are sequentially inputted. In the training operation mode, data is repeatedly input at a period of P samples.

In the judgment reference mode, the data _{K-P + 1} from the successively input _K to P samples before are input to the data select circuit 15 _i.
Will be entered. This data select circuit 15 _i
Then, if necessary, any one of the data _K to _{K-P + 1} is selected from the input terminal 5 _{i at} an arbitrary timing as shown in the figure, and the data select circuit 15 _i selects the data in synchronization with the timing. Data is output. Therefore, according to the selection signal from the input data bus _Pi , the data a _K
~a _{K-P + 1} (or _{K ~ K-P + 1)} is selected at any time, will be input to the coefficient control circuit 9.

FIG. 3 is a diagram showing a second embodiment of the present invention. This embodiment shows an example of a system configuration of the so-called ZF method, similar to the adaptive equalizer shown in FIG. 5 shown as a conventional example. In the basic configuration shown in FIG. FIG.

The coefficient control circuit 9 corresponds to the shift register 51 shown in FIG.
Is replaced by a demultiplexer circuit 28,
Other configurations are the same as those of the coefficient control circuit 9 in FIG.

In the adaptive equalizer, the data select circuit 15 ₁
But select signal as output at all times a _K (or a _K) is applied to the input terminal 5 _1. On the other hand, the data from the select circuit 15 _{2, a K, a K-1} , a K-2 ( or _{K, K-1, K-} 2) selection signal as continuously outputs within one sample time There is applied to the input terminal 5 _2. Thereby, the data select circuit
15 _second output, i.e., the input of the demultiplexer circuit 28,
Three serially multiplexed data are supplied. In the coefficient control circuit 9, based on these data, the multiplexed data is returned to the parameters by the demultiplexer circuit 28, and the same calculation as in the related art is executed.

FIG. 4 is a diagram showing a configuration of an adaptive equalizer according to a third embodiment of the present invention.

This system configuration uses a decision feedback equalizer, so-called DF
The coefficient control circuit 9 is provided with a coefficient judgment feedback filter section including demultiplexer circuits 42 and 43, tap coefficient circuits 44, 45 and 46, and an addition circuit 47. Further, this coefficient control circuit 9, and the error e _K from the addition circuit 26, multiplication circuit 41 for multiplying the output multiplexed data select circuit 15 ₂ is provided. Multiplication circuit 41
The output of as inputs of the demultiplexer circuit 42, also, the output of the data select circuit 15 ₂ is given as the input of the demultiplexer circuit 43.

On the other hand, the digital filter 10, and the error e _K from the addition circuit 26, of each stage of the cysts register circuit 21 data X
A multiplication circuit 48 for multiplying _{K + i} (i = 0, 1, 2) is provided. Further, an addition circuit 17 for adding the output W _K of the digital filter 10 and the output of the coefficient determination feedback filter is provided, and the addition result is used as a filter output Y _K.

In this embodiment, the filter output Y _K, the coefficient of the coefficient C _i and decision feedback filter portion of the digital filter 10 d
_j is given by the following equation.

Here, alpha, beta is corrected gain, _j past decision value for the number of the j, e _K is the difference between the D / A conversion value and the digital filter output values Y _K determination value _K, C _i is the digital Filter 10
And _dj are coefficients of the decision feedback filter unit. In addition,
The training mode, using the training value a _K as determined value a _K.

In the present system configuration, an addition circuit 17 is added to the output section of the digital filter 10 to provide a filter configuration having a feedback loop.

[Effects of the Invention] As described above, according to the present invention, a training pulse generation function is provided in advance as an adaptive equalizer, and a training value or a determination value at an arbitrary timing is selectively output by a data select circuit. This eliminates the need for a new training pulse generation circuit, increases the modularity of the coefficient control circuit, improves the versatility of the system, and can flexibly adapt to system changes and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram of an adaptive equalizer according to a first embodiment of the present invention, FIG. 2 is an operation waveform diagram of the adaptive equalizer, and FIG. 3 is a diagram according to a second embodiment of the present invention. Block diagram of an adaptive equalizer,
FIG. 4 is a block diagram of an adaptive equalizer according to a third embodiment of the present invention, and FIG. 5 is a block diagram of a conventional adaptive equalizer. 1; signal input terminal, 2; judgment value output terminal, 3; mode selection signal input terminal, 4; data clock signal input terminal, 5 _{1 to} 5 _M ; data select circuit selection signal input terminal, 10; acyclic digital filter , 12; amplitude value judgment circuit, 13, 21; shift register circuit, 14, 15 ₁ to 15 _M ; data select circuit, 22, 44
~ 46; Tap coefficient circuit, 17, 23, 26, 47; Addition circuit, 24; Storage circuit, 25; D / A conversion circuit, 27; Delay circuit, 28, 42, 43; Demultiplexer circuit, 29 to 31, 41,48; Multiplication circuit, 32-34; Accumulation circuit

Claims (1)

(57) [Claims] 1. An adaptive equalizer for adaptively and approximately equalizing a transmission path by a non-recursive digital filter having a variable coefficient parameter, a determination circuit for determining an amplitude value of an output of the digital filter, and the determination circuit. And a first data select for selecting one of the output of the determination circuit and the output of the last stage of the shift register, and outputting the selected output to the first stage of the shift register. A circuit, a plurality of second data select circuits for selecting one of input data to each stage of the shift register, and an output of the digital filter and an output of each of the second data select circuits. And a coefficient control circuit for controlling a coefficient value and an output value of the digital filter, wherein the shift register has a preset value as an initial stage value. Tsu is constituted by preparative possible plurality of memory circuits, adaptive equalizer, characterized in that is to move in synchronism with the data clock data sequentially in a constant direction of the storage circuit.