JP2994873B2 - Reference voltage generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit for compensating for temperature dependency, and more particularly to a reference voltage generating circuit formed by CMOS technology.

[0002]

2. Description of the Related Art Recently, as a reference voltage generating circuit often used for a semiconductor integrated circuit, a bandgap voltage (an intrinsic voltage of a substance at an absolute zero degree, 1.20 in the case of Si).
5 V, and about 0.7 V at room temperature). Particularly, in a semiconductor integrated circuit using CMOS technology, for example, a reference voltage generating circuit shown in FIG. 4 is well known as the most basic circuit in which a MOS field effect transistor is converted to a lateral bipolar transistor. "IEEE JOURNAL OF SOL
ID STATE CIRCUIT, VOL. SC-1
8, NO. 3 pp. 278, June 1983 ".

The structure shown in FIG. 4 is a P-channel MOS transistor Q of the same size connected to a power supply voltage Vdd.
_1, Q ₂ is mirror - connected current mirror - constitute a circuit, the current mirror - NPN drain of the output-side P-channel MOS transistor to Q ₁ circuit through the resistor R _1, R ₂ connected in series Baipo - is connected to the collector of La transistor Q _3, the NPN Baipo - the emitter of La transistor Q ₃ are being connected to the ground voltage Vss, its base - the scan is connected to a connection point of the resistors R _1, R ₂ .

On the other hand the current mirror - the drain of the reference-side P-channel MOS transistor Q ₂ of the circuit is NPN Baipo - is connected to the collector of La transistor Q _4, the NPN
Baipo - emitter of La transistor Q ₄ is ground voltage Vs
is connected to the s, the base - scan is the NPN Baipo - intended to be connected to the collector of La transistor Q _3,
Reference voltage V _REF is outputted from the drain of the P-channel MOS transistor Q ₁ to the output terminal (1).

[0005] Here, the NPN Baipo - emitter area of La transistor Q ₄ are, the NPN Baipo - and is set to K times the emitter area of La transistor Q _3. In the reference voltage generation circuit based on the configuration described above,
Now NPN Baipo - La transistor Q ₃ of the base - the scan-emitter voltage is V _BE3, resistor R ₁ connected in series, R ₂
Are defined as R ₁ and R ₂ respectively, and the reference voltage V _REF generated under the condition that the base current flowing through the NPN bipolar transistors Q ₃ and Q ₄ is ignored is V _REF = V _BE3 + (R _{1 / R 2) · (kT /} q) · l n K ( that given by 1) are known. Here, k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge. That is, in this circuit, the NPN bipolar transistor Q ₃
The voltage V _BE3 generated between the base and the emitter is used. Since V _BE3 has a negative temperature coefficient, it is expressed by the following equation.

[0006] _{V BE3 = V go -αT (2} ) where, V _go the band gap voltage of the Si at the absolute zero, α is the temperature coefficient. Wherein the (2) equation V _REF3 = V _go + by substituting the equation (1) to _{{(R 1 / R 2)} · (k / q) · l n K-α} · T (3) Becomes Here, the absolute temperature T in the second term of the above equation (3)
If the values of R ₁ , R ₂ and K are set so that the coefficient of V _REF becomes zero, the temperature coefficient of V _REF becomes zero and the bandgap voltage V
Nearly complete temperature compensation can be achieved by canceling out the negative temperature coefficient of _BE3 . Accordingly, the reference voltage V _REF generated at this time does not have the temperature dependency and the power supply voltage Vdd dependency, and the bandgap voltage V _go (= 1.20)
5V).

In this circuit, assuming that the threshold voltages of the P-channel MOS transistors Q ₁ and Q ₂ constituting the current mirror circuit are Vtp (approximately 1.0 V), the reference voltage V _REF is equal to the band gap voltage V _Assuming that the minimum operating power supply voltage required to generate _go is V _MIN ,
_MIN is theoretically expressed by the following equation. V _MIN = V _REF + Vtp = 2.205 V (4) Accordingly, the reference voltage generating circuit having the above-described configuration can be replaced with a CMOS IC having a power supply voltage Vdd specification of 3 V to 5 V, for example.
, A stable reference voltage V _REF can be obtained.

[0008]

However, in the reference voltage generating circuit based on the above configuration, since there is no bias circuit directly supplied from the power supply, the power supply voltage Vdd
The operation of the current mirror circuit is not guaranteed depending on the method of turning on the power supply.
Even though the voltage is sufficiently higher than _MIN (for example, 5 V), the current mirror circuit does not operate, so that the NPN
Since the bipolar transistors Q ₃ and Q ₄ are not turned on, a problem occurs that the reference voltage V _REF is not generated and the ground voltage Vss level is maintained.

This phenomenon will be described separately for the following cases. When the power supply voltage Vdd rises sharply: this is normal
Power supply voltage Vdd (for example, 5 V)
This is the case when throwing. In this case, as shown in FIG.
P-channel MO constituting the reference side of the current mirror circuit
S transistor Q_TwoDue to the capacitance C parasitic on the drain of
The drain of the P-channel MOS transistor
It does not follow the rise of the source voltage Vdd,
Channel MOS transistor Q_TwoBetween source and drain
Causes a potential difference equal to the power supply voltage Vdd. The P-chan
Flannel MOS transistor Q_TwoIs diode connected
Therefore, this potential difference is directly applied to the source-gate voltage V.
gs, and Vgs> Vtp is established and turned on. this
The P-channel MOS transistor on the output side of the current mirror circuit
Transistor Q₁Turns on, which causes the NPN bipolar
Transistor Q_Three, Q_FourOf the P-channel MO
S transistor Q₁Biased by current supplied from
Turns on, the circuit operates normally, and the reference
Pressure V_REFIs the bandgap voltage V_goBecomes Power supply voltage Vdd gradually rises from ground voltage Vss
Case: the reference side of the current mirror circuit shown in FIG.
P-channel MOS transistor Q_TwoOn the drain of
The parasitic capacitance C is charged by the leakage current,
Since the source voltage Vdd follows the rise, the P channel
Flannel MOS transistor Q _TwoSource-gate voltage V
gs, Vgs> Vtp does not hold and the P channel
MOS transistor Q_TwoMaintain the off state. This
As a result, the P channel constituting the output side of the current mirror circuit is
Flannel MOS transistor Q₁Also keep the off state
And the current mirror circuit does not operate.
Bipolar transistor Q_Three, Q_FourBase is biased
It is turned off.

Therefore, even when the power supply voltage Vdd rises to a voltage (for example, 5 V) sufficiently higher than the above-mentioned minimum operation power supply voltage _{VMIN, the} reference voltage _VREF is not generated, and the ground voltage Vs
The state is maintained with the s level. For this reason, when this reference voltage generation circuit is incorporated in the power supply voltage detection circuit, and when the power supply voltage Vdd gradually rises from the ground voltage Vss, the reference voltage generation circuit does not operate and the reference voltage _VREF is not applied. A change in the power supply voltage Vdd cannot be detected based on the comparison, causing a problem that the system malfunctions.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a reference voltage generation circuit that guarantees the operation even when the power supply voltage Vdd gradually rises from the ground voltage Vss.

[0012]

According to the present invention, a power supply voltage Vdd and a ground voltage Vss are provided in a conventional reference voltage generating circuit.
Series connected current limiting resistor R ₃ and diode between - de D _1, a series circuit consisting of D _2, anode - de side the resistor R
₃ and the diode - connected to a connection point of the de D _1, cathode - diode de side connected to the output terminal (1) - Star composed de D ₃ - up comprising the circuit (2) It is assumed that.

[0013]

SUMMARY OF] According to the above means, the power supply voltage if Vdd is gradually increased from the ground voltage Vss, the current mirror - in a state in which the circuit does not operate, the resistor R ₃ and diodes connected to the power supply voltage Vdd - de D It becomes possible to supply a current to the output side of the reference voltage generating circuit via ₃ . As a result, the NPN bipolar transistors Q ₃ and Q ₄ are turned on as the power supply voltage Vdd rises, and the drain (= gate) of the P-channel MOS transistor Q ₂ constituting the reference side of the current mirror circuit is grounded. It acts to lower the voltage to the level of Vss. Therefore, the P-channel MOS transistor Q ₂ is turned on, a current mirror receives this - P-channel MOS transistor Q ₁ constituting the output side of the circuit will be turned on, a current mirror - is possible to operate the circuit It becomes possible. Therefore, the power supply voltage Vdd is equal to the ground voltage Vss.
It is possible to guarantee the operation of the reference voltage generation circuit even when the voltage gradually rises from

[0014]

An embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing a reference voltage generation circuit according to an embodiment of the present invention. In FIG. 1, components denoted by the same reference numerals as those in FIG. 4 indicate the same components. The difference from the conventional example relating to the configuration of the reference voltage generation circuit of the present invention is that a start-up circuit (2) for guaranteeing the operation of the reference voltage generation circuit even when the power supply voltage Vdd gradually rises is provided. It is in.

[0015] The static - up configuration of the circuit (2) is as shown in FIG. 1, the power supply voltage Vdd and connected in series between the ground voltage Vss by a resistor R ₃ and diodes - a series circuit comprising a de D _1, D ₂ , anode - the de side and the resistor R ₃ diodes -
Is connected to the connection point of the de D _1, cathode - diode de side connected to the output terminal (1) of the reference voltage generating circuit - but are composed of de D _3, other configurations are configured the same as the conventional example Is a reference voltage generating circuit.

FIG. 2 is a characteristic diagram showing the dependency of the reference voltage V _REF generated in the reference voltage generating circuit according to the present invention shown in FIG. 1 on the power supply voltage Vdd. It should be noted that the characteristic diagram shown in FIG. 1 shows that Q ₁ , Q ₂ = 10/10 μm, R ₁
= 490 kΩ, R ₂ = 38 kΩ, K = 5, R ₃ = ₂₀ kΩ
FIG. 3 is a characteristic diagram based on the reference voltage generation circuit designed in FIG.
Further, V _F (approximately 0.7 V) shown in the figure is a forward ON voltage of the diode, and V _MIN is a minimum operating power supply voltage for normal operation of the above-described reference voltage generating circuit.

Next, the operation of the reference voltage generation circuit according to the present invention will be described with reference to the power supply voltage Vdd region with reference to FIGS. When Vss ≦ Vdd ≦ 2V _F : The power supply voltage Vdd is provided by the provision of the above-described start-up circuit (2).
The equivalent circuit shown in FIG. 3 is formed between the voltage and ground voltage Vss. Here, diode shown in FIG. 3 - de D ₄ are NPN Baipo in Figure 1 - is a de - diode between scan-emitter - La transistor Q ₃ of the base.

In this region, the diodes D _{1 to} D ₄
Not turned completely, the resistance R ₃ minute current from the power supply voltage Vdd, diode - grounded via the de D ₁ and D ₂ Voltage V
with flowing in the ss, resistance from the power supply voltage Vdd R _3, diode - de D _3, resistors R _1, diode - via de D ₄ flows to the ground voltage Vss. In this case, since the resistance values of the diodes D ₃ and D ₄ are much higher than the resistance values of the resistors R ₃ and R ₁ ,
The reference voltage V _REF output to the output terminal (1) is determined mainly by the voltage dividing action of the resistance values of the diodes D ₃ and D ₄ .

Therefore, the reference voltage V _REF is equal to the power supply voltage Vdd.
Increases with the slope of about Vdd / 2. For _{2V F <Vdd ≦ V MIN:} NPN in this area Baipo - La transistor Q ₃ of the base - scan-emitter diode - de D ₄ is turned on, the NPN Baipo - La transistor Q ₃
Turns on. Thus the NPN Baipo - initially the collector current flows through the La transistor Q _3, In response to this, N
PN Baipo - base La transistor Q ₄ - scan current is supplied, the NPN Baipo - La transistor Q ₄ is turned on, a current mirror - circuit substantially ground voltage drain of P-channel MOS transistors Q ₂ to which constitutes the reference side of the Reduce to Vss level. Therefore, the P-channel MOS transistor Q ₂ of gate - DOO-Source - relates scan voltage Vgs,
Vgs> Vtp is established and the transistor is turned on. Current mirror To that - P-channel MOS transistor Q ₁ constituting the output side of the circuit is also turned on, the reference voltage generating circuit starts operating. However, in this region, the power supply voltage Vdd is lower than the above-mentioned minimum operation power supply voltage V _MIN , so that the current supplied from the current mirror circuit is small, and the constant current required for normal operation is not supplied. _REF rises while having power supply voltage Vdd dependency.

On the other hand, in this region, the diodes D ₁ and D ₂ constituting the start-up circuit (2) are also turned on.
Diode - anode de D ₃ - de side potential becomes 2V _F. Furthermore diode - cathode of de D ₃ - de side, since equal to the potential of the reference voltage V _REF, the V _F over potential. Thus diode - de D ₃ is would be reverse biased, diode - de D ₃
, The supply of current to the reference voltage generating circuit is stopped, and the role of the start-up circuit (2) ends. When V _MIN <Vdd: A sufficient constant current is supplied from the current mirror circuit for the normal operation of the reference voltage generation circuit. As a result, as described above, the reference voltage V _REF generates the band gap voltage V _go without depending on the power supply voltage Vdd.

As described above, by providing the start-up circuit (2) in the conventional reference voltage generating circuit, even when the power supply voltage Vdd gradually rises from the ground voltage Vss, the reference voltage generating circuit can reliably operate. It is guaranteed to work. Moreover, the start-up circuit (2)
A reference voltage generating circuit is operating normally, in a state where the reference voltage V _REF generated occurs a bandgap voltage V _go, Star - up diode constituting the circuit (2) - De D ₃ is completely Since it is reverse-biased, the characteristics of the reference voltage generating circuit are not affected at all.

[0022]

As described above, according to the reference voltage generating circuit of the present invention, since the start-up circuit (2) is provided, even if the power supply voltage Vdd rises gently from the ground voltage Vss, it is possible to reduce the power supply voltage. Operation can be guaranteed. Thereby, when the reference voltage generation circuit of the present invention is incorporated in the power supply voltage detection circuit, even when applied to a system in which the power supply voltage Vdd rises gently from the ground voltage Vss, the comparison with the reference voltage _VREF is performed. Power supply voltage V
The change in dd can be detected, and malfunction of the system can be prevented.

In addition, the start-up circuit (2)
Since it is composed of a small number of elements of one resistor and three diodes, there is also an advantage that the increase in the pattern area is small.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a reference voltage generation circuit according to an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing a power supply voltage Vdd dependency of a reference voltage V _REF generated by a reference voltage generation circuit shown in FIG.

FIG. 3 is an equivalent circuit diagram for explaining an operation of the reference voltage generation circuit shown in FIG.

FIG. 4 is a circuit diagram showing a reference voltage generation circuit according to a conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 output terminal 2 start-up circuit Q ₁ , Q ₂ P-channel MOS transistor Q ₃ , Q ₄ NPN bipolar transistor R _{1 to} R ₃ resistance D _{1 to} D ₃ diode

Claims (1)

(57) [Claims] A mirror connected to a power supply voltage Vdd side;
One size P-channel MOS transistor Q₁, Q_Twoso
A current mirror circuit configured and an output of the current mirror circuit.
P-channel MOS transistor Q constituting the input side₁of
Temperature compensation resistor R connected in series to the drain₁, R_TwoThrough
The collector is connected, and the emitter is connected to the ground voltage Vss.
Connected, and the base is connected to the resistor R₁, R_TwoConnection point
NPN bipolar transistor Q_ThreeAnd the current
P-channel MOS transistor constituting the reference side of the
Jista Q_TwoThe collector is connected to the drain of the
Is connected to the ground voltage Vss, and the base is connected to the NPN device.
Polar transistor Q_ThreeConnected to the collector of the
The area of the NPN bipolar transistor Q _ThreeNo
NPN bipolar transistor set to K times the emitter area
Jista Q_FourAnd the reference voltage V_REFIs the P-cha
Channel MOS transistor Q₁Drain to output terminal
In the reference voltage generation circuit output in (1), the reference voltage generation circuit generates
Start-up circuit for guaranteeing circuit operation (2)
Wherein the start-up circuit (2) comprises a power supply voltage
A resistor R connected in series between Vdd and the ground voltage Vss_ThreePassing
And diode D₁, D_TwoAnd the anode side
Is the resistance R_ThreeAnd the diode D₁Connection point
And a die whose cathode side is connected to the output terminal (1).
Mode D_ThreeAnd a reference voltage generator.
Raw circuit.