JP2986761B2 - Hardware scaleable microprocessor / soft core design method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor ASI.
The present invention relates to a cooperative design method of hardware and software of a microprocessor / soft core for the purpose of computerization.

[0002]

2. Description of the Related Art A microprocessor (.mu.P) / soft core mounted on an ASIC aiming at high speed by executing dedicated instructions on a semiconductor by hardware (H / W) is generally a microprocessor of general-purpose parts. (ΜP),
Various instruction sets that can be handled by hardware and software (S / W) design are defined in advance. FIG.
FIG. 3 is a diagram showing an example of an H / W configuration 11 for realizing program processing by combining these instruction sets.
In the figure, an H / W 11 is a ROM 12 for storing a program by microcoding, a decoder 13 for decoding the program in H / W, an accumulator 14 for temporarily holding a value used for an operation, and storing an operation result. It has a register 15 whose value changes including a flag depending on the operation result, a RAM 16 used for saving the operation result holding register value and loading data to the accumulator 14, and each operation unit 17. The H / W blocks to be mounted are fixed as specifications for each μP type, and do not increase or decrease depending on the S / W. FIG. 9 is a diagram showing an example of the S / W program processing flow 21. The program for the μP soft core is coated with a high-level language such as C language or a language such as the assembler 22, and the program is applied to a compiler or assembler (step). 23), generate microcode 24; This generated microcode group is denoted by R
It is stored in the OM 12 and used.

[0003] Next, the operation of the microcode group generated by the above-described design method will be described. When the μP is started, first, the head of the microcode stored in the ROM 12 is read. The read microcode is analyzed by the decoder, and the instruction is executed. The microcode is sequentially read and executed according to a program counter indicating an execution address of the program. Here, a specific example in which the value of the address A of the memory is multiplied by the value of the address B and the result is stored in the memory address C will be described. (1) First, accumulator A from address A of RAM
Load values into (2) Next, from the address B of the RAM to the accumulator B
Load values into At the same time that each accumulator is loaded with a value, the value is input to the multiplier, and after a lapse of time according to the H / W execution performance, the result of the multiplication is set in the register. (3) The value of the register in which the operation result is set is stored in RAM
Is stored at the address C.

In the above-described μP soft core, the μP soft core
As with P, H / W specifications such as what H / W elements are incorporated are fixed. Therefore, in order to configure the system, even if there are arithmetic units and H / W blocks that are not used at all by the μP soft core, they remain in the ASIC without being deleted as H / W specifications. FIG.
FIG. 2 is a diagram showing a relationship between general system required performance and system processing time. When limited to a specific S / W execution,
There is often room for execution time. That is, the performance (system processing time) when μP is used for a specific S / W program often exceeds the system required performance. This results in wasted waiting time.

[0005]

The conventional μP soft core is configured as described above, and has a fixed H / W specification. Therefore, even if there is an unused H / W block, it is deleted. There is no. Therefore, compared to the case where the ASIC is formed using only the originally necessary μP soft core block,
The chip area increases and the delay time inside the ASIC increases,
There has been a problem that costs and power consumption increase. Furthermore, even if the system required performance is over-spec, there is a problem that the S / W program is not replaced with another microcode, and a wasteful waiting time occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems.
H / W blocks unnecessary for the S / W processing are reduced, or replaced with another microcode capable of performing equivalent processing within a predetermined time when over-specifying, and the specific gravity of the S / W processing is increased to increase the H / W block. The purpose is to reduce W blocks. As a result, it is an object to reduce the chip area of the entire ASIC and to reduce the delay time and the power consumption.

[0007]

According to the present invention, a method for designing a hardware-scale variable microprocessor / soft core according to the present invention decomposes a necessary instruction group into microcodes handled by a target microprocessor, and executes the decomposed microcodes. Element determination step to find the necessary hardware sub-elements and identification of decomposed microcode
Place the replacement microcode in another microcode group
Software replacement step to replace and other
Hardware that has become unused due to the use of microcode groups
Unnecessary hardware blocks to remove hardware sub-elements
Software deletion step, and the software
The air treatment was added.

[0008]

Still further, in the software replacement step, information indicating whether replacement is possible or not is added to an equivalent instruction,
Only the microcode to which the replaceable information is added is replaced by using another microcode group.

Further, in the software replacement step, priorities for replacing with equivalent instructions are provided, and replacement is performed using another microcode group in order from the microcode having the highest replacement priority.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. To delete unnecessary H / W blocks from the μP soft core and its S / W program, use S / W
It is necessary to analyze the program to grasp the usage status of the H / W element corresponding to the instruction, and to determine the unused H / W element. Further, if the system processing time has a sufficient margin than the required performance of the system, some S / W instructions (microcodes) are replaced with other microcodes and used.
Reducing the number of elements is effective for a well-balanced μP soft core design. FIG. 1 is a diagram showing the steps (steps) of the μP soft core design method according to the present embodiment.
FIG. 2 is a conceptual diagram of a basic configuration of an H / W element corresponding to the μP soft core of the ASIC. The μP soft core 31 includes a ROM 32 in which microcode obtained by decomposing the S / W program is stored, a decoder 33 that analyzes the microcode and controls an instruction, an accumulator 34 in which a value to be operated is stored, and an operation result. A register 35 for storing or changing (flag) a value according to the operation result, a RAM 36 for loading data into the accumulator 34 and saving the value of the register 35 for storing the operation result,
7 is provided. As described later, these H / W elements are new in that they can be deleted if they are not used in microcode.

FIG. 2 is a configuration diagram of a μP soft core with a variable hardware scale according to the present embodiment. FIG. 3 is a diagram showing an example in which microcode of a μP soft core is described using the H / W configuration shown in FIG.
The entire P soft core is designed as a module and each H / W is used hierarchically. In FIG. 3, from the module declaration on the first line to the end module declaration on the last line is the entire μP soft core, and each of the lines from the second line to the tenth line between the two lines is the H / W block of each H / W block. It means corresponding to the operation. FIG. 4 shows the H / W required for executing the instruction by the assembler instruction used in the μP soft core of FIG. 3 and the converted microcode.
It shows the correspondence list described by the element. For example, an LD (load instruction), which loads a value from a certain address in the RAM to the accumulator A, represents a list of H / W elements necessary for that.

A method of designing a μP soft core according to the present embodiment will be described with reference to the above-described design flowchart and an explanatory diagram of the μP soft core. First, step S in FIG.
In step 1, according to the basic configuration of the instruction set of the μP soft core, the μP soft core S / W program coated with the original C language or a language such as
Into microcodes. In the H / W configuration of the μP soft core as described above, the S / W designer can load the accumulator A, add / subtract, multiply, divide, store the operation result, and jump (including conditional jump). Can be handled by a high-level language represented by C language or S / W of an assembler. For example, assume that the following S / W program is described in assembler. LD A MUL B ST C (1) The expression (1) means that the value of the RAM address A is loaded into the accumulator A, multiplied by the value of the RAM address B, and the result is stored in the RAM address C. .

Next, an S / W program created by a high-level language such as C language or an assembler for the μP soft core described above is extracted for each operation instruction, and the S / W instruction, microcode and its instructions shown in FIG. 4 are executed. All necessary H /
Extract W description. For example, if the original μP soft core has a multiplier, but the multiplication instruction is not used in the S / W program, mltply (multiplier) is not listed as a necessary H / W block. That is, it can be specified that the block is an unnecessary H / W block. The H / W description related to the specified H / W block
By deleting from P soft core, unnecessary H /
Since the W block is not formed into an ASIC, the chip area can be reduced. That is, when the entire H / W description of the μP soft core used is extracted from this S / W program, the element of the following equation (2) is obtained from the correspondence table between the microcode and the H / W element in FIG. Required. rom decoder ram acca accb mltply reg (2) In other words, the microcode for executing the S / W of the equation (1) is an alu (adder / subtractor) of the μP soft core shown in FIG.
The H / W block corresponding to the video (divider) is unnecessary. In this case, alu in the μP soft core of FIG.
The device related block can be deleted from the H / W component, and therefore, the chip area of the ASIC can be reduced in step S7.

Next, a part of the microcode is replaced within the range required by the system requirement performance to replace the other redundant, but H
A description will be given of a method of reducing the number of H / W elements by making the / W element a code that can be shared with other microcodes. For the replacement of the microcode, it is convenient to create replacement mapping information in which instructions in the group of instructions handled in the μP soft core perform equivalent processing. The mapping information is a combination of an S / W instruction that handles a dedicated H / W block and another general-purpose S / W instruction that performs equivalent processing without using a dedicated H / W block. Is created as information. Further, in order to check that the upper limit of the system processing time falls within the required system performance, the clock cycle of the μP soft core is given as information in step S3 of FIG. 1, and the number of S / W program processing steps is determined in step S5. The obtained actual processing time is compared with the required system performance. In step S5, for the system required performance,
If there is enough processing time, S / W in step S6
The instructions used in the microcode of the program are searched from the mapping information, and replaced with microcode that performs other equivalent processing without using the dedicated H / W block used in the microcode. Thereafter, if the system required performance is satisfied by performing steps S12 to S15, the replacement assumed in step S6 is satisfied, and the dedicated H corresponding to the instruction originally used in S / W is satisfied.
Since the / W block is not required, the H / W element determined in step S17 and converted into an ASIC can be reduced.

Using the specific instruction group shown in FIG. 5, FIG.
The design method will be described. Hereinafter, first, in step S1, μ
Describes the H / W used by the microcode of the P soft core. Next, in step S2, an ASIC technology library is used to synthesize a netlist using logic elements to determine an operable clock operating frequency, and then in step S3, the period of the clock to be actually applied is determined. FIG. 5 is a diagram showing, as an example of step S6, mapping information in which instructions in the S / W instruction group perform equivalent processing, and shows a description when a multiplication instruction is replaced with an addition instruction. ing. FIG. 5 shows an example in which the high-level language and the assembler level are replaced, and it is defined that equivalent processing is performed on the left and right sides of the arrow. In addition to such mapping information, the time when the execution of the S / W program must be completed and the previously determined clock cycle are given to the compiler. For example, if the S / W processing constraint time is 50 μs and the clock cycle is 20 ns, the S / W processing step in the μP soft core is as shown in equation (3). 50 μs / 20 ns = 50000 ns / 20 ns = 2500 (steps) (3) That is, it is understood that the number of steps must be suppressed to a maximum of 2500 steps.

A microcode is generated by compiling an S / W program using a high-level language or assembler instruction that can be handled by the μP soft core basic configuration without replacing the instruction, and generating a microcode based on the number of steps and the clock cycle of the μP soft core. Processing time can be calculated. The system processing time is compared with the given constraint time, and if there is enough time in the system processing time, the microcode is replaced and the reevaluation is performed after step S6. In the case described above, if the number of S / W processing steps is 2500 steps or less, it can be determined that there is enough system processing time.

If there is a margin in the system processing time, S /
The W program searches for replaceable instructions and replaces them with equivalent S / W instruction processing according to the mapping information. For example, all multiplication instructions used in the S / W program are replaced with equivalent addition instructions according to the mapping information in FIG. In this way, the multiplier can be eliminated from the μP soft core.

Based on the H / W configuration description by the μP soft core from which unnecessary multipliers have been deleted, in steps S12 to S13, the data is re-synthesized into a netlist using logic elements using an ASIC technology library. After obtaining an operable clock operating frequency, the period of the clock to be applied is determined. On the other hand, the S / W program in which instructions have been replaced so as to perform equivalent system processing is recompiled to generate microcode, and the number of steps until the execution is completed is calculated. A system processing time is calculated in step S14 from the number of steps and the system operating frequency, and a system processing restriction time (specification) is determined in step S15.
Compare with If the processing can be performed within the system processing restriction time, it can be concluded in step S17 that the multiplier is finally unnecessary, and the reduction in the area of the μP soft core is determined.

According to the μP soft core design method described above, unnecessary H / W blocks can be deleted by S / W processing,
It is possible to change the specific gravity of H / W processing and S / W processing. By arbitrarily changing the mapping information, a circuit that can be used in the future can be left, or only part of the circuit can be replaced with equivalent S / W processing.

Embodiment 2 FIG. Superiority in replacing S / W instruction,
The case where restrictions are added will be described. When there are a plurality of pieces of mapping information, it is conceivable that only some of the S / W instructions may be replaced in consideration of future changes in the S / W program. Hereinafter, the soft core design method in the present embodiment will be described with reference to the drawings. FIG. 6 is a diagram illustrating an example of mapping information describing an instruction that may be replaced in consideration of future S / W use and an instruction that should not be replaced. In the figure, F1 is a replaceability / non-replacement designation flag which temporarily indicates at the time of design whether or not conversion is possible. Attempt to replace only the instruction whose flag is 1 (convertible). In this way, it is possible to easily change the instruction replacement condition simply by adding, as a definition, the condition of whether or not replacement is possible to the mapping information between instructions for which a plurality of processes are equivalent. Since the mapping information can be changed freely, the replacement load is changed and the S / W
The number of steps of the program, the chip area of the μP soft core, and the system processing time are calculated, and it is possible to determine whether or not the processing can be performed within the system processing restriction time.

Another μP soft core design method according to the present embodiment will be described with reference to FIG. When there is a plurality of pieces of mapping information, priority is given to instruction replacement, and replacement is considered up to the limit of system specifications. That is, in FIG. 7, F2 is a priority designation flag, which gives a priority to an instruction to be replaced with mapping information between instructions for which a plurality of processes are equivalent. Replace with the one with the highest priority (smaller number). In this way, it is possible to easily change the order of replacement of instructions in addition to the definition information. The instruction is replaced in the priority order of the S / W instruction, and the unnecessary H /
Delete the W block. The order is changed to find the operating frequency of the μP soft core, and a loop of compiling the S / W program is repeated, and the processing is completed within a time period not exceeding the system constraint time.

[0023]

As described above, according to the present invention, an element determination step and a system constraint calculation step are provided.
Since H / W is reduced if the required specifications are not satisfied, there is an effect that the chip area is reduced, and small and low power consumption and an improvement in operating frequency are obtained.

Furthermore, a software replacement step is provided to evaluate the system with equivalent microcode, so that a well-balanced μ without wasteful delay time can be obtained.
There is an effect that a P soft core can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a step of a microprocessor / softcore design method according to the present invention.

FIG. 2 illustrates an example of a microprocessor hardware component according to the present invention.

FIG. 3 is a diagram illustrating an example of hardware description of a μP soft core using the hardware components of FIG. 2;

FIG. 4 is a diagram showing an example of correspondence between assembler instructions, microcode, and used hardware elements.

FIG. 5 is a diagram showing an example of an instruction that can be replaced with another equivalent S / W instruction in the S / W instruction group.

FIG. 6 is a diagram illustrating an example of mapping information according to the second embodiment.

FIG. 7 is a diagram showing another example of mapping information according to the second embodiment.

FIG. 8 shows a microprocessor H / having a fixed H / W element.
It is a W component diagram.

FIG. 9 is a flowchart of a program processing for generating a general μP microcode.

FIG. 10 is a diagram showing a relationship between general system processing time and system required performance.

[Explanation of symbols]

S1 Decomposition into μP microcode, element determination step for obtaining hardware components, S4, S14 S / W processing time calculation step using microcode, S5, S
15 Comparing step to check whether it falls within the system constraint time, S6: replacing step by replacing with another equivalent microcode, S7, S17: deleting step by which H / W elements not used by the microcode are deleted, F1 replacement enable / disable designation flag, F2 Priority specification flag.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-116302 (JP, A) JP-A-10-31693 (JP, A) JP-A-9-160949 (JP, A) JP-A 9-160 81604 (JP, A) JP-A-9-251477 (JP, A) JP-A-3-102571 (JP, A) WO 95/31778 (WO, A1) Tsuyoshi Ikenaga, Katsuhiko Shirai, " Specialized Processor Design Support System for Realizing Advanced Algorithms, ”Transactions of the Information Processing Society of Japan, November 1991, Vol. 32, No. 11, p. 1445-1456 (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 17/50

Claims (3)

(57) [Claims] 1. An element determining step of decomposing a necessary instruction group into microcodes handled by a target microprocessor, and determining a hardware sub-element required to execute the decomposed microcode; Micro to be replaced
Software that replaces code with other microcode groups
A) by using the substituting step and using the substituting other microcode group
Unnecessary hardware to remove hardware sub-elements
Request execution time with a hardware block deletion step
A hardware scale variable microprocessor / soft core design method characterized in that software processing is stored in the software . 2. In the software replacement step,
Information that can or cannot be replaced is added to a valuable instruction,
Only microcode with possible information added to other
The feature is that replacement is performed using crocode groups.
The hardware scale variable microprocessor according to claim 1,
Sessa soft core design method. 3. In the software replacement step,
Priority is set to replace expensive instructions, and the priority of the replacement is
Use other microcode groups in descending order of microcode
2. The method according to claim 1, wherein the replacement is performed.
Hardware scalable microprocessor / software
A design method.