JP2982291B2 - Field effect transistor logic circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor logic circuit, and more particularly to a field effect transistor logic circuit to which a reference voltage generation circuit is added.

[Conventional technology]

GaAs semiconductors have several times faster electron mobility than Si and can easily obtain a semi-insulating substrate, which can reduce the parasitic capacitance of the circuit during integration and enable high-speed logic operation. Based on this idea, vigorous R & D has been conducted in various places. Some GaAs semiconductors have been commercially available,
The varieties are mainly from SSI to MSI class, and the next development varieties are expected to be 1K to 4K bit memories and gate array type integrated circuits with several thousand gates.
Especially, BFL (Buffered FET Logi) using depletion type Schottky gate field effect transistor (MESFET).
c) The circuit is capable of high-speed logic operation even when driving a large load, and has been used for designing GaAs LSIs.

Conventionally, a GaAs BFL circuit has an inverter circuit and a level shift type buffer circuit as shown in FIG. 3, and a method of driving a large load by the buffer circuit has been adopted. In FIG. 3, the drain electrode of FET1 is connected to power supply terminal 100, the source and gate electrodes are connected to node 11, the drain electrode of FET2 is connected to node 11, the gate electrode is connected to input terminal 10, and the source electrode is connected to input terminal 10. The electrodes are connected to a power supply terminal 101, and these FETs 1 and 2 constitute an inverter circuit. FET3 has its drain electrode connected to the power supply terminal 100,
The gate electrode is connected to the node 11 of the output of the inverter circuit, and the source electrode is connected to the node 12. The diode 4 has an anode connected to the node 12, a cathode connected to the output terminal 20, a drain electrode of the FET 5 connected to the output terminal 20, a source and a gate electrode connected to the power supply terminal 102, and these FETs 3, 3. The diode 4 and the FET 5 constitute a buffer circuit. In particular, the FET 5 is used as a constant current source, and the potential of the output terminal 20 is determined by the balance with the drain current of the FET 3.

Such a BFL circuit has a buffer circuit to improve the gain of the inverter circuit, even if the current supply capability of FET1 is extremely small compared to FET2,
The delay time of the output potential does not increase.

[Problems to be solved by the invention]

In the BFL circuit shown in FIG. 3, the delay time of the circuit is strongly affected by the current of the FET5. On the other hand, the current of the FET 5 is approximately given by a function as shown by the equation (1).

IDS = W5KVt ² (1) In equation (1), W5 is the gate width of the FET 5, K is the transconductance, and Vt is the threshold voltage. From equation (1)
It can be seen that the current of the FET 5 is proportional to the square of the threshold voltage and is strongly affected by the threshold voltage.

By the way, the BFL circuit requires two types of power supplies as power supplies for the inverter circuit section and the level shift circuit section, and thus consumes a large amount of power.
However, there is a disadvantage that the operating temperature becomes high. Further, there is a disadvantage that the threshold voltage of the MESFET shifts to the negative side as the environmental temperature increases, resulting in a further increase in the amount of heat generated. When such a BFL circuit is placed in an IC chip,
It is a serious problem that the temperature "unevenness" is locally generated and the delay time of each logic circuit inside the IC fluctuates greatly due to the threshold voltage fluctuation.

It is an object of the present invention to provide a field effect transistor logic circuit that suppresses fluctuations in circuit delay time even when Vt fluctuations occur due to local temperature unevenness due to heat generation inside an IC and does not increase the number of types of power supplies. is there.

[Means for solving the problem]

In the field effect transistor logic circuit according to the present invention, a load element having one end connected to the first power supply terminal and the other end connected to the first node, a drain electrode connected to the first node, and a gate electrode connected to the first node. An inverter circuit connected to a terminal, the source electrode being a first MESFET connected to a second power supply terminal, and a drain electrode connected to the first power supply terminal;
A second MESFET having a gate electrode connected to the first node and a source electrode connected to the second node; and a level shifter having one end connected to the second node and the other end connected to the output terminal. A level shift type buffer circuit including an element, a third MESFET having a drain electrode connected to the output terminal, a gate electrode connected to the third node, and a source electrode connected to the third power supply terminal; A plurality of serial level shift elements connected to a second power supply terminal and the other end connected to a fourth node; one end connected to the fourth node and the other end connected to the third node; And a reference voltage generating circuit including a fourth MESFET having a drain electrode connected to the third node and a source and a gate electrode connected to the third power supply terminal. .

[Action]

In the field-effect transistor logic circuit according to the present invention, the gate-source voltage of the current source FET is determined by circuit parameters by obtaining the gate potential of the buffer current source FET of the BFL logic circuit from the reference voltage generation circuit. It takes the maximum value in the threshold voltage. By setting the design value of the threshold voltage to this value, it is possible to suppress the current fluctuation of the current source FET due to the temperature fluctuation.

The delay time of the circuit is not affected by the fluctuation of the threshold voltage due to the control of the current by the reference voltage generating circuit.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. First
FIG. 1 shows an embodiment of a field effect transistor logic circuit according to the present invention. In the present embodiment, the gate voltage of the current source FET 5 of the buffer unit is connected to the resistor 6 having one end connected to the power supply terminal 103 and the other end connected to the node 13, the drain electrode connected to the node 13, the gate and the source. The electrodes are obtained from a reference voltage generating circuit comprising an FET 7 connected to a power supply terminal 102. Other configurations are the same as the configuration of the circuit shown in FIG. 3, and the same elements are denoted by the same reference numerals.

Here, the threshold voltage of the depletion type FET is Vt,
Assuming that the transconductance is K, the resistance value of the load element of the reference voltage generation circuit is R, the gate width of the MESFET is W7, and the Schottky rising voltage of the buffer current source FET5 is Vf, the threshold voltage Vt and the reference voltage generation circuit section The load resistance R is (2)
Choose to satisfy the formula.

The reason for limiting the threshold voltage of the FET as described above is that the negative feedback by the reference voltage generating circuit is obtained by finding the threshold voltage value at which the current change of the FET 5 with respect to the change of the threshold voltage Vt is minimized. This is to prevent the effect from becoming excessive.

Now, when the “H” level is input to the input terminal 10, the node 11
Becomes "L" level, the driving capability of the FET 3 is temporarily reduced, and the charge of the load capacitance connected to the output terminal 20 is discharged by the FET 5. The amount of current at this time is determined by the gate bias of FET5. This gate bias is obtained from the reference voltage generating circuit, and its level takes the maximum value at the threshold voltage determined by the parameters of the circuit, as shown in FIG. By setting the design value of the threshold voltage to this value, it is possible to suppress the current fluctuation of the current source FET caused by the threshold fluctuation due to the temperature fluctuation. As a result, the delay time of this circuit is
No longer affected by temperature fluctuations.

The reason why the voltage of the power supply terminal is limited as shown in the equation (3) is to reduce the number of types of power supplies by connecting the reference voltage generation circuit between the power supply terminals 101 and 102.

[Effect of the Invention] In the field effect transistor logic circuit according to the present invention, since the gate bias of the buffer current source FET is obtained from the reference voltage generation circuit, the variation of the delay time due to the temperature fluctuation is smaller than that of the normal BFL circuit. Few. Therefore, it is possible to improve the chip yield by applying the circuit of the present invention to blocks in the LSI where timing is important. In addition, by limiting the range of the threshold voltage of the FET and the range of the power supply voltage, the type of power supply can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a diagram for explaining the current and gate-source voltage of a buffer current source FET of the circuit of the present invention, and FIG. 3 is a conventional example. It is a circuit diagram. 1,2,3,5,7 ... depletion type FET, 4,8 ... level shift element, 6 ... resistor, 10 ... input terminal, 20 ... output terminal, 11,12,13 ... node , 100, 101, 102, 103 ... Power supply terminals.

Claims (2)

(57) [Claims] A load element having one end connected to the first power supply terminal and the other end connected to the first node; a drain electrode connected to the first node; a gate electrode connected to the input terminal; A first MESFET whose electrode is connected to a second power supply terminal
And a second MESFET having a drain electrode connected to the first power supply terminal, a gate electrode connected to the first node, and a source electrode connected to the second node.
A first level shift element having one end connected to the second node and the other end connected to the output terminal; a drain electrode connected to the output terminal; a gate electrode connected to the third node; and a source electrode connected to the third node. Third MESFET connected to third power supply terminal
A plurality of serial level shift elements having one end connected to the second power supply terminal and the other end connected to the fourth node, and one end connected to the fourth power supply terminal.
A load element having the other end connected to the third node and a fourth element having a drain electrode connected to the third node, and a source and a gate electrode connected to the third power supply terminal. A field effect transistor logic circuit, comprising: a reference voltage generation circuit including a MESFET. 2. The threshold voltage of the MESFET is Vt, the transconductance is K, the voltage of the second power supply terminal is Vss1, the voltage of the third power supply terminal is Vss2, the load element of the reference voltage generation circuit. Is R, the gate width of the fourth MESFET is W, the Schottky rising voltage of the third MESFET and the shift amount of the level shift element are Vf, The field effect transistor logic circuit according to claim 1, wherein the following condition is satisfied.