JP2979077B2 - Installation / removal system between computer and optional equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply for an optional device such as a hard disk or a printer which is a peripheral device of a personal computer. The present invention relates to a system configured to transfer data between a unit and an internal circuit unit of an optional device, and to a system for mounting and removing the optional device with respect to a computer main body.

[0002]

2. Description of the Related Art FIG. 5 is a schematic circuit diagram showing a conventional system for attaching and detaching a computer main body and optional equipment.

In the figure, A ₁ is a computer body, B is
₁ optional equipment, 1 socket portion of the computer main body A ₁ and optional equipment B _1, 2 are optional equipment control unit, 3 optional equipment internal circuit unit, 4 is a DC power supply output section of the computer main body A ₁ side, 5 is a DC power reception unit of the optional device B ₁ side. It is directly connected to the optional device control unit 2 and optional equipment B optional equipment internal circuit 3 in _one of the computer body A _1. Moreover, it is directly connected to the DC power supply output section 4 and the optional equipment B ₁ of the DC power reception unit 5 of the computer main body A ₁ side.

When connecting the optional device B ₁ to the computer main unit A ₁ via the socket unit 1,
The power of the computer A ₁ in the OFF after the state eliminating the output of the DC power supply output section 4, mounting the optional device B ₁ to the computer main body A _1. After the mounting is complete, turn ON the power of the computer main body A ₁ supplies power to the DC power reception unit 5 from the DC power supply output section 4, the optional equipment internal circuit portion 3 from the DC power reception unit 5 It would use the optional equipment B ₁ by feeding.

Further, when detaching the optional device B ₁ from a state wearing the optional equipment B ₁ to the computer main body A _1, in the same manner as mentioned above, previously, the DC power source is turned OFF the power of the computer main body A ₁ after a state of eliminating the output of the output unit 4, to desorb the optional device B ₁ from the computer main body a _1.

[0006]

[SUMMARY OF THE INVENTION] However, optional equipment power B ₁ is with is powered directly from the DC power supply output section 4 of the computer main body A _1, computer A ₁ optional equipment control unit 2 and optional equipment B _Since the optional device internal circuit section 3 is directly connected to the computer main unit A _{1 when} the optional device B ₁ is attached to and detached from the computer main unit A _1.
If the device is attached or detached while the power of the
There is a danger of destruction (latch-up, etc.) and malfunction of the device. That is, the protection circuit is not provided to latch-up, also because regulations regarding access data exchange with the computer A ₁ and optional equipment B ₁ is not yet been any.

[0007] Therefore, when the wearing the optional equipment B ₁ the computer main body A ₁ is, sure, temporarily suspended the work of a computer body A _1, OFF the power
There was an inconvenience that it had to be done.

The present invention has been made in view of such circumstances, and even if an optional device is attached / detached while the power supply of the computer is ON, the IC is destroyed (latch-up or the like) or malfunctions. The purpose is to prevent the occurrence of.

[0009]

According to the first aspect of the present invention ,
System for attaching and detaching the computer and optional equipment
Beam is, there is the option device is freely wearing state the computer main body, which is configured for exchanging data between the internal circuit unit in the optional device with optional equipment control unit in the computer, provided with a locking mechanism for locking the mounted state of the optional device for said computer main body, and provided with a detecting means for detecting the locking state of the locking mechanism, when the detection means detects the unlock state
Activates the interrupt processing, and
Set down unconnected state, while prohibiting data Professor receive between each other, when the detecting means detects the locked state interrupt
Start the process and connect the option to the computer
Set, comprises an interrupt means for allowing the data Professor receive between each other. A loading / removing system according to claim 2
In the interrupt means, the detecting means detects the unlocked state.
Power supply to optional equipment when
When the lock status is detected, the power
Characterized in that it is designed to start paying
I have.

[0010]

[Function] Even if the optional device is mounted on the computer main unit, access to data transfer between the optional device control unit of the computer main unit and the internal circuit unit of the optional device is prohibited unless the lock mechanism is locked. The data transfer is allowed only when the lock state is set. Then, when the optional device is detached from the computer main body, when the lock mechanism is released, access for data transfer is also prohibited. Therefore, even if the optional equipment is mounted or removed while the power of the computer main body is kept ON, the destruction (latch-up or the like) or malfunction of the IC is prevented.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a system for attaching and detaching a computer main body and optional equipment according to the embodiment.

[0013] The computer main body A and the optional device B is adapted to be the wearing through the socket portion 11. In FIG. 1, reference numeral 12 denotes an optional device control unit, 13 denotes an optional device internal circuit unit, 14 denotes a DC power output unit on the computer main body A side, and 15 denotes a DC power supply receiving unit on the optional device B side.

On the computer main unit A side, low active three-state buffers 16a and 16b are provided in a state connected to the optional device control unit 12, and on the optional device B side, low active three-state buffers 17a and 17b are provided. Is provided in a state connected to the optional device internal circuit unit 13, and the optional device control unit 12 and the optional device internal circuit unit 13
Are the three-state buffers 16a, 16b, 1
They are connected via 7a and 17b. The DC power supply output unit 14 includes a DC power supply Vcc (+5 V), a starting resistor R ₁ ,
The MOS-FET 18 of the P-channel type output, and a NPN-type switching transistor Q ₁ Tokyo for startup. DC power receiving unit 1 on optional equipment B side
5 is connected to the drain of the MOS-FET 18. An inverter circuit 19 having an output terminal connected to the base of the switching transistor Q ₁ has a first register R whose input terminal specifies the optional device presence / absence signal S _1.
It is connected to the g _1.

On the optional device B side, a reset circuit 20 for outputting a reset pulse in accordance with the rise of the DC power supply receiving unit 15 (DC power supply Vcc (+5 V)), a reset pulse waveform shaping circuit 21, and an inverter circuit 22
, A D-type flip-flop circuit 23, an optional device lock detection switch 24, and the like.

On the other hand, the computer main unit A is provided with a D-type flip-flop circuit 25, an AND circuit 26, a three-state buffer 27, an OR circuit 28, and the like. 29 indicates a pull-up resistor indicated by a downward triangle.

An output terminal of the reset circuit 20 is connected to an input of a waveform shaping circuit 21. An output terminal of the waveform shaping circuit 21 is connected to an input of an inverter circuit 22.
The output terminal 2 is connected to the clock terminal CLK of the flip-flop circuit 23.

The / Q output terminal of the flip-flop circuit 23 (the symbol “/” represents negation) is connected to one input terminal of the AND circuit 26. The optional device lock detection switch 24 is connected to the first register Rg ₁ and the inverter circuit 19, and is also connected to the clock terminal CLK of the flip-flop circuit 25. The Q output terminal of the flip-flop circuit 25 is connected to one input terminal of the OR circuit 28, and the / Q output terminal is connected to one input terminal of the AND circuit 26. Output terminals of the AND circuit 26 is connected to the control terminal of the three-state buffer 27, an output terminal of the three-state buffer 27 is connected to the second register Rg ₂ to specify the interrupt signal S _{2. Third} to specify the interrupt ack signal S3
The register Rg ₃ of the flip-flop circuits 23 and 25
Is connected to the clear terminal CLR. Fourth register Rg ₄ is connected to one input terminal of the OR circuit 28, the output terminal is three-state buffer 16a of the OR circuit 28, 16b, 17a to specify the three-state ON signal S _4,
17b is connected to the control terminal.

FIG. 2 and FIG. 3 schematically show a locking mechanism of the optional device B with respect to the computer main body A. The optional device B in the case of FIG. 2 is, for example, a printer. At both ends of the optional device B, when the optional device B is mounted on the computer main body A, the mounting state is manually locked. A lock mechanism 30 for manually releasing the lock before the lock is provided. The optional device B in the case of FIG. 3 is a cartridge-type hard disk, and a lock mechanism 30 similar to the above is provided at one end of the optional device B. Such a lock mechanism 30 is provided by the optional device lock detection switch 24 shown in FIG.
The optional device lock detection switch 24 is closed when locked, and is opened when unlocked.

Next, the operation of the system for attaching and detaching the computer main body and the optional equipment configured as described above will be described.

[1] Mounting of Optional Equipment First, the operation when the optional equipment B is mounted on the computer main body A will be described.

Now, it is assumed that the optional device B is detached from the computer main unit A. Since the lock mechanism 30 is in the released state, the optional device lock detection switch 24
Is open. Then, the computer body A
It is assumed that the power is currently ON and in use. In the initialization at the time of power ON, the third register Rg
_The interrupt acknowledgment signal S3 designated by ₃ once becomes "L" level, clears the flip-flop circuit 25, and sets each Q output terminal to "L" level and / Q output terminal to "H" level. Thereafter, it returns to the “H” level.

However, the "L" level and "H" level states of the Q output terminal and the / Q output terminal are maintained as they are. Both input terminals of the AND circuit 26 are at the “H” level, and the three-state buffer 27 is in the three-state OFF state. Moreover, three-state ON signal S ₄ of the fourth register Rg ₄ is set at "H" level, the output of the OR circuit 28 is at "H" level, the low active state buffer 16a, 16b is inactive.

In this state, it is assumed that the user mounts the optional device B on the computer main body A via the socket section 11 and locks the lock mechanism 30 after the mounting is completed. With this lock, the optional device lock detection switch 24 is closed. Then, the option device presence / absence signal S ₁ becomes “L” level and is stored in the first register Rg _1, and the switching transistor Q ₁ of the DC power supply output unit 14 is turned on via the inverter circuit 19. MOS-FET 18 is also conducted by the conduction of the switching transistor Q _1, a DC power source Vcc of the DC power supply output section 14 (+ 5V) is to be supplied to the DC power reception unit 15 in the optional device B.

A DC power supply Vcc (+5
When V) is supplied, the input voltage of the reset circuit 20 increases, and the reset circuit 20 outputs a reset pulse.

This reset pulse is supplied to the waveform shaping circuit 21.
After the waveform is shaped and inverted by the inverter circuit 22, it is input to the clock terminal CLK of the flip-flop circuit 23. Then, the flip-flop circuit 2
3 / Q output terminal is changed from "H" level to "L" level.
Invert to level. Therefore, the AND circuit 26 is "L" level output, and the three-state buffer 27 to ON "L" level of the interrupt signal S ₂ the second
Stored in the register Rg _2.

In the computer main unit A, when the interrupt signal S ₂ is inverted to “L” level, the BIO
An interrupt processing routine of an S (basic input / output system) program is executed. This will be described with reference to the flowchart of FIG.

[0028] When the second register Rg ₂ is the interrupt signal S ₂ specifies becomes "L" level, the process proceeds to the interrupt processing routine from step S1. In step S1, a determination is made as to confirm the first contents of the register Rg _1, or optional equipment existence signal S ₁ is present ( "L") or not ( "H"). Here, as described above, since it is present (“L”), the process proceeds to step S2, and “common device” is set in the BIOS common area. That is, the access to the optional device B is set to “permitted”. Then, in step S3, the fourth register Rg ₄ is set to "L" level three-state ON signal S _4, then the routine proceeds to step S6, the third register R
Once the interrupt acknowledge signal S ₃ in g ₃ "L"
Level, and immediately return to the “H” level. By the interrupt acknowledge signal S ₃ will once "L" level, clears the flip-flop circuits 23 and 25, respectively /
The Q output terminal is set to “H” level. Then, since the two input terminals of the AND circuit 26 become “H” level, the output thereof becomes “H” level, and the three-state buffer 27
The output of the three-state OFF condition, the interrupt signal S ₂ is a storage content of the second register Rg ₂ is cleared and returns to the original step of the main routine ends the interrupt processing routine. Further, since the two input terminals of the OR circuit 28 are also at "L" level, the output thereof is also at "L" level, and the low active three-state buffer 1
6a, 16b, 17a, and 17b become active, the optional device control unit 12 in the computer main unit A and the optional device internal circuit unit 13 in the optional device B are connected, and the active state is determined to be "enabled" in step S2. In addition, data can be exchanged between the optional device control unit 12 and the optional device internal circuit unit 13.

As described above, until the optional device lock detection switch 24 is closed, the three-state buffers 16a, 16b, 17a, and 17b are kept in the inactive state. Only after confirming that the mounting state of the device B is locked and the optional device lock detection switch 24 is closed (step S2), the three-state buffers 16a, 16b, 17a, and 17b are first obtained.
Activate the optional device control unit 1
2 is allowed to transmit and receive data between the optional device internal circuit section 13 and the IC device can be destroyed even if the optional device B is mounted while the power of the computer main unit A is ON. Latch-up, etc.) and malfunction can be prevented.

[2] Attachment / detachment of optional equipment Next, the operation when the optional equipment B is attached / detached from the computer main body A will be described.

It is assumed that the user releases the lock mechanism 30 to detach the optional device B from the computer main unit A while the power of the computer main unit A is ON. Then, the optional device lock detection switch 24 is opened from the previously closed state. Then
Is optional equipment existence signal S ₁ is "H" level is stored in the first register Rg _1. When the optional device presence / absence signal S ₁ becomes “H” level, the switching transistor Q ₁ of the DC power output unit 14 is cut off via the inverter circuit 19. When the switching transistor Q ₁ is blocking MOS-FET 18 is also cut off, the DC power source Vcc of the DC power supply output section 14 (+ 5V) is not supplied to the DC power reception unit 15 in the optional device B.

Further, by inverting the optional device presence / absence signal S ₁ from “L” level to “H” level,
The Q output terminal of the flip-flop circuit 25 goes to “H” level, and the output of the OR circuit 28 also goes to “H” level. Then, the low-active three-state buffer 16
a, 16b, 17a, and 17b enter the three-state OFF state (inactive state), and the computer main unit A
The connection between the optional device control unit 12 and the optional device internal circuit unit 13 in the optional device B is cut off, and the transfer of data between the optional device control unit 12 and the optional device internal circuit unit 13 is prohibited.

On the other hand, when the / Q output terminal of the flip-flop circuit 25 is inverted to "L" level, the AND circuit 2
6 becomes "L" level, the three-state buffer 27 is turned on, and the "L" level interrupt signal S
Stores ₂ into the second register Rg _2.

Since the interrupt signal S ₂ has been inverted to the “L” level, the processing shifts to an interrupt processing routine of a BIOS (basic input / output system) program. That is, the determination as shown in the flowchart of FIG. 4, at step S1, check the first contents of the register Rg _1, or optional equipment existence signal S ₁ is present ( "L") or not ( "H") I do. Here, as described above, there is no (“H”), so the process proceeds to step S4 to set “no optional device” in the common area of the BIOS. That is, access to the optional device B is set to “impossible”. Then, the process proceeds to step S5, in the fourth register Rg ₄ is set to "H" level three-state ON signal S _4, then the routine proceeds to step S6, the third register R
Once the interrupt acknowledge signal S ₃ in g ₃ "L"
Level, and immediately return to the “H” level. By the interrupt acknowledge signal S ₃ will once "L" level, clears the flip-flop circuits 23 and 25, respectively /
The Q output terminal is set to “H” level. Then, since the two input terminals of the AND circuit 26 become “H” level, the output thereof becomes “H” level, and the three-state buffer 27
The output of the three-state OFF condition, the interrupt signal S ₂ is a storage content of the second register Rg ₂ is cleared and returns to the original step of the main routine ends the interrupt processing routine. Also, maintenance since the three-state ON signal S ₄ is set to "H" level, even if the Q output terminal of flip-flop circuit 25 is "L" level, the output of the OR circuit 28 is the "H" level And the low active three-state buffers 16a, 16b,
The inactive states of 17a and 17b are maintained.

As described above, as a preliminary operation before detaching the optional device B from the computer main unit A, the optional device B is opened based on the opening of the optional device lock detection switch 24 by releasing the lock mechanism 30.
, The three-state buffers 16a, 16b, 17a, and 17b are set to the inactive state, and the power supply to the DC power receiving unit 15 in the optional device B is cut off. Then, in this state, the optional device B is detached from the computer main body A in the socket section 11.

Therefore, even if the optional device B is detached while the power of the computer main unit A is kept ON, the destruction (latch-up, etc.) and malfunction of the IC can be prevented.

[0037] In after desorption of the optional equipment B also, optional equipment whether or not the signal S ₁ keeps the "H" level, "no option equipment" to the common area of the BIOS
Maintain the state setting of.

The lock mechanism 30 and the optional device lock detection switch 24 may be provided on the computer main unit A side.

[0039]

As described above, according to the present invention, data transmission between the computer and the optional device is prohibited unless the optional device is locked to the computer. Even if the optional device is supplied with power from the computer main body, even if the optional device is attached / detached while the power of the computer main body is turned on, destruction (latch-up, etc.) and malfunction of the IC are prevented. be able to. In other words, it is not necessary to turn off the power of the computer body each time an optional device is attached or detached, so that operability and workability can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a system for attaching and detaching a computer main body and optional devices according to an embodiment of the present invention.

FIG. 2 is a perspective view schematically showing an example of a lock mechanism in the embodiment.

FIG. 3 is a perspective view schematically showing another example of the lock mechanism in the embodiment.

FIG. 4 is a flowchart for explaining the operation in the embodiment.

FIG. 5 is a schematic circuit diagram showing a conventional system for attaching and detaching a computer main body and optional devices.

[Explanation of symbols]

A Computer body B Optional equipment 11 Socket part 12 Optional equipment control part 13 Optional equipment internal circuit part 14 DC power output part 15 DC power receiving part 16a, 16b Three-state buffer 17a, 17b Three-state buffer 19 Inverter circuit 20 Reset circuit 21 Waveform Shaping circuit 22 Inverter circuit 23 Flip-flop circuit 24 Optional device lock detection switch 25 Flip-flop circuit 26 AND circuit 27 Three-state buffer 28 OR circuit 29 Pull-up resistor 30 Lock mechanism Q ₁ Switching transistor S ₁ Optional device presence / absence signal S ₂ Interrupt signal S ₃ interrupt acknowledge signal S ₄ tristate ON signal Rg ₁ ~Rg ₄ registers

Claims (2)

(57) [Claims] 1. The computer bodyOptional machine
BowlFreely removableage, The computer body
Option device control section and the optional device
Exchange data with the internal circuit sectionConfiguration andIs
System for attaching and detaching the computer and optional equipment
And  Mounting of the optional device on the computer body
In addition to providing a lock mechanism to lock the wearing state,
Detects the lock state of the lock mechanismdetectionProvide meansIn
This inspectionWhen the release means detects the unlocked stateIs relatively
Start the loading process, and the option
Set the connection statusData transferReceivingWhile banning, Detecting hands
StepWhen the lock status is detectedActivate interrupt handling
And set the option connection status on the computer
Data transferReceivingTolerateinterruptEquipped with meansingThat
Characteristic attachment / detachment between computer and optional equipment
Wearing system. 2. The loading / removing system according to claim 1, wherein
The interrupt means detects the unlocked state by the detecting means.
Power supply to optional equipment
Supply power to optional devices when a lock condition is detected.
Characterized in that it is configured to start
An attachment / detachment system for the computer and optional equipment.