JP2976452B2 - Feedback pulse width modulation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an improvement in a circuit for transmitting a pulse width signal corresponding to a DC input voltage. INDUSTRIAL APPLICABILITY The present invention is used for transmitting a DC voltage signal to a remote place in an input circuit of an analog-to-digital converter or an automatic control device, a measuring device, a measuring device, and the like.

〔Overview〕

The present invention provides pulse width modulation in which positive and negative reference voltage sources to be added to an input of an integration circuit are alternately connected by inverting and connecting capacitors charged by a unipolar power supply, and positive and negative reference voltages are generated from one power supply. In a circuit, regardless of the output pulse width that changes according to the voltage of the input terminal, the capacitor charging voltage is set by forcibly connecting the capacitor and the power supply for the minimum required time to charge this capacitor in one cycle. Is insufficient to avoid an error in the positive and negative reference voltages.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional example of a pulse width modulation circuit. In FIG. 3, the DC input voltage which is the modulation input to be transmitted
Ex, reference voltage + E where the absolute value is the same and the polarity is reversed
r, −Er, and the clock signal ± Ec whose polarity is inverted at a constant cycle are added by resistors R ₁ , R ₂ and R ₃ , respectively, and applied to the input of the integration circuit S. voltage is supplied to the input of the comparison circuit COMP, to obtain a pulse width signal at its output E ₀ is compared with the common potential. This pulse width signal is a switch SW for inverting the polarity of the reference voltage.
Is connected back to the control.

FIG. 4 is a time chart for explaining this operation. For the sake of simplicity, assuming that the DC input voltage Ex = 0, the clock signal generating circuit CLK has + Ec and -Ec
Are sent alternately at a fixed cycle, so the output of the integrating circuit
e ₀ becomes like a bold line in the figure, and the output E _{0 of the} output terminal sends out a pulse width modulation output in which the positive period and the negative period are equal.
The output E of the output terminal ₀ is consistent with the waveform of the reference voltage ± Er from being feedback-connected to the polarity changeover switch SW of the reference voltage Er. In this figure, the input voltage Ex = 0 as described above, but when the input voltage Ex becomes negative, the output E ₀ has a longer positive period accordingly, and when the input voltage Ex becomes positive, the output E _{0 accordingly.} The positive period becomes shorter.

Such a conventional circuit requires two power supplies having equal absolute values to generate the reference voltage ± Er. That is, the power supply serving as the reference voltage source needs to have one end fixedly connected to the common potential in order to operate stably without being affected by induction noise or the like. Therefore, it is not a realistic design to adopt the configuration of inverting connection. Further, since the difference between the absolute values of the two power supplies becomes an output error as it is, it is necessary to set the absolute values of the two power supplies equally with high accuracy, and the reference voltage source becomes complicated and expensive.

In order to improve this, as a reference voltage source, there is provided one unipolar power supply having one side fixedly connected to a common potential, and a capacitor charged by the power supply, and the reference voltage source is provided with the one-polarity power supply. The reference voltage is sent from this power supply during the period of sending the voltage of the polarity, and this capacitor is connected to this power supply to charge the battery.During the period of sending the voltage of the opposite polarity, the power supply is disconnected and the capacitor is connected to the opposite polarity Then, a technique of sending out the voltage charged in the capacitor has been considered.

[Problems to be solved by the invention]

This technique is an excellent circuit that can generate a reference voltage having the same positive and negative absolute values by using a unipolar power supply. However,
Depending on the value of the input voltage that is the modulation signal, the pulse width during the period of sending a voltage of one polarity is shortened, and the capacitor may be discharged due to polarity reversal before the capacitor is fully charged. I do. In this case, an error occurs in the absolute value of the positive and negative reference voltages, which results in an error in the output pulse width, and the output pulse width does not correspond to the input voltage.

The present invention is an improvement of the present invention. Even if the output pulse width that changes according to the value of the input signal becomes short, the capacitor can be sufficiently charged and a reference voltage having the same positive and negative absolute values is generated. It is an object of the present invention to provide a pulse width modulation circuit which can perform error-free operation.

[Means for solving the problem]

The present invention is characterized in that a capacitor is forcibly connected to a power supply and charged for a period required for charging the capacitor regardless of the value of the input voltage. Further, a buffer amplifier is provided in the output circuit of the reference voltage source, and the switching means is
It is composed of a CMOS circuit. CMOS can also be used for the capacitor.

[Action]

A power supply whose one side is fixedly connected to a common potential is stable, and since it is a single power supply, an operation such as adjusting a difference in absolute value is not required. During the period of generating a voltage having the same polarity as that of the single power supply, the reference voltage is directly transmitted from the power supply. During this period, a capacitor is connected to this power supply to allow sufficient charge. During the next period of generating a voltage of the opposite polarity, the terminal connected to the common potential of the capacitor is reversed, and the charging voltage of the capacitor is transmitted as a reference voltage of the opposite polarity. Therefore, the circuit for generating the voltage of the opposite polarity is significantly simplified.

In the circuit of the present invention, even if the output pulse width may be short, the capacitor is connected to the power supply for the minimum necessary time for charging the capacitor.

〔Example〕

FIG. 1 is a circuit diagram of a device according to an embodiment of the present invention. This circuit includes an input terminal for a DC voltage Ex which is a modulation signal, a reference voltage source for generating positive and negative reference voltages ± Er, and a clock signal generating circuit CLK for alternately generating positive and negative voltages ± Ec in a constant cycle.
And the terminal voltage Ex, the output voltage of the reference voltage source ± E
r, an addition circuit composed of three resistors R ₁ R ₂ R ₃ for adding the output voltage ± Ec of the clock signal generation circuit, and an integration circuit S for integrating the addition voltage of the addition circuit as an input.
A comparison circuit COMP for comparing the output of the integration circuit S with a reference potential (here, a common potential); and switching means SW for switching the output polarity of the reference voltage source according to the output of the comparison circuit COMP. .

Here, as a feature of the present invention, the reference voltage source includes a unipolar power supply Er whose one end is fixedly connected to a common potential, and one capacitor C ₀ whose both ends are connected to the switching means. the switching means, delivering the reference voltage source is charged by connecting the capacitor C ₀ is the period for sending the voltage of the one polarity to the power supply Er, the capacitor C ₀ is the period for sending the opposite polarity The discharge is performed by inverting connection to the terminal. Reference voltage ± Er is supplied from the resistor R ₂ via the buffer circuit BA.

Further, the output of the clock signal generating circuit CLK has a pulse generating circuit MM for generating a short pulse in synchronization with the output.
The switching means includes a logical sum circuit OR, and by taking the logical sum of the output of the pulse generation circuit MM and the output voltage E ₀ , the pulse width of the output E _{0 that} changes according to the voltage Ex of the input terminal is obtained. though, the output period of the pulse generating circuit MM has a structure to sufficiently charged by forcibly connect the capacitor C ₀ to the power Er.

This will be described in more detail. FIG. 2 is a time chart for explaining the operation of the circuit of this embodiment. FIG. 2A shows a case where the input voltage Ex, which is a modulation signal, is zero. The clock signal generation circuit CLK continues to generate the periodic voltage ± Ec, and when the reference voltage ± Er is added to the periodic voltage ± Ec and input to the integration circuit S, the output e ₀ of the integration circuit S becomes the output e ₀ of FIG. ). The integrating circuit S has a negative input. Output E ₀ coincides with the waveform of the reference voltage ± Er from being fed back to the switching means SW. Thus when the input voltage Ex = 0, the waveform of the output E ₀ is a positive period and the negative period substantially equal.

Now the input voltage Ex is a positive voltage, the positive period negative duration becomes longer in the output E ₀ becomes shorter. FIG. 2 (b)
Fig. 2 (c) shows a state where the input voltage Ex becomes almost equal to its positive limit + Er, and Fig. 2 (c) shows a state where the input voltage Ex becomes equal to its negative limit -Er.

Here, the switching means SW will be described.
SW is constituted by a CMOS circuit. The state of each switch in FIG. 1 is a state in which a positive voltage is transmitted as a reference voltage. At this time, the output of the power supply Er is applied to the input of the buffer circuit BA, and a voltage + Er equal to the output is sent out.
When in accordance with the output of the comparison circuit COMP each switch of the switching means SW is inverted simultaneously, power Er is in a state of being opened, the capacitor C ₀ voltage buffer circuit which is charged to the BA
Is supplied to the input. At this time, since connected positive terminal of the capacitor C ₀ is the common potential is the terminal on the negative side is applied to the buffer circuit BA, the potential becomes -Er, also the output voltage of the buffer circuit BA becomes -Er.

The operation of the pulse generation circuit MM will be described with reference to FIG.
Alternatively, when the positive period of the output E ₀ is long as shown in FIG. 3C, the capacitor C ₀ is sufficiently charged because the capacitor C ₀ is connected to the power supply Er over this positive period. The output E ₀ is inverted and the capacitor C ₀
When disconnected from the terminal, its terminal voltage is Er. However, the input voltage Ex as shown in FIG. 2 (b) becomes positive, the positive period of the output voltage E ₀ becomes shorter the shorter the charge time of the capacitor C _0, before the terminal voltage reaches Er In some cases. In this example circuit,
It provided a pulse generating circuit MM To prevent this, a short time immediately before the clock signal rises from the voltage -Ec to + Ec tp only sends a pulse, overlapping the pulse output E ₀ by the OR circuit OR, the time tp Even when the output E ₀ disappears on the scale, the capacitor C ₀ is forcibly connected to the power supply Er.

Time tp capacitor C ₀ is set to the conduction resistance values and the switch circuit of the capacitor C ₀ to be sufficient time required for charging. This configuration, disconnected it is eliminated while the capacitor C ₀ is not sufficiently charged.
As it can be seen from Figure 2, the time tp is no problem if included in FIG. 2 (a) or time capacitor C _0, as in FIG. (C) is connected to the original power Er ,
To be longer than the time T ₁ illustrated as shown in FIG. 2 (b), the time is longer than this time T ₁ is not available for the output pulse width modulated signal. That is, the input voltage Ex
Is a positive value and its value is close to + Er, the voltage range that can be transmitted is slightly narrowed.

However, the use range of the input voltage Ex, the value of the capacitor C _0, and the like conduction resistance value of the input constants and the switch circuit of the buffer circuit BA, a time sufficient to charge the capacitor C ₀ can always be set in one cycle With such a setting, the pulse generation circuit MM and the OR circuit OR are unnecessary.

〔The invention's effect〕

As described above, according to the present invention, the circuit constituting the reference voltage source can be realized by a unipolar power supply having one end fixedly connected to a common potential, so that the operation is stable and the simple configuration is achieved. It can be. Compared with the case where two power supplies are provided, there is no need to adjust the voltage error between the two power supplies, and the number of manufacturing steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention. FIG. 2 is a time chart for explaining the operation of the embodiment circuit. FIG. 3 is a circuit diagram of a conventional example. FIG. 4 is an operation time chart of a conventional circuit diagram. Ex: input DC voltage that is a modulation signal, S: integrating circuit,
COMP: Comparison circuit, CLK: Clock signal generation circuit, SW
... Switching means.

Claims (1)

(57) [Claims] An input terminal for a DC voltage which is a modulation signal, a positive / negative reference voltage source having an equal absolute value, a clock signal generating circuit for alternately generating a positive / negative voltage at a constant period, a voltage at said terminal, An adding circuit for adding the output voltage of the reference voltage source and the output voltage of the clock signal generating circuit, an integrating circuit for integrating the added voltage of the adding circuit, a comparing circuit for comparing the output of the integrating circuit with a reference potential; Switching means for switching the output polarity of the reference voltage source according to the output of the comparison circuit, wherein the reference voltage source includes a unipolar power supply having one end fixedly connected to a common potential, and a capacitor. The switching means connects the capacitor to the power supply during the period in which the reference voltage source sends out the voltage of one polarity and charges the capacitor, and sends out the capacitor in the period of sending out the opposite polarity. A feedback pulse width modulation circuit including a circuit for inverting and discharging a pulse signal, a pulse generation circuit for generating a short pulse in synchronization with an output of the clock signal generation circuit, A feedback pulse width modulation circuit, comprising means for forcibly connecting and charging the capacitor to the power supply regardless of the voltage of the input terminal during the output period.