JP2973525B2 - Field effect transistor logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor logic circuit, and more particularly to a bias current temperature compensation circuit for a laser diode driving IC.

[0002]

2. Description of the Related Art A GaAs semiconductor has several times faster electron mobility than Si, and a semi-insulating substrate can be easily obtained. Vigorous R & D has been conducted in various places because of the idea that high-speed logic operation is possible. Some GaAs semiconductors have begun to be marketed, and particularly, an SSI for ultrahigh-speed optical communication of 10 Gbps or more, which is required for the next optical communication system, is expected.

As shown in FIG. 2, the optical communication system converts an electric signal into an optical signal with a laser diode 3, transmits the converted signal using an optical fiber 5, and converts the electric signal into an electric signal again with an avalanche photodiode 6. However, to drive the laser diode in this system, a constant threshold current and modulation current are required.

[0004] The threshold current of a laser diode tends to increase as the temperature rises due to heat generation of the laser diode or the like. To obtain a constant optical output even when the temperature fluctuates, the threshold current fluctuates. It is necessary to control the bias current.

An IC 7 for driving this laser diode
Supplies a laser diode 3 with a modulation current composed of a differential circuit 1 and a bias circuit 2 and biased to a constant current as shown in FIG. 3, and the gate of the FET of the bias circuit monitors the optical output of the laser diode. A method of controlling the light output by increasing the gate voltage when the light output decreases and decreasing the gate voltage when the light output increases.

In FIG. 3, reference numerals 11, 12, 13, and 14 denote depletion type n-channel MESFETs, and reference numeral 15 denotes a resistor as a level shift element. The drain electrode of the FET 11 is connected to the power supply terminal 100, the gate electrode is connected to the input terminal 20, the source electrode is connected to the node 41, the drain electrode of the FET 12 is connected to the output terminal 30, and the gate electrode is connected to the input terminal 21. Connected, the source electrode is connected to the contact 41, the drain electrode of the FET 13 is connected to the node 41, and the gate and source electrodes are connected to the power terminal 1
01, and these FETs 11, 12 and 1
Reference numeral 3 denotes the differential circuit 1. The FET 14 has a drain electrode connected to the output terminal 30, a gate electrode connected to the optical output feedback circuit 4, and a source electrode connected to the power supply terminal 101.

[0007]

In the laser diode driving circuit shown in FIG. 3, an element for monitoring the optical output in order to increase the bias current as the temperature of the laser diode rises, and to feed the element back to the driving circuit. Since these circuits are composed of hybrid circuits, the circuits are disadvantageous in that the cost is high and the size becomes large when the circuits are modularized.

An object of the present invention is to provide a field effect transistor logic circuit for driving a laser diode, which is equipped with a circuit for compensating a bias current according to a temperature change of the laser diode.

[0009]

According to the field effect transistor logic circuit of the present invention, a drain electrode is connected to a first power supply terminal, a gate electrode is connected to a first input terminal, and a source electrode is connected to a first node. A first MESFET, a drain electrode connected to the output terminal, a gate electrode connected to the second input terminal, a source electrode connected to the first node, and a drain electrode connected to the first node. And a third MESFET having a gate and a source electrode connected to a second power supply terminal, a drain circuit connected to the first output terminal, and a gate electrode connected to the second output terminal. A fourth MESFET having a source electrode connected to the second power supply terminal, a drain electrode connected to a third power supply, and a gate and a source electrode connected to the second node. A fifth connected MESFET, one end of which is connected to the second node, the other end of which is connected to the second power supply terminal connected to the load element, an anode connected to the second node, and a cathode connected to the second node. And a first diode connected to the power supply terminal.

[0010]

In the field effect transistor logic circuit according to the present invention, by obtaining the gate potential of the bias circuit from the reference voltage generating circuit, the voltage between the gate and the source of the bias circuit current reducing FET is increased as the temperature rises. If the current of the FET is increased and it is set so that it is controlled by the maximum voltage by the diode clamp above the maximum temperature in the laser diode standard, the fluctuation of the optical output due to the temperature rise is kept small, and the operating temperature exceeds the standard value. If this happens, the bias current can be suppressed and excess current can be prevented from flowing through the laser diode.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a field effect transistor logic circuit according to the present invention. In the present embodiment, the gate voltage of the current source FET 14 of the bias circuit is set such that the drain electrode is connected to the power supply terminal 102, the gate and the source electrode are connected to the node 42, one end of the FET 16 is connected to the node 42, and the other end is connected to the node 42. And a diode 17 connected to the power supply terminal 102. Other configurations are
The configuration is the same as that of the circuit shown in FIG. 3, and the same elements are denoted by the same reference numerals.

When the "H" level is input to the input terminal 20 and the "L" level is input to the input terminal 21,
When the “L” level is input to the input terminal 20 and the “H” level is input to the input terminal 21, the current flowing to the output terminal 30 increases. A bias current connected to the output terminal 30 is flowing. The amount of current at this time is determined by the gate bias of the FET 14.

The gate bias is obtained from the reference voltage generating circuit. The threshold voltage of the FET 16 shifts to the negative side due to the temperature rise, so that the voltage drop at the resistor 15 increases. By increasing the source-to-source voltage, the bias current can be increased as the temperature rises. At a temperature equal to or higher than the standard value, the diode 17 prevents the gate-source voltage exceeding a certain level from being applied to the FET 14, thereby making it possible to control the excess current so as not to flow through the laser diode. As a result, the light output of the laser diode driven by the amount of current of the bias circuit is not affected by the temperature fluctuation.

[0014]

In the field effect transistor logic circuit according to the present invention, since the gate bias of the bias circuit current source FET is obtained from the reference voltage generation circuit, it can be integrated on the chip of the laser diode driving circuit. It is possible to reduce the manufacturing cost as compared with the optical output control method of the ordinary optical communication system.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating an optical communication system.

FIG. 3 is a circuit diagram illustrating a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Differential circuit 2 Bias circuit 3 Laser diode 4 Optical output monitor circuit 5 Optical fiber 6 Avalanche photodiode 7 Laser diode drive IC 8 Preamplifier 11, 12, 13, 14, 16 Depletion type F
ET 15 Resistance 17 Diode 20, 21 Input terminal 30 Output terminal 41, 42 Node 100, 101, 102 Power supply terminal

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H01S 3/18 H03K 17/687 H03K 17/78 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. A first MESFET having a drain electrode connected to a first power supply terminal, a gate electrode connected to a first input terminal, a source electrode connected to a first contact, and a drain electrode connected to an output terminal. And a second electrode having a gate electrode connected to the second input terminal and a source electrode connected to the first contact.
And a third MESFET having a drain electrode connected to the first contact and a gate and source electrode connected to a second power supply terminal, and a drain electrode connected to the first output terminal. Connected and the gate electrode
A fourth MESFET having a source electrode connected to the second power supply terminal and a fifth MESFET having a drain electrode connected to the third power supply and a gate and source electrode connected to the second node. And a load element having one end connected to the second node and the other end connected to the second power terminal, an anode connected to the second node, and a cathode connected to the second power terminal. And a reference voltage generation circuit comprising a first diode.