JP2972262B2 - Communication control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device, and more particularly to a communication control device that selects and processes one interrupt from a plurality of lines.

[Conventional technology]

Conventionally, this type of communication control apparatus has been pre-assigned an address according to the mounting position of the line adapter so that the address of the line adapter is determined by the position where the line adapter is mounted, and performs communication in the order of the address values. The control unit common unit reads the status register inside the line adapter, detects whether the processing request flag is set based on the contents of the status register, and if the flag is set, performs processing corresponding to that flag to the line adapter. I was going to.

[Problems to be solved by the invention]

The above-described conventional communication control device performs an interrupt process from a line according to a fixed priority regardless of the traffic amount. Therefore, when many lines are connected, underrun / overrun due to waiting for a high-traffic line is waited. There is a disadvantage that overrun occurs.

[Means for solving the problem]

A communication control device according to the present invention includes a reception buffer for temporarily storing reception data converted into parallel data, a buffer amount detection circuit for detecting an amount of data stored in the reception buffer, and an interruption of a line interrupt. Data stored in the reception buffer, having a priority control circuit for performing priority control and a line address output circuit for outputting a line address when an interrupt from the line is selected with priority, for each line adapter; It is characterized in that the priority of interruption from the line adapter is changed according to the amount.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

The communication control unit common unit 6 includes a control unit 61 for controlling line adapters 71 and 72 connected thereto, a memory unit 62 for temporarily storing data to be transmitted and received, and the like.

The control circuit 611 in the control unit 61 activates the counter 612 upon receiving an interrupt signal from the priority control circuits 714, 724 in the line adapters 71, 72, and also outputs the line address output circuits 715, 725.
When the line address is input from the counter, the counter 612 is reset, and 9-bit address information necessary for reading the internal registers (not shown) of the general-purpose receivers / transmitters 711 and 721 in the rotary adapters 71 and 72 is output to the address bus 4. I do. The counter 612 is a 4-bit binary down counter which is started by the control circuit 611 and counts down from a maximum value 1111 (2) which can be realized by a 4-bit binary number at regular intervals, and transfers the value to the buffer amount bus 2. Output.

Each of the line adapters 71 and 72 accommodates one line and is connected to the communication control unit common unit 6.

The data bus 1 includes a communication control unit common unit 6 and a line adapter.
This is an 8-bit bus for exchanging data with 71 and 72.

The buffer amount bus 2 is a bus for broadcasting the 4-bit division value output from the counter 612 in the control unit 61.

The interrupt line address bus 3 is a 6-bit bus from which the line address selected by the priority control is output from the line address output circuits 715 and 725.

The address bus 4 is a bus from which a 9-bit address sent from the communication control device common unit 6 to the line adapters 71 and 72 is output. The 9-bit address communicated on the address bus 4 is classified into 5 bits for identifying a line adapter and 4 bits for designating a register inside the line adapter.

The interrupt signals from the priority control circuits 714 and 724 of the line adapters 71 and 72 are output from the open collector to the interrupt signal line 5, ORed, and sent to the control circuit 611 in the communication control unit common unit 6.

The general-purpose receiver / transmitters 711 and 721 are circuits for performing serial / parallel conversion of transmission / reception data.

The reception buffers 712 and 722 are first-in / first-out buffers that temporarily store the reception data converted into parallel data by the general-purpose receivers / transmitters 711 and 721.

The buffer amount detection circuits 713, 723
Is a circuit for detecting the amount of data stored in the receiving buffer 712, 722, dividing the data amount into 16 levels, and outputting the divided 4-bit division values to the signal lines 81, 82.

The priority control circuits 714 and 724 are circuits that perform interrupt priority control of the line adapters 71 and 72. The priority control circuits 714, 72
4 works as follows. Controls an interrupt that occurs when the rotating adapters 71 and 72 receive data from the line and transfer it to the memory unit 62 in the communication control unit common unit 6 (hereinafter, the interrupt is referred to as an “interrupt due to reception”). When receiving, the reception buffer 712,7
When the division value is input, the four bits obtained by dividing the number of data in 22 into 16 steps are started, and the four-bit division value is held, and at the same time, the interrupt signal is sent to the control circuit 611 by the open collector output. . The control circuit 611 thereby controls the counter
Activate 612, and read the buffer amount bus 2 from the counter 612.
When the value sent through the Priority Control Circuits 714 and 724 matches the value held by the Priority Control Circuits 714 and 724, the Priority Control Circuits 714 and 724 send a signal to activate the line address output circuit with a three-state output. On the other hand, in the case of an interrupt other than the interrupt caused by reception, the priority control circuits 714 and 724 are activated by the line adapter control circuits 717 and 727, and unlike the case of the interrupt caused by reception, the interrupt signal is sent to the control circuit 611. At the same time, the line address output circuits 715 and 725 are activated.

In order to prevent a plurality of priority control circuits from simultaneously activating the line address output circuit, priorities are determined in descending order of the line addresses according to previously assigned line addresses, and a priority control circuit of a certain line adapter is connected thereto. When the line address output circuit is activated,
At the same timing, the third priority control circuit in another line adapter having a lower priority order is set so that the line address output circuit connected thereto is not activated.
A signal that disables the state output and sets the state to a high impedance state is transmitted.

The line address output circuits 715 and 725 are circuits that output line addresses uniquely set for each line by a switch or the like, and output the line address output circuits 715 and 725 to the interrupt line address bus 3 only when the line is selected. Output.

The address decoders 716 and 726 are provided in the communication controller common unit 6.
Is a circuit for decoding the address sent when reading / writing the registers in the line adapters 71 and 72.

The line adapter control circuits 717 and 727
This is a circuit that performs overall control.

The line adapter control circuits 717 and 727 operate as follows. The line adapter control circuits 717 and 727 constantly monitor the status register in the general-purpose receiver / transmitter 711 and 721, and
When an interrupt occurs in the 721 and a flag is set in the status register, it activates the buffer amount detection circuits 713 and 723 if it is an interrupt due to reception, and if it is an interrupt other than an interrupt due to reception, Control circuit 714,724
Start up. Also, it receives decoded signals from the address decoders 716 and 726, and outputs and reports the contents to registers in the general-purpose receivers / transmitters 711 and 721 to the control circuit 611 and outputs received data to the reception buffers 712 and 722.

In the case of an interrupt from the line adapters 71 and 72, the control circuit 611 is controlled based on the line address sent from the line address output circuits 715 and 725 in the line adapters 71 and 72 to the control circuit 611 in the communication controller common unit 6. The 9-bit address is sent to the address decoders 716 and 726, the register in the line adapter specified by the 9-bit address is read, and the interrupt factor is recognized based on the flag in the register.

〔The invention's effect〕

As described above, the present invention has a circuit for detecting the amount of data in the buffer for each line, and is capable of processing a line having a large amount of data preferentially with respect to an interruption due to reception. It is possible to suppress the occurrence of overrun during operation and to provide a communication control device with good cost / performance.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1 ... Data bus, 2 ... Buffer amount bus, 3 ... Interrupt line address bus, 4 ... Address bus, 5 ... Interrupt signal line, 6 ... Communication control unit common part, 71,72 ... Line adapter 711,721 general-purpose receiver / transmitter 712,722 reception buffer 713 723 buffer amount detection circuit 714 724 priority control circuit 715 725 line address output circuit 716 726 address decoder 717
727 …… Line adapter control circuit, 81,82 …… Signal line, 61…
... Control unit, 611 ... Control circuit, 612 ... Counter, 62 ...
Memory section.

Continuation of the front page (56) References JP-A-1-117549 (JP, A) JP-A-1-17449 (JP, A) JP-A-63-94745 (JP, A) JP-A-63-59140 (JP, A) , A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 29/02

Claims (1)

(57) [Claims] A reception buffer for temporarily storing reception data converted into parallel data; a buffer amount detection circuit for detecting an amount of data stored in the reception buffer;
A plurality of line adapters each including a priority control circuit that performs priority control of an interrupt from a line, and a rotation address output circuit that outputs a own line address when an interrupt from the own line is selected with priority; A control circuit that receives an interrupt signal from the priority control circuit, starts a counter, and inputs a line address from the line address output circuit, resets the counter and outputs address information for reading received data from the line, and starts the control circuit. A communication unit including a control unit including a counter for outputting the count value to the priority control circuit and a memory unit for temporarily storing data to be transmitted / received through the line. Communication control device.